CN113193871B - Sampling network modeling circuit based on buffer architecture - Google Patents
Sampling network modeling circuit based on buffer architecture Download PDFInfo
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- CN113193871B CN113193871B CN202110460837.4A CN202110460837A CN113193871B CN 113193871 B CN113193871 B CN 113193871B CN 202110460837 A CN202110460837 A CN 202110460837A CN 113193871 B CN113193871 B CN 113193871B
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- H—ELECTRICITY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Abstract
The invention discloses a sampling network modeling circuit based on a buffer architecture, which comprises an edge equivalent parasitic circuit, an input buffer and an in-core equivalent parasitic circuit which are sequentially connected, wherein the edge equivalent parasitic circuit is used for simulating internal resistance of a signal source, bonding wire parasitic inductance and parasitic resistance introduced by encapsulation and parasitic capacitance of a chip PAD; the in-core equivalent parasitic circuit is used for simulating parasitic resistance introduced by the in-core layout wiring and the in-core sample hold circuit; and the edge equivalent parasitic circuit, the input buffer and the nuclear equivalent parasitic circuit which are connected in sequence jointly realize signal sampling. The sampling network modeling circuit is divided into the edge equivalent parasitic circuit, the input buffer and the nuclear equivalent parasitic circuit, the implementation is simple, and the transfer function of the input buffer is optimized through the equivalent modeling of the three circuits, so that the transfer function of the whole ADC sampling network is optimized, the maximum bandwidth and linearity of an input signal are realized, and the whole performance of the ADC is improved.
Description
Technical Field
The invention belongs to the technical field of circuit electronics, and particularly relates to a sampling network modeling circuit based on a buffer architecture.
Background
With the rapid development of wireless communication technology in recent years, the design requirements of Analog-to-Digital Converter (ADC) are increasing, and the ADC has a requirement of higher accuracy and higher speed. With high speed and high accuracy, it is generally necessary to add an input buffer to isolate the input signal source from the intra-core sampling network to reduce kickback noise of the intra-core sampling network and to provide a low-impedance output node. However, the design of the current input buffer does not comprehensively consider the analog bandwidth requirement of the ADC and the interface matching between the signal source and the ADC, and too high analog bandwidth increases difficulty in input matching of the buffer, is complex to implement, and cannot guarantee the maximum bandwidth and linearity of the input signal.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a sampling network modeling circuit based on a buffer architecture.
One embodiment of the invention provides a sampling network modeling circuit based on a buffer architecture, which comprises an edge equivalent parasitic circuit, an input buffer and an in-core equivalent parasitic circuit which are sequentially connected, wherein,
the edge equivalent parasitic circuit is used for simulating the internal resistance of a signal source, the parasitic inductance and the parasitic resistance of a bonding wire led in by encapsulation and the parasitic capacitance of a chip PAD;
the in-core equivalent parasitic circuit is used for simulating parasitic resistance introduced by the in-core layout wiring and the in-core sample hold circuit;
and the edge equivalent parasitic circuit, the input buffer and the in-core equivalent parasitic circuit which are sequentially connected jointly realize signal sampling.
In one embodiment of the invention, the edge equivalent parasitic circuit includes a signal source V IN Internal resistance R of signal source S Parasitic inductance L of bonding wire BONDING Parasitic resistance R of bonding wire BONDING PAD parasitic capacitance C PAD Impedance matching resistor R T Wherein, the method comprises the steps of, wherein,
the signal source V IN The internal resistance R of the signal source S The bonding wire parasitic inductance L BONDING The bonding wire parasitic resistance R BONDING Sequentially connected with the signal source V IN The other end of the bonding wire is groundedResistor R BONDING And the other end of the PAD parasitic capacitance C PAD Upper stage board of (2), the impedance matching resistor R T Is connected with the input buffer, the PAD parasitic capacitance C PAD Lower plate of the impedance matching resistor R T The other end of which is grounded.
In one embodiment of the invention, the in-core equivalent parasitic circuit includes a layout trace parasitic resistance R PAR Layout wiring parasitic capacitance C PAR An in-core sample-and-hold circuit, wherein,
layout wiring parasitic resistor R PAR One end of the layout wiring parasitic resistance R is connected with the input buffer PAR The other end of (2) is connected with the layout wiring parasitic capacitance C PAR The upper-level board of the chip is connected with the in-core sample-and-hold circuit, and the layout wiring parasitic capacitance C PAR Is grounded.
In one embodiment of the invention, the in-core sample-and-hold circuit includes a sample switch on-resistance R IN Parasitic resistor array R REF Sampling capacitor C S Parasitic capacitance C P On-resistance R of reset signal CM Signal source V CM Wherein, the method comprises the steps of, wherein,
the on-resistance R of the sampling switch IN One end of (1) is connected with the layout wiring parasitic capacitance C PAR Is connected with the upper-level plate of the sampling switch, and the on-resistance R of the sampling switch IN And the other end of the parasitic resistor array R REF Is one end of the sampling capacitor C S Upper-stage board of (C), the parasitic capacitance C P Upper level board connection of the parasitic resistor array R REF Is connected with the reference voltage V REF The sampling capacitor C S Lower plate and signal output end of the circuit, the reset signal on-resistance R CM One end of the reset signal is connected with the on-resistance R CM Is connected with the other end of the signal source V CM Is connected to one end of the parasitic capacitance C P Lower plate of said signal source V CM The other end of which is grounded.
In one embodiment of the invention, the parasitic resistor array R REF For simulating the reference voltage V REF Parasitic resistance introduced by the trace.
In one embodiment of the invention, the parasitic resistor array R REF Comprising parasitic resistance R REF1 ～R REFN The reference voltage V REF Including a reference voltage V REF1 ～V REFN The parasitic resistance R REF1 ～R REFN One end of each of the capacitors is connected with the sampling capacitor C S Upper-level plate connection of said parasitic resistance R REF1 ～R REFN The other ends of the voltage transformer are correspondingly connected with the reference voltage V REF1 ～V REFN 。
In one embodiment of the present invention, the input buffer is a source follower structure based buffer.
In one embodiment of the present invention, the source follower structure-based buffer includes a transistor M 1 A current source Idc, wherein,
the transistor M 1 The gate of the transistor M is connected with the edge equivalent parasitic circuit 1 The drain of (2) is connected to the supply voltage VDD, the transistor M 1 And the source electrode of the current source Idc is connected with one end of the in-core equivalent parasitic circuit and the other end of the current source Idc is grounded.
In one embodiment of the invention, the signal source V CM Is one half of the supply voltage VDD.
Compared with the prior art, the invention has the beneficial effects that:
the sampling network modeling circuit based on the buffer architecture provided by the invention is divided into the edge equivalent parasitic circuit, the input buffer and the nuclear equivalent parasitic circuit, is simple to realize, can deduce the whole transfer function of the ADC sampling network through equivalent modeling of the three circuits, optimizes the transfer function of the input buffer by means of the model, and further optimizes the transfer function of the whole ADC sampling network so as to realize the maximum bandwidth and linearity of an input signal and improve the whole performance of the ADC.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a sampling network modeling circuit based on a buffer architecture according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a sampling network practical model based on a buffer architecture according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a sampling network modeling circuit based on a buffer architecture according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of another sampling network modeling circuit based on a buffer architecture according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a sampling network modeling circuit based on a buffer architecture according to an embodiment of the present invention. The embodiment provides a sampling network modeling circuit based on a buffer architecture, which comprises:
the device comprises an edge equivalent parasitic circuit, an input buffer and an in-core equivalent parasitic circuit which are sequentially connected, wherein the edge equivalent parasitic circuit is used for simulating the internal resistance of a signal source, the parasitic inductance and the parasitic resistance of a bonding wire led in by encapsulation and the parasitic capacitance of a chip PAD; the in-core equivalent parasitic circuit is used for simulating parasitic resistance introduced by the in-core layout wiring and the in-core sample hold circuit; and the edge equivalent parasitic circuit, the input buffer and the nuclear equivalent parasitic circuit which are connected in sequence jointly realize signal sampling. According to the embodiment, the sampling network is subjected to equivalent modeling, the transfer function of the input buffer is optimized by means of the modeling circuit to optimize the transfer function of the whole sampling network, and the whole transfer function of the ADC sampling network is deduced, so that the maximum bandwidth and linearity of an input signal are realized, and the whole performance of the ADC is improved.
Further, the edge equivalent parasitic circuit of the embodiment comprises a signal source V IN Internal resistance R of signal source S Parasitic inductance L of bonding wire BONDING Parasitic resistance R of bonding wire BONDING PAD parasitic capacitance C PAD Impedance matching resistor R T 。
Specifically, referring to fig. 2 and 3, fig. 3 is a specific circuit schematic diagram of a sampling network modeling circuit based on a buffer architecture according to an embodiment of the present invention, and fig. 2 is a schematic diagram of a sampling network actual model structure based on a buffer architecture according to an embodiment of the present invention, where circuit connection of an edge equivalent parasitic circuit of the embodiment specifically includes: signal source V IN Positive terminal of (2), internal resistance of signal source R S Parasitic inductance L of bonding wire BONDING Parasitic resistance R of bonding wire BONDING Sequentially connected with a signal source V IN Is grounded at the negative end of the bonding wire parasitic resistance R BONDING And the other end of the capacitor (C) is connected with the PAD parasitic capacitance PAD Upper-stage board of (a), impedance matching resistor R T Is connected with the input buffer, PAD parasitic capacitance C PAD Lower plate of (a), impedance matching resistor R T The other end of (C) is Grounded (GND). As shown in FIG. 2, the present embodiment can make the input signal source equivalent to an ideal signal source V IN And internal resistance R of signal source S Is connected in series with signal source V IN When connecting the chip pins and packaging the chip, bonding wires are used for connecting the chip pins with PAD on the packaging piece DIE, and the bonding wire model can be equivalent to the parasitic inductance L of the bonding wires BONDING Parasitic resistance R of bonding wire BONDING Series connection, impedance matching resistor R T Is added inside the chip for impedance matching, and PAD can be equivalent to a parasitic capacitance C to the ground GND PAD To form an edge equivalent parasitic circuit.
Further, the nuclear equivalent parasitic circuit of the embodiment comprises a layout wiring parasitic resistor R PAR Layout wiring parasitic capacitance C PAR And an in-core sample-and-hold circuit.
Specifically, referring to fig. 2 and 3, the circuit connection of the equivalent parasitic circuit in the core of the present embodiment is specifically: layout wiring parasitic resistor R PAR One end of (2)Is connected with an input buffer, and is provided with a layout wiring parasitic resistor R PAR The other end of (2) and the layout wiring parasitic capacitance C PAR Upper-level board and in-core sample-and-hold circuit connection, layout wiring parasitic capacitance C PAR Is grounded. As shown in FIG. 2, the signal of the embodiment is realized from the output end of the input buffer to the in-core sample-and-hold circuit, in particular, the layout wiring can be equivalent to a bridged layout wiring parasitic resistance R PAR Layout wiring parasitic capacitance C with ground GND PAR Specific layout wiring parasitic resistor R PAR Layout wiring parasitic capacitance C PAR The values of (2) are related to the layout practice layout.
Further, the in-core sample-and-hold circuit of the present embodiment includes a sampling switch on-resistance R IN Parasitic resistor array R REF Sampling capacitor C S Parasitic capacitance C P On-resistance R of reset signal CM Signal source V CM 。
Specifically, referring to fig. 4, fig. 4 is a specific circuit schematic diagram of another sampling network modeling circuit based on a buffer architecture according to an embodiment of the present invention, and the circuit connection of the sample-hold circuit in the core of this embodiment is specifically: sampling switch on-resistance R IN One end of (1) and layout wiring parasitic capacitance C PAR Is connected with the upper plate of the sampling switch and is used for sampling the on-resistance R IN And parasitic resistor array R REF One end of (C) sampling capacitor S Upper-level plate of (C), parasitic capacitance (C) P Upper-level board connection of parasitic resistor array R REF Is connected with the reference voltage V REF Sampling capacitor C S Lower plate of (a) and signal output terminal V O On-resistance R of reset signal CM One end of the reset signal is connected with the on-resistance R CM Is connected with the other end of the signal source V CM Is connected with the positive terminal of the parasitic capacitor C P Lower plate of (2), signal source V CM The negative terminal of (2) is grounded. The sampling switch of the sampling network of the embodiment is conductive in the sampling stage and can be equivalent to a sampling switch on-resistance R IN Signal source V CM Can be equivalent to a reset signal on-resistance in the sampling stageR CM Sampling capacitor C S Parasitic capacitance C as actual capacitance P Equivalent to sampling capacitor C S Corresponding parasitic capacitance, parasitic resistance array R REF Equivalent to reference voltage V REF Parasitic resistance introduced by wiring, specifically, parasitic resistance array R of this embodiment REF Comprising parasitic resistance R REF1 ～R REFN Reference voltage V REF Including a reference voltage V REF1 ～V REFN Parasitic resistance R REF1 ～R REFN One end of (a) is connected with the sampling capacitor C S Upper-level board connection of (1), parasitic resistance R REF1 ～R REFN The other ends of (a) are respectively connected with a reference voltage V REF1 ～V REFN 。
Further, the input buffer of the present embodiment is a source follower structure based buffer.
Specifically, referring to fig. 3 again, the architecture of the sampling of the present embodiment is a buffer based on a source follower structure, and the corresponding equivalent circuit may include a transistor M 1 A current source Idc, in which the transistor M 1 PAD parasitic capacitance C in gate and edge equivalent parasitic circuit PAD Upper-level plate connection of transistor M 1 The drain electrode of (2) is connected with the power supply voltage VDD, the transistor M 1 Layout parasitic resistor R in source electrode of (1) and positive end of current source Idc and in nuclear equivalent parasitic circuit PAR Is connected to the negative terminal of the current source Idc to Ground (GND). Wherein, the signal source V CM The voltage value of (2) is one half of the power supply voltage VDD.
The present embodiment assumes that the edge equivalent parasitic transfer function is F(s), the input buffer transfer function is B(s), the in-core equivalent parasitic transfer function is L(s), and the entire network transfer function is H(s). Wherein, the resistance R in all circuits is represented as R in s domain, the capacitance C is represented as 1/Cs in s domain, the inductance L is represented as Ls in s domain, and the resistance R, the capacitance C and the inductance L are only used for explaining the representation forms of all parts in the circuits in s domain and do not represent the resistance in the circuits. The edge equivalent parasitic circuit transfer function(s) of this embodiment is designed as a two pole low pass transfer function, specifically expressed as:
the transfer function L(s) of the equivalent parasitic circuit in the core of the embodiment can be designed and simplified into an RC low-pass filter, which is specifically expressed as:
wherein R 'represents the equivalent resistance of all the resistances in the in-core equivalent parasitic circuit, and C' represents the equivalent inductance of all the inductances in the in-core equivalent parasitic circuit.
The transfer function H(s) of the whole network of the present embodiment can be expressed as a cascade system of a third order low pass filter and an input buffer. Substituting the actual circuit parameters to calculate three poles of the third-order filter, and then reasonably designing the transfer function of the input buffer as B(s) according to the size distribution of the three poles, wherein the transfer function B(s) of the input buffer can be optimized by modifying the specific architecture and transistor size of the buffer, the specific transfer function is not limited, so that the transfer function H(s) of the whole sampling network is optimized, and the transfer function H(s) of the whole sampling network is expressed as:
in summary, in the sampling network modeling circuit based on the buffer architecture provided in this embodiment, the sampling network modeling circuit is divided into the edge equivalent parasitic circuit, the input buffer and the in-core equivalent parasitic circuit, the implementation of integrated modeling by adopting the active and passive sampling networks is simple, and the path between the signal source and the ADC input terminal of the input signal is restored in a manner closest to the practical application through the equivalent modeling of the three circuits, so that the overall transfer function of the ADC sampling network can be deduced, and the transfer function of the input buffer is optimized by means of the model, so that the transfer function of the overall ADC sampling network is optimized, so as to achieve the maximum bandwidth and linearity of the input signal, and improve the overall performance of the ADC.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (7)
1. A sampling network modeling circuit based on a buffer architecture is characterized by comprising an edge equivalent parasitic circuit, an input buffer and an in-core equivalent parasitic circuit which are sequentially connected, wherein,
the edge equivalent parasitic circuit is used for simulating the internal resistance of a signal source, the parasitic inductance and the parasitic resistance of a bonding wire led in by encapsulation and the parasitic capacitance of a chip PAD;
the in-core equivalent parasitic circuit is used for simulating parasitic resistance introduced by the in-core layout wiring and the in-core sample hold circuit;
the edge equivalent parasitic circuit, the input buffer and the in-core equivalent parasitic circuit which are sequentially connected jointly realize signal sampling;
the nuclear equivalent parasitic circuit comprises a layout wiring parasitic resistor R PAR Layout wiring parasitic capacitance C PAR An in-core sample-and-hold circuit, wherein,
layout wiring parasitic resistor R PAR One end of the layout wiring parasitic resistance R is connected with the input buffer PAR The other end of (2) is connected with the layout wiring parasitic capacitance C PAR The upper-level board of the chip is connected with the in-core sample-and-hold circuit, and the layout wiring parasitic capacitance C PAR Is grounded;
the in-core sample hold circuit comprises a sampling switch on-resistance R IN Parasitic resistor array R REF Sampling capacitor C S Parasitic capacitance C P On-resistance R of reset signal CM Signal source V CM Wherein, the method comprises the steps of, wherein,
the on-resistance R of the sampling switch IN One end of (1) is connected with the layout wiring parasitic capacitance C PAR Is connected with the upper-level plate of the sampling switch, and the on-resistance R of the sampling switch IN And the other end of the parasitic resistor array R REF Is one end of the sampling capacitor C S Upper-stage board of (C), the parasitic capacitance C P Upper level board connection of the parasitic resistor array R REF Is connected with the reference voltage V REF The sampling capacitor C S Lower plate and signal output end of the circuit, the reset signal on-resistance R CM One end of the reset signal is connected with the on-resistance R CM Is connected with the other end of the signal source V CM Is connected to one end of the parasitic capacitance C P Lower plate of said signal source V CM The other end of which is grounded.
2. The sampling network modeling circuit based on a buffer architecture according to claim 1, wherein the edge equivalent parasitic circuit comprises a signal source V IN Internal resistance R of signal source S Parasitic inductance L of bonding wire BONDING Parasitic resistance R of bonding wire BONDING PAD parasitic capacitance C PAD Impedance matching resistor R T Wherein, the method comprises the steps of, wherein,
the signal source V IN The internal resistance R of the signal source S The bonding wire parasitic inductance L BONDING The bonding wire parasitic resistance R BONDING Sequentially connected with the signal source V IN The other end of the bonding wire is grounded, the parasitic resistance R of the bonding wire BONDING And the other end of the PAD parasitic capacitance C PAD Upper stage board of (2), the impedance matching resistor R T Is connected with the input buffer, the PAD parasitic capacitance C PAD Lower plate of the impedance matching resistor R T The other end of which is grounded.
3. The sampling network modeling circuit based on a buffer architecture according to claim 1, wherein the parasitic resistor array R REF For simulating the reference voltage V REF Parasitic introduced by wiringAnd (3) resistance.
4. The sampling network modeling circuit based on a buffer architecture according to claim 1, wherein the parasitic resistor array R REF Comprising parasitic resistance R REF1 ～R REFN The reference voltage V REF Including a reference voltage V REF1 ～V REFN The parasitic resistance R REF1 ～R REFN One end of each of the capacitors is connected with the sampling capacitor C S Upper-level plate connection of said parasitic resistance R REF1 ～R REFN The other ends of the voltage transformer are correspondingly connected with the reference voltage V REF1 ～V REFN 。
5. The buffer architecture based sampling network modeling circuit of claim 1, wherein the input buffer is a source follower structure based buffer.
6. The buffer architecture based sampling network modeling circuit of claim 5, wherein the source follower structure based buffer comprises a transistor M 1 A current source Idc, wherein,
the transistor M 1 The gate of the transistor M is connected with the edge equivalent parasitic circuit 1 The drain of (2) is connected to the supply voltage VDD, the transistor M 1 And the source electrode of the current source Idc is connected with one end of the in-core equivalent parasitic circuit and the other end of the current source Idc is grounded.
7. The sampling network modeling circuit based on a buffer architecture of claim 1, wherein the signal source V CM The voltage value of (2) is one half of the power supply voltage VDD.
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