CN113193041A - Structure of antimonide quantum well CMOS device and preparation method thereof - Google Patents
Structure of antimonide quantum well CMOS device and preparation method thereof Download PDFInfo
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- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 title claims abstract description 149
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 75
- 230000004888 barrier function Effects 0.000 claims abstract description 68
- 238000002955 isolation Methods 0.000 claims abstract description 39
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 13
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 13
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910005542 GaSb Inorganic materials 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910004205 SiNX Inorganic materials 0.000 claims 1
- 239000004047 hole gas Substances 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 238000001259 photo etching Methods 0.000 description 10
- 238000002791 soaking Methods 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005566 electron beam evaporation Methods 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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Abstract
The invention discloses a structure of an antimonide quantum well CMOS device and a preparation method thereof, belonging to the technical field of microelectronics. The device structure includes: a substrate; a buffer layer is arranged on the substrate; a p-channel antimonide quantum well layer and an n-channel antimonide quantum well layer are arranged on the buffer layer relatively and independently; and a passivation isolation layer is arranged between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer. The antimonide quantum well structure provided by the invention can reduce dislocation density caused by lattice mismatch through component regulation and control, and can effectively isolate the channel from a high-k gate medium through the barrier layer to form two-dimensional electron/hole gas on the surface of the channel, so that the mobility is improved, and the performance of a device is improved. The invention also provides a preparation method of the antimonide quantum well CMOS device, which realizes the epitaxial growth of the n-channel and p-channel materials of the same system.
Description
Technical Field
The invention belongs to the technical field of microelectronics, relates to a semiconductor device, and particularly relates to a structure of an antimonide quantum well CMOS device and a preparation method thereof.
Background
The feature size of the traditional Si channel MOSFET device is continuously reduced following Moore's law, and the comprehensive performance of the device, such as speed, power consumption and the like, approaches the physical limit. In order to maintain the continuous development of microelectronic technology, researchers consider a Si channel device with a new nanoscale structure, and meanwhile, the adoption of non-Si materials with higher mobility as an n channel and a p channel becomes an important research direction for improving the performance of the CMOS device.
The electron mobility of III-V compounds is more than ten times greater than Si and Ge, which drives the development of devices towards high frequency applications. GaAs, InGaAs and InP CMOS devices prepared by a series of methods are continuously reported, however, the hole mobility of the As-containing compound materials is not high, and the As-containing compound materials are required to be combined with Ge materials with high hole mobility to prepare the CMOS devices. Due to the fact that the difference between the lattice constant, the polarity and the thermal expansion coefficient of the Ge material and the As compound material is large, the growing difficulty and the process preparation difficulty of the epitaxial material are increased.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a structure of an antimonide quantum well CMOS device and a preparation method thereof. The structure effectively isolates the channel from the high-k medium through the barrier layer, and two-dimensional electron/hole gas is formed on the surface of the channel, so that the mobility is improved, and the performance of the device is improved. Meanwhile, the invention can realize the epitaxial growth of the n-channel and p-channel materials of the same system.
A first object of the present invention is to provide a structure of an antimonide quantum well CMOS device, comprising:
a substrate;
a buffer layer is arranged on the substrate;
a p-channel antimonide quantum well layer and an n-channel antimonide quantum well layer are arranged on the buffer layer relatively and independently;
the p-channel antimonide quantum well layer includes:
the first lower barrier layer, the first channel layer, the first isolating layer, the first upper barrier layer, the first interface control layer and the first cap layer are sequentially arranged on the buffer layer in a laminated mode from bottom to top; a first doping layer is also arranged in the first upper barrier layer;
the n-channel antimonide quantum well layer includes:
a second lower barrier layer, a second channel layer, a second isolation layer, a second upper barrier layer, a second interface control layer and a second cap layer which are sequentially arranged on the buffer layer in a laminated manner from bottom to top; a second doping layer is also arranged in the second upper barrier layer;
a passivation isolation layer is arranged between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well;
high-K gate dielectric layers are arranged on the first interface control layer and the second interface control layer;
a source electrode and a drain electrode are arranged on the first cap layer and the second cap layer;
and grid electrodes are arranged on the two high-K grid dielectric layers.
The second purpose of the invention is to provide a preparation method of the structure of the antimonide quantum well CMOS device, which comprises the following steps:
selecting a substrate material;
growing a buffer layer on the substrate;
preparing a p-channel antimonide quantum well layer, an n-channel antimonide quantum well layer and a passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer on a buffer layer;
respectively preparing a source electrode and a drain electrode on the first cap layer and the second cap layer;
respectively etching the first cap layer and the second cap layer to a first interface control layer and a second interface control layer, and then respectively preparing high-K gate dielectric layers on the first interface control layer and the second interface control layer;
and preparing a grid electrode on the two high-K grid dielectric layers to obtain the preparation of the antimonide CMOS device.
Compared with the prior art, the invention has the following beneficial effects:
in the antimonide quantum well CMOS device, the p channel and the n channel both adopt antimonide quantum well structures, the structure can reduce dislocation density caused by lattice mismatch through component regulation and control on one hand, and on the other hand, the channel is effectively isolated from a high-k gate medium through a barrier layer, and two-dimensional electron/hole gas is formed on the surface of the channel, so that the mobility is improved, the performance of the device is improved, and the mobility realized by the antimonide n or p channel quantum well structure is far greater than that of Si, Ge channel and GaAs system materials in the prior art.
The invention provides a preparation method of an antimonide quantum well CMOS device, which realizes the epitaxial growth of n-channel and p-channel materials of the same system and avoids the complex process problem of integrating the InGaAs material of an n-channel and the Ge material of a p-channel in the prior art.
The invention is based on that under the natural environment condition, the surface of an antimonide material has high activity, and the high interface state density Dit is caused by the Fermi level pinning effect of trap charges such as Sb-Sb polymer, Sb simple substance and the like>1012cm-2eV-1And the carrier scattering center is formed, so that the advantage of high mobility of an antimonide material cannot be exerted, and in the insulated gate process, an InAs thin layer is introduced to serve as an interface control layer, so that the formation of trapped charges such as Sb elements is avoided, and the interface state density is reduced.
According to the antimonide quantum well CMOS device, the p channel and the n channel are both of antimonide quantum well structures, and the application stability of the CMOS device in an integrated circuit is effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
The embodiment of fig. 1 provides a schematic diagram of an antimonide quantum well CMOS device structure.
Fig. 2 is a schematic flow chart of a method for manufacturing an antimonide quantum well CMOS device structure according to embodiment 1.
Fig. 3 is a schematic flow chart of a method for manufacturing an antimonide quantum well CMOS device structure according to embodiment 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The schematic diagram of the structure of the antimonide quantum well CMOS device provided by the invention is shown in figure 1 and comprises the following components:
a substrate 1;
the substrate 1 is provided with a buffer layer 2, and the thickness of the buffer layer is 1-3 mu m;
a p-channel antimonide quantum well layer 3 and an n-channel antimonide quantum well layer 4 are arranged on the buffer layer 2 relatively and independently;
the p-channel antimonide quantum well layer 3 includes:
sequentially laminated from bottom to top on the buffer layer 2
The first lower barrier layer 31 is made of AlGaSb material and has a thickness of 50 to 100nm,
The first channel layer 32 is made of InGaSb material and has a thickness of 10-20 nm,
The first isolation layer 33 is made of AlGaSb material and has a thickness of 2-5 nm,
A first upper barrier layer 34 made of AlGaSb material and having a thickness of 5-8 nm,
The first interface control layer 35 is made of InAs material with a thickness of 1-2 nm,
The first cap layer 36 is made of InSb or GaSb materials, and the thickness of the first cap layer is 5-20 nm;
a first doped layer 341 is further disposed in the first upper barrier layer 34, the first doped layer 341 is a Be material and has a doping concentration of 1.0 × 1018～1.0×1019cm-3；
The first cap layer is heavily doped with Be at a concentration of 1 × 1018～5×1019cm-3；
The n-channel antimonide quantum well layer 4 includes:
sequentially laminated from bottom to top on the buffer layer 2
The second lower barrier layer 41 is made of AlInSb material and has a thickness of 50-100 nm,
The second channel layer 42 is made of InAsSb material and has a thickness of 10-20 nm,
The second isolation layer 43 is made of AlInSb material and has a thickness of 2-5 nm,
The second upper barrier layer 44 is made of AlInSb material and has a thickness of 5-8 nm,
A second interface control layer 45 made of InAs material with a thickness of 1-2 nm,
The second cap layer 46 is made of InSb or GaSb materials, and the thickness is 5-20 nm;
a second doping layer 441 is further disposed in the second upper barrier layer 44, the second doping layer 441 is made of Si or Te material and has a doping concentration of 1.0 × 1018～1.0×1019cm-3；
The second cap layer is heavily doped with Si at a concentration of 1 × 1018～5×1019cm-3；
A high-K gate dielectric layer 71 is arranged on each of the first interface control layer 35 and the second interface control layer 45;
the source electrode 6 and the drain electrode 5 are arranged on the first cap layer 36 and the second cap layer 46;
and the two high-K gate dielectric layers are provided with a gate 7.
A passivation isolation layer 8 is further arranged between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer;
the high-K gate dielectric layer adopts HfO2、Al2O3Or Ta2O5A material;
the substrate is made of Si or GaAs material.
The structure and the preparation method of an antimonide quantum well CMOS device provided by the invention are described below by combining specific embodiments.
Example 1
An antimonide quantum well CMOS device structure, shown in fig. 1, comprising:
GaAs is used as a substrate 1;
the substrate 1 is provided with a buffer layer 2, and the thickness of the buffer layer is 1.0 mu m;
a p-channel antimonide quantum well layer 3 and an n-channel antimonide quantum well layer 4 are arranged on the buffer layer 2 relatively and independently;
the p-channel antimonide quantum well layer 3 includes:
sequentially laminated from bottom to top on the buffer layer 2
The first lower barrier layer 31 is made of AlGaSb material and has a thickness of 50nm,
A first channel layer 32 made of InGaSb material and having a thickness of 10nm,
A first isolation layer 33 made of AlGaSb material and having a thickness of 2nm,
A first upper barrier layer 34 made of AlGaSb material and having a thickness of 5nm,
The first interface control layer 35 is made of InAs material with a thickness of 2nm,
The first cap layer 36 is made of InSb material and has the thickness of 5 nm;
a first doped layer 341 is further disposed in the first upper barrier layer 34, the first doped layer 341 is a Be material and has a doping concentration of 3.3 × 1018；
The first cap layer is heavily doped with Be at a concentration of 2 × 1019(ii) a The n-channel antimonide quantum well layer 4 includes:
sequentially laminated from bottom to top on the buffer layer 2
The second lower barrier layer 41 is made of AlInSb material and has a thickness of 50nm,
A second channel layer 42 made of InAsSb material and having a thickness of 10nm,
The second isolation layer 43 is made of AlInSb material and has a thickness of 2nm,
The second upper barrier layer 44 is made of AlInSb material and has a thickness of 5nm,
A second interface control layer 45 made of InAs material with a thickness of 1nm,
And a second cap layer 46 made of InSb material and having a thickness of 5 nm;
a second doping layer 441 is further disposed in the second upper barrier layer 44, the second doping layer 441 is made of Si material and has a doping concentration of 5 × 1018；
The second cap layer is heavily doped with Si at a concentration of 3 × 1019；
A high-K gate dielectric layer 71 is arranged on each of the first interface control layer 35 and the second interface control layer 45;
the source electrode 6 and the drain electrode 5 are arranged on the first cap layer 36 and the second cap layer 46;
and the two high-K gate dielectric layers are provided with a gate 7.
A passivation isolation layer 8 is further arranged between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer;
the high-K gate dielectric layer is HfO2；
The preparation method of the antimonide quantum well CMOS device structure is shown in figure 2 and comprises the following steps:
s101 selecting GaAs substrate
S102, growing 1 mu m of AlGaSb buffer layer on a GaAs substrate by utilizing a Molecular Beam Epitaxy (MBE) technology.
S103, growing p-channel antimonide quantum well layers on the buffer layer in sequence by utilizing a molecular beam epitaxy technology to form a heterojunction; growing a first lower barrier layer AlGaSb on the surface of the buffer layer; growing a first channel layer InGaSb on the first lower barrier layer; growing a first isolation layer algalsb on the first channel layer; growing a first upper barrier layer AlGaSb on the first isolation layer; doping Be in the first upper barrier layer; and growing a first interface control layer InAs on the first upper barrier layer, and growing a first cap layer InSb on the first upper barrier layer.
S104, forming a groove region in which the n-channel antimonide quantum well layer can grow by utilizing an ICP (inductively coupled plasma) etching technology, wherein the thickness of the groove region is equal to that of the n-channel quantum well layer.
S105, growing a second lower barrier layer AlInSb on the buffer layer by utilizing a molecular beam epitaxy technology; growing a second channel layer InAsSb on the second lower barrier layer; growing a second isolating layer AlInSb on the second channel layer; growing a second upper barrier layer AlInSb on the second isolation layer; doping Si in the second upper barrier layer to form a second doping layer; and growing a second interface control layer InAs on the second upper barrier layer, and growing a second cap layer InSb on the second upper barrier layer, wherein Si heavy doping is carried out in the second cap layer.
Formation of S106 n-channel antimonide quantum well layer and p-channel antimonide quantum well layer passivation isolation region
(a) Cleaning the device, and then drying the device by using nitrogen;
(b) and photoetching and etching the cleaned antimonide epitaxial material to complete the mesa isolation of the epitaxial material and the isolation between the n channel and the p channel.
(c) And depositing an SiN passivation layer on the cleaned epitaxial material by adopting PECVD equipment, and forming passivation isolation regions on the n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer.
S107, ohmic contact preparation:
(a) photoetching a source-drain ohmic region on the surface of the cleaned antimonide epitaxial material to manufacture a photoresist mask;
(b) soaking in a 37% dilute hydrochloric acid solution for 15s to remove a surface oxide layer;
(c) sequentially depositing Pd/Ti/Pt/Au multilayer metals on the heavily doped InSb cap layers of the whole n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer, and annealing at the temperature of 300-350 ℃ for 15-30s to form ohmic contact.
S108, preparing a high-K gate dielectric layer:
(a) photoetching a dielectric layer region on the surface of the antimonide epitaxial material to manufacture a photoresist mask;
(b) soaking to dilute citric acid (C)6H8O7:H2O21:1) solution 60s, removing the cap layer under the gate, and etching to the InAs of the first interface control layer;
(c) deposition of HfO using Atomic Layer Deposition (ALD)2And forming a high-K gate dielectric layer.
S109, preparing a grid:
photoetching is carried out on a gate electrode region on the surface of the high-k dielectric layer, and a photoresist mask is manufactured;
depositing metal Ti/Pt/Au on the high-K gate dielectric layer by electron beam evaporation;
soaking the device in the photoresist removing solution, and stripping the metal except the defined pattern to complete the manufacture of the insulated gate;
s110Pad deposition:
(a) photoetching is carried out on a Pad area on the surface of the antimonide epitaxial material to manufacture a photoresist mask;
(b) depositing metal Ti/Au by electron beam evaporation to obtain a grid electrode and a drain electrode;
(c) and soaking the device in the photoresist removing solution, stripping the metal except the defined pattern, and cleaning with deionized water.
S111 secondary passivation protection device:
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the antimonide quantum well CMOS device.
Example 2
An antimonide quantum well CMOS device structure, the same as embodiment 1, except that:
the preparation method of the antimonide quantum well CMOS device structure is shown in figure 3 and comprises the following steps:
s201 selecting GaAs substrate
S202, growing AlGaSb with a buffer layer of 1 μm on a GaAs substrate by using a molecular beam epitaxy technique.
S203, sequentially growing n-channel antimonide quantum well layers on the buffer layer by using a molecular beam epitaxy technology to form a heterojunction; growing a second lower barrier layer AlInSb on the surface of the buffer layer; growing a second channel layer InAsSb on the second lower barrier layer; growing a second isolating layer AlInSb on the second channel layer; growing a second upper barrier layer AlInSb on the second isolation layer; doping Si in the second upper barrier layer to form a second doping layer; and growing a second interface control layer InAs on the second upper barrier layer, and growing a second cap layer InSb on the second upper barrier layer, wherein Si heavy doping is carried out in the second cap layer.
S204, forming a groove region in which the p-channel antimonide quantum well layer can grow by utilizing an ICP (inductively coupled plasma) etching technology, wherein the thickness of the groove region is equal to that of the p-channel quantum well layer.
S205, sequentially growing p-channel antimonide quantum well layers on the buffer layer by using a molecular beam epitaxy technology to form a heterojunction; growing a first lower barrier layer AlGaSb on the surface of the buffer layer; growing a first channel layer InGaSb on the first lower barrier layer; growing a first isolation layer algalsb on the first channel layer; growing a first upper barrier layer AlGaSb on the first isolation layer; doping Be in the first upper barrier layer; and growing a first interface control layer InAs on the first upper barrier layer, and growing a first cap layer InSb on the first upper barrier layer.
S206 n-channel antimonide quantum well layer and p-channel antimonide quantum well layer passivation isolation region formation (a) the clean antimonide epitaxial material is subjected to photoetching and etching, and mesa isolation of the epitaxial material and isolation between the n-channel and the p-channel are completed.
(b) And depositing an SiN passivation layer on the cleaned epitaxial material by adopting PECVD equipment, and forming passivation isolation regions on the n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer.
S207, ohmic contact preparation:
(a) photoetching a source-drain ohmic region on the surface of the cleaned antimonide epitaxial material to manufacture a photoresist mask;
(b) soaking in a 37% dilute hydrochloric acid solution for 15s to remove a surface oxide layer;
(c) sequentially depositing Pd/Ti/Pt/Au multilayer metals on the heavily doped InSb cap layers of the whole n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer, and annealing at the temperature of 300-350 ℃ for 15-30s to form ohmic contact.
S208, preparing a high-K gate dielectric layer:
(a) photoetching a dielectric layer region on the surface of the antimonide epitaxial material to manufacture a photoresist mask;
(b) soaking to dilute citric acid (C)6H8O7:H2O21:1) solution 60s, removing the cap layer under the gate, and etching to the InAs of the first interface control layer;
(c) deposition of HfO using Atomic Layer Deposition (ALD)2And forming a high-K gate dielectric layer.
S209, preparing a grid:
photoetching is carried out on a gate electrode region on the surface of the high-k dielectric layer, and a photoresist mask is manufactured;
depositing metal Ti/Pt/Au on the high-K gate dielectric layer by electron beam evaporation;
soaking the device in the photoresist removing solution, and stripping the metal except the defined pattern to complete the manufacture of the insulated gate;
s210Pad deposition:
(a) photoetching is carried out on a Pad area on the surface of the antimonide epitaxial material to manufacture a photoresist mask;
(b) depositing metal Ti/Au by electron beam evaporation to obtain a grid electrode and a drain electrode;
(c) and soaking the device in the photoresist removing solution, stripping the metal except the defined pattern, and cleaning with deionized water.
S211, secondary passivation of the protection device:
(a) cleaning the device, and then drying the device by using nitrogen;
(b) and depositing a silicon nitride passivation layer on the cleaned device by adopting PECVD equipment, thereby completing the preparation of the antimonide quantum well CMOS device.
Example 3
The same as in example 1, except that,
the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer on the buffer layer, and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared according to the following steps,
after the p-channel antimonide quantum well layer is prepared, selective area etching p-channel antimonide quantum well layer epitaxial material to the buffer layer to form a groove area where the n-channel antimonide quantum well layer can grow, and forming a groove area on the p-channel antimonide quantum well layer through PECVDPassivating the etched side, and depositing a passivation layer SiO2The passivated isolation region between the n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer can be achieved by forming a passivated isolation layer and then growing the n-channel antimonide quantum well layer on the buffer layer.
In the antimonide quantum well CMOS device, the p channel and the n channel both adopt antimonide quantum well structures, the structure can reduce dislocation density caused by lattice mismatch through component regulation and control on one hand, and on the other hand, the channel is effectively isolated from a high-k gate medium through a barrier layer, and two-dimensional electron/hole gas is formed on the surface of the channel, so that the mobility is improved, the performance of the device is improved, and the mobility realized by the antimonide n or p channel quantum well structure is far greater than that of Si, Ge channel and GaAs system materials in the prior art.
The invention provides a preparation method of an antimonide quantum well CMOS device, which realizes the epitaxial growth of n-channel and p-channel materials of the same system and avoids the complex process problem of integrating the InGaAs material of an n-channel and the Ge material of a p-channel in the prior art.
The invention is based on that under the natural environment condition, the surface of an antimonide material has high activity, and the high interface state density Dit is caused by the Fermi level pinning effect of trap charges such as Sb-Sb polymer, Sb simple substance and the like>1012cm-2eV-1And the carrier scattering center is formed, so that the advantage of high mobility of an antimonide material cannot be exerted, and in the insulated gate process, an InAs thin layer is introduced to serve as an interface control layer, so that the formation of trapped charges such as Sb elements is avoided, and the interface state density is reduced.
According to the antimonide quantum well CMOS device, the p channel and the n channel are both of antimonide quantum well structures, and therefore the stability of the antimonide quantum well CMOS device applied to an integrated circuit is effectively improved.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A structure of an antimonide quantum well CMOS device, comprising:
a substrate;
a buffer layer is arranged on the substrate;
a p-channel antimonide quantum well layer and an n-channel antimonide quantum well layer are arranged on the buffer layer relatively and independently;
the p-channel antimonide quantum well layer includes:
the first lower barrier layer, the first channel layer, the first isolating layer, the first upper barrier layer, the first interface control layer and the first cap layer are sequentially arranged on the buffer layer in a laminated mode from bottom to top; a first doping layer is also arranged in the first upper barrier layer;
the n-channel antimonide quantum well layer includes:
a second lower barrier layer, a second channel layer, a second isolation layer, a second upper barrier layer, a second interface control layer and a second cap layer which are sequentially arranged on the buffer layer in a laminated manner from bottom to top; a second doping layer is also arranged in the second upper barrier layer;
a passivation isolation layer is arranged between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well;
high-K gate dielectric layers are arranged on the first interface control layer and the second interface control layer;
a source electrode and a drain electrode are arranged on the first cap layer and the second cap layer;
and grid electrodes are arranged on the two high-K grid dielectric layers.
2. The structure of an antimonide quantum well CMOS device of claim 1, wherein the first lower barrier layer is AlGaSb, the first channel layer is InGaSb, the first isolation layer is AlGaSb, the first upper barrier layer is AlGaSb, and the first doping layer is Be.
3. The structure of an antimonide quantum well CMOS device of claim 1, wherein the second lower barrier layer is made of AlInSb material, the second channel layer is made of InAsSb material, the second isolation layer is made of AlInSb material, the second upper barrier layer is made of AlInSb material, and the second doping layer is made of Si or Te material.
4. The structure of the antimonide quantum well CMOS device of claim 1, wherein the first interface control layer and the second interface control layer both use InAs materials;
the first cap layer and the second cap layer are made of GaSb or InSb materials.
5. The structure of the antimonide quantum well CMOS device of claim 1, wherein the substrate is made of Si or GaAs material; the passivation isolation layer is made of SiO2Or SiNxA material.
6. A method for preparing the structure of the antimonide quantum well CMOS device as claimed in any one of claims 1 to 5, comprising the following steps:
selecting a substrate material;
growing a buffer layer on the substrate;
preparing a p-channel antimonide quantum well layer, an n-channel antimonide quantum well layer and a passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer on a buffer layer;
respectively preparing a source electrode and a drain electrode on the first cap layer and the second cap layer;
respectively etching the first cap layer and the second cap layer to a first interface control layer and a second interface control layer, and then respectively preparing high-K gate dielectric layers on the first interface control layer and the second interface control layer;
and preparing a grid electrode on the two high-K grid dielectric layers to obtain the preparation of the antimonide CMOS device.
7. The method of claim 6, wherein the p-channel antimonide quantum well layer, the n-channel antimonide quantum well layer and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared on the buffer layer according to the following steps:
growing a first lower barrier layer, a first channel layer, a first isolating layer, a first upper barrier layer, a first interface control layer and a first cap layer on the buffer layer in sequence to form a p-channel antimonide quantum well layer;
etching the selected region of the p-channel antimonide quantum well layer until the buffer layer forms a groove region where the n-channel antimonide quantum well layer can grow;
growing a second lower barrier layer, a second channel layer, a second isolating layer, a second upper barrier layer, a second interface control layer and a second cap layer on the buffer layer in sequence to form an n-channel antimonide quantum well layer;
and etching the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer until reaching the buffer layer, and then passivating to form a passivation isolation layer.
8. The method of claim 6, wherein the p-channel antimonide quantum well layer, the n-channel antimonide quantum well layer and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared on the buffer layer according to the following steps:
growing a second lower barrier layer, a second channel layer, a second isolating layer, a second upper barrier layer, a second interface control layer and a second cap layer on the buffer layer in sequence to form an n-channel antimonide quantum well layer;
etching the selected region of the n-channel antimonide quantum well layer until the buffer layer forms a groove region where the p-channel antimonide quantum well layer can grow;
growing a first lower barrier layer, a first channel layer, a first isolating layer, a first upper barrier layer, a first interface control layer and a first cap layer on the buffer layer in sequence to form a p-channel antimonide quantum well layer;
and etching the n-channel antimonide quantum well layer and the p-channel antimonide quantum well layer until reaching the buffer layer, and then passivating to form a passivation isolation layer.
9. The method of claim 6, wherein the p-channel antimonide quantum well layer, the n-channel antimonide quantum well layer and the passivation isolation layer between the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are prepared on the buffer layer according to the following steps:
growing a first lower barrier layer, a first channel layer, a first isolating layer, a first upper barrier layer, a first interface control layer and a first cap layer on the buffer layer in sequence to form a p-channel antimonide quantum well layer;
etching the selected region of the p-channel antimonide quantum well layer until the buffer layer forms a groove region where the n-channel antimonide quantum well layer can grow;
then passivating the etched side of the p-channel antimonide quantum well layer to form a passivation isolation layer;
and sequentially growing a second lower barrier layer, a second channel layer, a second isolating layer, a second upper barrier layer, a second interface control layer and a second cap layer on the buffer layer to form an n-channel antimonide quantum well layer.
10. The method for manufacturing the structure of the antimonide quantum well CMOS device as claimed in any one of claims 7 to 9, wherein the p-channel antimonide quantum well layer and the n-channel antimonide quantum well layer are respectively manufactured on the buffer layer by adopting a molecular beam epitaxy technology.
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