CN113169180A

CN113169180A - Three-dimensional flat NAND memory device with curved memory elements and method of fabricating the same

Info

Publication number: CN113169180A
Application number: CN201980079862.9A
Authority: CN
Inventors: 崔志欣; 西川雅敏; 张艳丽
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2019-02-18
Filing date: 2019-11-26
Publication date: 2021-07-23
Also published as: WO2020171869A1

Abstract

A three-dimensional memory device includes alternating stacks of conductive and spacer strips located over a substrate and laterally spaced from each other by a memory stack assembly. These spacer strips may comprise air gap strips or insulating strips. Each of these memory stack components includes two-dimensional arrays of lateral protruding regions. Each of the lateral protruding regions includes a respective curved charge storage element. These charge storage elements may be discrete elements located within respective lateral protruding regions, or may be part of a layer of charge storage material extending vertically over a plurality of conductive strips. Each of these memory stack components may include two rows of vertical semiconductor channels laterally overlying a respective vertical stack of charge storage elements.

Description

Three-dimensional flat NAND memory device with curved memory elements and method of fabricating the same

RELATED APPLICATIONS

This application claims priority from U.S. non-provisional patent application serial nos. 16/278,426 and 16/278,488 filed on 18/2/2019, and the entire contents of these applications are incorporated herein by reference.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional flat NAND memory devices including curved memory elements and methods of fabricating the same.

Background

Configurations of three-dimensional NAND memory devices use planar memory cells in which the tunneling dielectric has a planar vertical surface. Hang-Ting Lue et al describe such flat memory devices in an article entitled "A128 Gb (MLC)/192Gb (TLC) Single-gate Vertical Channel (SGVC) Architecture 3D NAND using only16Layers of 128Gb (MLC)/192Gb (TLC) Single Gate Vertical Channel (SGVC) Architecture 3D with Robust Read Disturb, Long-term Retention, and Excellent Scaling capabilities", IEDM Procedings (IEDM Association, 2017), page 461.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a three-dimensional memory device including: alternating stacks of conductive and air-gap strips over a substrate and laterally spaced from each other by a memory stack assembly, wherein the memory stack assembly extends laterally in a first horizontal direction and is spaced from each other in a second horizontal direction, wherein: each of the memory stack components includes two-dimensional arrays of lateral protrusion areas; each laterally projecting region projects laterally outward from a respective vertical plane that includes an interface between a respective one of the accumulator stack assemblies and the air gap strip within a respective one of the alternating stacks; each of the lateral protruding regions comprises a respective curved charge storage element; each of the memory stack assemblies includes two rows of vertical semiconductor channels; and each vertical semiconductor channel within the two rows of vertical semiconductor channels laterally overlies a respective vertical stack of charge storage elements.

According to another embodiment of the present disclosure, there is provided a method of forming a three-dimensional memory device; forming alternating stacks of strips of a first sacrificial material and strips of a second sacrificial material over a substrate, wherein the alternating stacks are laterally spaced from each other by line trenches extending laterally in a first horizontal direction; modifying the line trenches to provide a two-dimensional array of lateral recesses on each sidewall of the line trenches, wherein each two-dimensional array of lateral recesses is laterally bounded by a respective two-dimensional array of lateral recess surfaces of the second strip of sacrificial material; forming memory stack components in each volume, the each volume comprising a combination of a volume of wire trenches and a volume of two contiguous two-dimensional arrays of lateral recesses, wherein each of the memory stack components comprises two-dimensional arrays of lateral protruding regions, and each of the lateral protruding regions comprises a respective charge storage element; replacing the remaining portion of the second strip of sacrificial material with a conductive strip; and forming an air gap strip by removing the first strip of sacrificial material.

According to still another embodiment of the present disclosure, there is provided a three-dimensional memory device including: alternating stacks of conductive strips and insulating strips over the substrate and laterally spaced from each other by memory stack components, wherein the memory stack components extend laterally in a first horizontal direction and are spaced from each other in a second horizontal direction, wherein: each of the memory stack components includes two-dimensional arrays of lateral protrusion areas; the lateral protruding regions protrude laterally outward from respective vertical planes that include interfaces between the memory stack assembly and the subset of air gap strips; and each of the lateral protruding regions includes a respective charge storage element having a pair of concave inner side wall segments having a respective horizontal concave profile in horizontal cross-section and a pair of convex outer side wall segments having a respective horizontal convex profile in horizontal cross-section.

According to still another embodiment of the present disclosure, there is provided a method of forming a three-dimensional memory device, the method including: forming alternating stacks of insulating strips and sacrificial material strips over a substrate, wherein the alternating stacks are laterally spaced from each other by line trenches extending laterally in a first horizontal direction; modifying the line trenches to provide a two-dimensional array of lateral recesses on each sidewall of the line trenches, wherein each two-dimensional array of lateral recesses is laterally bounded by a respective two-dimensional array of lateral recess surfaces of the strip of sacrificial material; forming memory stack components in each volume, the each volume comprising a combination of a volume of wire trenches and a volume of two contiguous two-dimensional arrays of lateral recesses, wherein each of the memory stack components comprises two rows of material stack strips extending vertically and laterally overlying a sidewall of a respective one of the alternating stacks, and each row of material stack strips comprises a respective plurality of material stack strips laterally spaced along a first horizontal direction, and each of the material stack strips comprises a respective layer of charge storage material comprising charge storage elements within each respective vertical stack of lateral recesses selected from the two-dimensional arrays of lateral recesses; and replacing the sacrificial material layer with a conductive strip.

Drawings

Fig. 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming a vertically alternating sequence of first and second layers of sacrificial material and an insulating cap layer according to a first embodiment of the present disclosure.

Fig. 2 is a schematic vertical cross-sectional view of a first example structure after forming stepped platforms and backward stepped dielectric material portions according to a first embodiment of the present disclosure.

Fig. 3A is a schematic vertical cross-sectional view of a first exemplary structure after forming a line trench according to a first embodiment of the present disclosure.

Fig. 3B is a top view of the first exemplary structure of fig. 3A. The vertical plane a-a' is the plane of the section of fig. 3A.

Fig. 4A is a vertical cross-sectional view of a portion of a line trench in the first exemplary structure of fig. 3A and 3B.

Fig. 4B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 4A. The vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 4A.

Fig. 4C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 4A. The vertical plane C-C' corresponds to the plane of the vertical cross-section of fig. 4A.

Fig. 5A is a vertical cross-sectional view of a portion of a line trench after forming a silicon oxide layer, a diffusion barrier layer, and a first masking material rail according to a first embodiment of the present disclosure.

Fig. 5B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 5A. The vertical plane a-a' corresponds to the plane of the vertical cross-section of fig. 5A.

Fig. 5C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 5A. The vertical plane C-C' corresponds to the plane of the vertical cross-section of fig. 5A.

Fig. 6A is a vertical cross-sectional view of a portion of a line trench after forming a two-dimensional array of posts of mask material according to a first embodiment of the present disclosure.

Fig. 6B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 6A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 6A.

Fig. 6C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 6A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 6A.

Fig. 7A is a vertical cross-sectional view of a portion of a wire trench after forming a diffusion barrier strip according to a first embodiment of the present disclosure.

Fig. 7B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 7A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 7A.

Fig. 7C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 7A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 7A.

Fig. 8A is a vertical cross-sectional view of a portion of a line trench after removing a two-dimensional array of posts of mask material and forming a semiconductor oxide layer having a two-dimensional array of thickened portions by an oxidation process, according to a first embodiment of the present disclosure.

Fig. 8B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 8A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 8A.

Fig. 8C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 8A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 8A.

Fig. 9A is a vertical cross-sectional view of a portion of a line trench after removal of a diffusion barrier strip and a semiconductor oxide layer according to a first embodiment of the present disclosure.

Fig. 9B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 9A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 9A.

Fig. 9C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 9A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 9A.

Fig. 10A is a vertical cross-sectional view of a portion of a line trench after forming a blocking dielectric layer and a charge storage material layer according to a first embodiment of the present disclosure.

Fig. 10B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 10A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 10A.

Fig. 10C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 10A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 10A.

Fig. 11A is a vertical cross-sectional view of a portion of a line trench after forming discrete charge storage elements by anisotropically etching a layer of charge storage material according to a first embodiment of the present disclosure.

FIG. 11B is a horizontal cross-sectional view taken along plane B-B' of the structure of FIG. 11A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 11A.

FIG. 11C is a horizontal cross-sectional view taken along plane C-C' of the structure of FIG. 11A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 11A.

Figure 12A is a vertical cross-sectional view of a portion of a line trench after forming a tunneling dielectric layer, a semiconductor channel material layer, and a second mask material rail according to a first embodiment of the present disclosure.

Fig. 12B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 12A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 12A.

Fig. 12C is a horizontal cross-sectional view taken along plane C-C' of the structure of fig. 12A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 12A.

Fig. 13A is a vertical cross-sectional view of a portion of a line trench after forming a two-dimensional array of posts of mask material according to a first embodiment of the present disclosure.

Fig. 13B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 13A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 13A.

Fig. 13C is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 13A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 13A.

Figure 14A is a vertical cross-sectional view of a portion of a line trench after separating a layer of semiconductor channel material into vertical semiconductor channels according to a first embodiment of the present disclosure.

Fig. 14B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 14A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 14A.

Fig. 14C is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 14A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 14A.

Fig. 15A is a vertical cross-sectional view of a portion of a line trench after removal of a two-dimensional array of posts of mask material according to a first embodiment of the present disclosure.

Fig. 15B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 15A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 15A.

Fig. 15C is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 15A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 15A.

Fig. 16A is a vertical cross-sectional view of a portion of a wire trench after forming a dielectric core according to a first embodiment of the present disclosure.

Fig. 16B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 16A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 16A.

Fig. 16C is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 16A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 16A.

Fig. 17A is a vertical cross-sectional view of the first exemplary structure after the processing steps of fig. 16A-16C.

Fig. 17B is a top view of the first exemplary structure of fig. 13A. The vertical plane a-a' is the plane of the section of fig. 13A.

Fig. 18A is a vertical cross-sectional view of a first example structure after forming a drain region, according to a first embodiment of the present disclosure.

Fig. 18B is a top view of the first exemplary structure of fig. 18A. The vertical plane a-a' is the plane of the cross-section of fig. 18A.

Fig. 19A is a vertical cross-sectional view of a first exemplary structure after forming a backside via cavity, according to a first embodiment of the present disclosure.

Fig. 19B is a top view of the first exemplary structure of fig. 19A. The vertical plane a-a' is the plane of the section of fig. 19A.

Fig. 20 is a schematic vertical cross-sectional view of a first exemplary structure after forming a backside recess according to a first embodiment of the present disclosure.

Fig. 21 is a schematic vertical cross-sectional view of a first exemplary structure after forming conductive strips in backside recesses, according to a first embodiment of the present disclosure.

Fig. 22A is a vertical cross-sectional view of a portion of the wire trench after the processing step of fig. 21.

Fig. 22B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 22A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 22A.

Fig. 22C is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 22A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 22A.

FIG. 23 is a schematic vertical cross-sectional view of a first exemplary structure after removing a first strip of sacrificial material and forming a strip of air gaps, according to a first embodiment of the present disclosure.

Fig. 24A is a vertical cross-sectional view of a portion of the wire trench after the processing step of fig. 23.

Fig. 24B is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 24A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 24A.

Fig. 24C is a horizontal cross-sectional view taken along plane B-B' of the structure of fig. 24A. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 24A.

Fig. 25A is a schematic vertical cross-sectional view of a first exemplary structure after formation of an air gap pillar in a backside via cavity, according to a first embodiment of the present disclosure.

Fig. 25B is a top view of the first exemplary structure of fig. 25A. The vertical plane a-a' is the plane of the cross-section of fig. 25A.

Fig. 26 is a schematic vertical cross-sectional view of a second exemplary structure after forming a vertically alternating sequence of insulating layers and sacrificial material layers and forming an insulating cap layer, according to a second embodiment of the present disclosure.

Fig. 27 is a schematic vertical cross-sectional view of a second example structure after forming stepped platforms and backward stepped dielectric material portions according to a second embodiment of the present disclosure.

Fig. 28A is a schematic vertical cross-sectional view of a second exemplary structure after forming a line trench according to a second embodiment of the present disclosure.

Fig. 28B is a top view of the second exemplary structure of fig. 28A. The vertical plane a-a' is the plane of the section of fig. 28A.

Fig. 29A is a first vertical cross-sectional view of a region of the second exemplary structure of fig. 28A and 28B.

Fig. 29B is a second vertical cross-sectional view of a region of the second exemplary structure of fig. 29A.

Fig. 29C is a horizontal sectional view taken along the plane C-C' of fig. 29A and 29B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 29A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 29B.

Fig. 30A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a first mask rail according to a second embodiment of the present disclosure.

Fig. 30B is a second vertical cross-section of a region of the second exemplary structure of fig. 30A.

Fig. 30C is a horizontal cross-sectional view taken along plane C-C of fig. 30A and 30B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 30A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 30B.

Fig. 31A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a two-dimensional array of posts of mask material according to a second embodiment of the present disclosure.

Fig. 31B is a second vertical cross-section of a region of the second exemplary structure of fig. 31A.

Fig. 31C is a horizontal sectional view taken along the plane C-C' of fig. 31A and 31B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 31A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 31B.

Fig. 32A is a first vertical cross-sectional view of a region of a second example structure after forming a two-dimensional array of lateral recesses on each sidewall of the line trench, in accordance with a second embodiment of the present disclosure.

Fig. 32B is a second vertical cross-section of a region of the second exemplary structure of fig. 32A.

Fig. 32C is a horizontal cross-sectional view taken along plane C-C of fig. 32A and 32B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 32A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 32B.

Fig. 33A is a first vertical cross-sectional view of a region of a second example structure after removal of the two-dimensional array of posts of mask material according to a second embodiment of the present disclosure.

Fig. 33B is a second vertical cross-section of a region of the second exemplary structure of fig. 33A.

Fig. 33C is a horizontal cross-sectional view along the plane C-C' of fig. 33A and 33B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 33A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 33B.

Figure 34A is a first vertical cross-sectional view of a region of a second example structure after forming a continuous layer stack of a blocking dielectric layer, a charge storage material layer, and a tunneling dielectric layer, according to a second embodiment of the present disclosure.

Fig. 34B is a second vertical cross-section of a region of the second exemplary structure of fig. 34A.

Fig. 34C is a horizontal cross-sectional view taken along the plane C-C of fig. 34A and 34B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 34A. The horizontal plane B-B' corresponds to the plane of the vertical sectional view of fig. 34B.

Fig. 35A is a first vertical cross-sectional view of a region of a second example structure after anisotropically etching a continuous layer stack according to a second embodiment of the present disclosure.

Fig. 35B is a second vertical cross-section of a region of the second exemplary structure of fig. 35A.

Fig. 35C is a horizontal cross-sectional view along the plane C-C of fig. 35A and 35B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 35A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 35B.

Figure 36A is a first vertical cross-sectional view of a region of a second example structure after forming a layer of semiconductor channel material, according to a second embodiment of the present disclosure.

Fig. 36B is a second vertical cross-section of a region of the second exemplary structure of fig. 36A.

Fig. 36C is a horizontal cross-sectional view taken along plane C-C of fig. 36A and 36B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 36A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 36B.

Fig. 37A is a first vertical cross-sectional view of a region of a second example structure after forming a layer of mask material according to a second embodiment of the present disclosure.

Fig. 37B is a second vertical cross-section of a region of the second exemplary structure of fig. 37A.

Fig. 37C is a horizontal cross-sectional view taken along plane C-C of fig. 37A and 37B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 37A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 37B.

Fig. 38A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a second mask rail according to a second embodiment of the present disclosure.

Fig. 38B is a second vertical cross-section of a region of the second exemplary structure of fig. 38A.

Fig. 38C is a horizontal cross-sectional view along the plane C-C of fig. 38A and 38B. The vertical plane a-a' corresponds to the plane of the vertical sectional view of fig. 38A. The horizontal plane B-B' corresponds to the plane of the vertical sectional view of fig. 38B.

Fig. 39A is a first vertical cross-sectional view of a region of a second exemplary structure after forming a two-dimensional array of posts of mask material according to a second embodiment of the present disclosure.

Fig. 39B is a second vertical cross-sectional view of a region of the second exemplary structure of fig. 39A.

Fig. 39C is a horizontal cross-sectional view taken along plane C-C of fig. 39A and 39B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 39A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 39B.

Figure 40A is a first vertical cross-sectional view of a region of a second example structure after forming a material stack stripe including a blocking dielectric layer, a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel, according to a second embodiment of the present disclosure.

Fig. 40B is a second vertical cross-section of a region of the second exemplary structure of fig. 40A.

Fig. 40C is a horizontal cross-sectional view along the plane C-C of fig. 40A and 40B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 40A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 40B.

Fig. 41A is a first vertical cross-sectional view of a region of a second exemplary structure after removal of the two-dimensional array of posts of mask material according to a second embodiment of the present disclosure.

Fig. 41B is a second vertical cross-sectional view of a region of the second exemplary structure of fig. 41A.

Fig. 41C is a horizontal sectional view taken along the plane C-C' of fig. 41A and 41B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 41A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 41B.

Fig. 42A is a first vertical cross-sectional view of a region of a second example structure after forming a dielectric core according to a second embodiment of the present disclosure.

Fig. 42B is a second vertical cross-section of a region of the second exemplary structure of fig. 42A.

Fig. 42C is a horizontal cross-sectional view along the plane C-C of fig. 42A and 42B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 42A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 42B.

Figure 43A is a first vertical cross-sectional view of a region of a second example structure after forming a drain region, according to a second embodiment of the present disclosure.

Fig. 43B is a second vertical cross-sectional view of a region of the second exemplary structure of fig. 43A.

Fig. 43C is a horizontal cross-sectional view along the plane C-C of fig. 43A and 43B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 43A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 43B.

Fig. 43D is a top view of a region of the second exemplary structure of fig. 43A-43C.

Fig. 44A is a vertical cross-sectional view of the second exemplary structure after the processing steps of fig. 43A-43D.

Fig. 44B is a top view of the second exemplary structure of fig. 44A. The vertical plane a-a' is the plane of the section of fig. 44A.

Fig. 45A is a vertical cross-sectional view of a second exemplary structure after forming a backside via cavity, according to a second embodiment of the present disclosure.

Fig. 45B is a top view of the second exemplary structure of fig. 45A. The vertical plane a-a' is the plane of the cross-section of fig. 45A.

Fig. 46 is a schematic vertical cross-sectional view of a second exemplary structure after forming a backside recess according to a second embodiment of the present disclosure.

Fig. 47 is a schematic vertical cross-sectional view of a second exemplary structure after forming conductive strips in backside recesses, according to a second embodiment of the present disclosure.

Fig. 48A is a first vertical cross-section of a region of the second exemplary structure of fig. 47.

Fig. 48B is a second vertical cross-section of a region of the second exemplary structure of fig. 48A.

Fig. 48C is a horizontal cross-sectional view along the plane C-C of fig. 48A and 48B. The vertical plane a-a' corresponds to the plane of the vertical cross-sectional view of fig. 48A. The horizontal plane B-B' corresponds to the plane of the vertical cross-sectional view of fig. 48B.

Fig. 49A is a schematic vertical cross-sectional view of a second example structure after forming dielectric pillars in a backside via cavity, according to a second embodiment of the present disclosure.

Fig. 49B is a top view of the second exemplary structure of fig. 49A. The vertical plane a-a' is the plane of the section of fig. 49A.

Detailed Description

As discussed above, the present disclosure relates to three-dimensional planar NAND memory devices including high mobility vertical semiconductor channels and methods of fabricating the same, various embodiments of which are described in detail herein. In particular, in various embodiments disclosed herein, a curved memory element in a planar memory device may be desirable because geometric effects reduce the required operating voltage of the planar memory device by enhancing the electric field strength.

The figures are not drawn to scale. Where a single instance of an element is illustrated, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated to be absent repetition of the element. Ordinal numbers such as "first," "second," and "third" are used merely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of the present disclosure. The same reference numerals indicate the same elements or similar elements. Elements having the same reference number are assumed to have the same composition unless otherwise specified. As used herein, a first element that is "on" a second element may be located on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is "directly" positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range that is less than the range of an underlying or overlying structure. In addition, a layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above and/or below.

A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "monomer" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. Instead, a two-dimensional array may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories are constructed by forming Memory levels on separate substrates and vertically stacking the Memory levels, as described in U.S. patent No. 5,915,167, entitled Three-dimensional Structure Memory. The substrate may be thinned or removed from the memory level prior to bonding, but such memories are not true monolithic three dimensional memory arrays because the memory level is initially formed over a separate substrate. Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices, and may be fabricated using the various embodiments described herein.

Generally, a semiconductor package (or "package") refers to a unitary semiconductor device that may be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "dies") bonded therein, such as by flip-chip bonding or another die-to-die bonding. A package or chip may include a single semiconductor die (or "die") or a plurality of semiconductor dies. The die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip having multiple dies is capable of executing as many external commands as the total number of planes therein at the same time. Each die includes one or more planes. The same concurrent operation may be performed in each plane within the same die, but there may be some limitations. Where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks") which are the smallest units that can be erased by a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

Referring to fig. 1, a first exemplary structure according to a first embodiment of the present disclosure is shown that may be used, for example, to fabricate a device structure including a vertical NAND memory device. The first exemplary structure includes a substrate (9,10), which may be a semiconductor substrate. The substrate may comprise a substrate semiconductor layer 9 and an optional semiconductor material layer 10. The substrate semiconductor layer 9 may be a semiconductor wafer or a layer of semiconductor material, and may include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor material layer 10 may have a doping of a first conductivity type, and the substrate semiconductor layer 9 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa.

As used herein, "semiconductor material" is meant to have a chemical composition of 1.0X 10^-6S/cm to 1.0X 10⁵A material having an electrical conductivity in the range of S/cm. As used herein, "semiconductor material" refers to a material having a molecular weight of 1.0 x 10 in the absence of an electrical dopant therein^-6S/cm to 1.0X 10⁵A material having an electrical conductivity in the range of S/cm and capable of being produced with appropriate doping of an electrical dopant having a conductivity in the range of 1.0S/cm to 1.0X 10⁵A doping material of conductivity in the range of S/cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to a valence band within the band structure, or an n-type dopant that adds electrons to a conduction band within the band structure. As used herein, "conductive material" means having a thickness of greater than 1.0 x 10⁵S/cm, of electrical conductivity. As used herein, "insulator material" or "dielectric material" is meant to have a thickness of less than 1.0 x 10^-6S/cm of conductivity. As used herein, "heavily doped semiconductor material" refers to a material that is doped with an electrical dopant at a sufficiently high atomic concentration to become conductive (i.e., has a concentration of greater than 1.0 x 10) when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initial amorphous state)⁵Electrical conductivity of S/cm). The "doped semiconductor material" may be a heavily doped semiconductor material, or may be a material including a metal provided at 1.0 × 10^-6S/cm to 1.0X 10⁵A semiconductor material of electrical dopant (i.e., p-type dopant and/or n-type dopant) at a concentration of conductivity in the range of S/cm. "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconducting or conducting, and may be intrinsic or doped semiconductor material. The doped semiconductor material may be semiconducting or conducting, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metallic element therein. All conductivity measurements were performed under standard conditions.

A vertically alternating sequence of first sacrificial material layers 132L and second sacrificial material layers 142L may be formed over the substrate (9, 10). As used herein, "vertically alternating sequence" refers to an alternating sequence of a plurality of instances of a first element and a plurality of instances of a second element that vertically alternate such that an instance of the second element overlies and/or underlies each instance of the first element and an instance of the first element overlies and/or underlies each instance of the second element. The vertically alternating sequence may include a stack of alternating pluralities of first sacrificial material layers 132L and second sacrificial material layers 142L. As used herein, a "layer of material" refers to a layer that includes the material throughout and throughout. As used herein, the alternating pluralities of first and second elements refers to structures in which instances of the first elements alternate with instances of the second elements. Each instance of a first element that is not an end element of the alternating plurality of elements abuts two instances of a second element on both sides, and each instance of a second element that is not an end element of the alternating plurality of elements abuts two instances of the first element on both ends. Thus, the vertically alternating sequence of first and second elements may be an alternating plurality of first and second elements, wherein the alternating of first and second elements occurs in a vertical direction. The first elements may have the same thickness therein, or may have different thicknesses. The second elements may have the same thickness therein, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or an instance of a second material layer and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, the instances of the first element and the instances of the second element may form a unit that repeats periodically within alternating multiple elements.

The alternating plurality of first sacrificial material layers 132L and second sacrificial material layers 142L may constitute a prototype stack or an in-process stack that includes alternating layers of first sacrificial material layers 132L and second sacrificial material layers 142L. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

The second material of the second sacrificial material layer 142L is a sacrificial material that is selectively removable with respect to the first material of the first sacrificial material layer 132L. As used herein, the removal of a first material is "selective" for a "second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process for the first material relative to the second material.

In one embodiment, the first sacrificial material layer 132L may comprise a first sacrificial semiconductor material, and the second sacrificial material layer 142L may comprise a second sacrificial semiconductor material that is selectively removable with respect to the first sacrificial semiconductor material. In one embodiment, the first sacrificial semiconductor material may comprise and/or consist essentially of single crystalline silicon, polycrystalline silicon, or amorphous silicon, and the second sacrificial semiconductor material may comprise and/or consist essentially of a single crystalline silicon germanium alloy, a polycrystalline silicon germanium alloy, and an amorphous silicon germanium alloy. The first sacrificial semiconductor material may comprise undoped silicon, i.e. silicon deposited without any intentional doping. In one embodiment, the first sacrificial semiconductor material may comprise undoped amorphous silicon. In one embodiment, the atomic concentration of germanium in the first sacrificial semiconductor material may be zero, and the atomic concentration of germanium in the second sacrificial semiconductor material may be in the range of 10% to 50% (such as 20% to 40%), although smaller and larger atomic concentrations of germanium may also be used.

The first sacrificial material layer 132L and the second sacrificial material layer 142L may be deposited by a chemical vapor deposition process. The thickness of the first sacrificial material layers 132L and the second sacrificial material layers 142L may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each first sacrificial material layer 132L and each second sacrificial material layer 142L. The number of repetitions of the pair of first sacrificial material layer 132L and second sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 142L may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although more repetitions may also be used. In one embodiment, each first sacrificial material layer 132L and each second sacrificial material layer 142L in the vertically alternating sequence (132L,142L) may have a uniform thickness that is substantially constant within each respective second sacrificial material layer 142L.

Referring to fig. 2, the vertically alternating sequence of first sacrificial material layers 132L and second sacrificial material layers 142L may be patterned to form a stepped surface that continuously extends from a bottommost layer of the vertically alternating sequence (132L,142L) to a topmost layer of the alternating sequence (132L,142L) in the contact region 300. The stepped cavity may be formed within a contact region 300 located between the memory array region 100 and a peripheral device region (not shown) that contains at least one semiconductor device for peripheral circuitry. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity varies stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the cavity depth by one or more levels and a second type of etching process that laterally extends the region to be vertically etched in a subsequent etching process of the first type. As used herein, a "level" of a structure comprising alternating pluralities is defined as the relative position of a pair of first and second material layers within the structure.

By forming stepped cavities, stepped surfaces are formed at peripheral portions of the vertically alternating series (132L, 142L). As used herein, "stepped surface" refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface abuts a first vertical surface extending upward from a first edge of the horizontal surface and abuts a second vertical surface extending downward from a second edge of the horizontal surface. "stepped cavity" refers to a cavity having a stepped surface.

The land regions are formed by patterning a vertically alternating sequence (132L, 142L). Each second sacrificial material layer 142L, except for the topmost second sacrificial material layer 142L, within the vertically alternating sequence (132L,142L) extends laterally further than any overlying second sacrificial material layer 142L within the vertically alternating sequence (132L, 142L). The land region includes a stepped surface of the vertically alternating series (132L,142L) that continuously extends from a bottommost layer within the vertically alternating series (132L,142L) to a topmost layer within the vertically alternating series (132L, 142L).

The backward stepped dielectric material portion 65 (i.e., the insulating fill material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from over the top surface of the topmost first sacrificial material layer 132L, for example, by Chemical Mechanical Planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity may constitute a backward stepped dielectric material portion 65. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is used for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may or may not be doped with dopants, such as B, P and/or F.

Referring to fig. 3A, 3B, and 4A-4D, a photolithographic material stack (not shown) including at least a photoresist layer may be formed over the topmost first sacrificial material layer 132L and the retro-stepped dielectric material portion 65, and may be lithographically patterned to form linear openings therein. The linear opening extends laterally along the first horizontal direction hd1, and has a uniform width along the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. The pattern in the stack of photolithographic material can be transferred through the retro-stepped dielectric material portions 65 and through the vertically alternating sequence (132L,142L) by at least one anisotropic etch using the patterned stack of photolithographic material as an etch mask. Portions of the vertically alternating sequence (132L,142L) underlying the line-shaped openings in the patterned stack of photolithographic material can be etched to form line trenches 49. As used herein, "line trench" refers to a trench that extends transversely straight in the horizontal direction.

The line trenches 49 extend transversely across the vertically alternating series (132L,142L) in a first horizontal direction hd 1. In one embodiment, the wire groove 49 has a corresponding uniform width that is constant during translation in the first horizontal direction hd 1. In one embodiment, the wire grooves 49 may have the same width throughout, and the spacing between adjacent pairs of wire grooves 49 may be the same. In this case, the line trenches 49 may constitute a one-dimensional periodic array of line trenches 49 having a pitch in the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. The width of the line trench 49 in the second horizontal direction hd2 may be in the range 30nm to 500nm, such as 60nm to 250nm, but smaller and larger widths may also be used.

The line trenches 49 extend through each layer of the vertically alternating sequence (132L,142L) and the rearwardly stepped dielectric material portions 65. The chemistry of the anisotropic etching process used to etch through the material of the vertically alternating series (132L,142L) may be alternated to optimize the etching of the first and second materials in the vertically alternating series (132L, 142L). The anisotropic etch may be, for example, a series of reactive ion etches. The sidewalls of the line trench 49 may be substantially vertical or may be tapered. The patterned stack of photolithographic material can then be removed, for example, by ashing.

The line trenches 49 may extend laterally across the entire memory array region 100 and may extend laterally into the contact regions 300. The line trench 49 may extend laterally across the entire contact region 300 in the first horizontal direction hd1, or may extend laterally across only a portion of the width of the contact region 300 instead of the entire width of the first horizontal direction hd1 of the contact region. In one embodiment, the overetch of the semiconductor material layer 10 may optionally be performed after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each line trench 49. The overetch may be performed before or after the stack of photolithographic materials is removed. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the un-recessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth may be in the range of, for example, 1nm to 50nm, although lesser and greater depths may also be used. The over-etch is optional and may be omitted. If no over-etching is performed, the bottom surface of the line trench 49 may be coplanar with the topmost surface of the semiconductor material layer 10. Referring to fig. 3B, in embodiments where an optional overetch is used and embodiments where an overetch is not performed, the layer of semiconductor material 10 may be exposed through the line trench 49.

Each of the line trenches 49 may include a sidewall (or sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. The substrate semiconductor layer 9 and the semiconductor material layer 10 jointly constitute a substrate (9,10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the line trench 49 may extend to the top surface of the substrate semiconductor layer 9. Although fig. 3B shows the exposed semiconductor material layer 10, the substrate semiconductor layer 9 may be exposed in an embodiment where the semiconductor material layer 10 may be omitted.

The vertically alternating sequence (132L,142L) may be divided into discrete portions by the wire trenches 49. Each remaining portion of the vertically alternating sequence (132L,142L) between a pair of line trenches 49 constitutes an alternating stack of remaining portions of the first sacrificial material layer 132L and remaining portions of the second sacrificial material layer 142. Each remaining portion of the first sacrificial material layer 132L may have a rectangular strip shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as a first sacrificial material strip 132. Each remaining portion of the second sacrificial material layer 142L may have a rectangular strip shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as a second sacrificial material strip 142. An alternating stack of first sacrificial material strips 132 and second sacrificial material strips 142 may be formed between each adjacent pair of line trenches 49 over the substrates (9, 10). The alternating stacks (132,142) may be laterally spaced from each other by a wire trench 49 that extends laterally along the first horizontal direction hd 1.

Referring to fig. 5A through 5C, the silicon oxide layer 121 and the diffusion barrier layer 123 may be sequentially deposited by a conformal deposition process. The silicon oxide layer 121 may have a thickness in the range of 1nm to 10nm, but smaller and larger thicknesses may also be used. The diffusion barrier 123 may have a thickness in the range of 4nm to 10nm, but smaller and larger thicknesses may also be used. The diffusion barrier 123 comprises a material that can block oxygen diffusion in subsequent processing steps. In one embodiment, the diffusion barrier layer 123 may comprise silicon nitride.

A mask material may be deposited in the remaining volume of the line trenches 49. Excess portions of the mask material may be removed from over the top surface of the horizontal portions of the diffusion barrier 123 overlying the alternating stack (132, 142). The remaining portion of the mask material in line trench 49 constitutes first mask material rail 124R. As used herein, "rail" or "rail structure" refers to a structure that extends laterally in a horizontal direction. In one embodiment, first mask material rail 124R may have a uniform vertical cross-sectional shape in a plane perpendicular to the longitudinal direction of wire groove 49 (i.e., first horizontal direction hd 1). In one embodiment, the vertical cross-sectional shape of first mask material rail 124R may be rectangular or trapezoidal with a top width greater than a bottom width. In one embodiment, first mask material rail 124R may comprise a carbon-based material. In one embodiment, first mask material rails 124R may comprise spin-on carbon that may be applied by spin-coating and subsequently dried.

Referring to fig. 6A-6C, a photoresist layer (not shown) may be applied over the first exemplary structure, and may then be patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include a plurality of rows of openings overlying a respective one of the line trenches 49. The row-to-row spacing within the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the line trenches 49. Each row of openings may have a periodic one-dimensional array of openings with a regular pitch P, which is the center-to-center distance between adjacent pairs of openings in the photoresist layer. In one embodiment, the rows may be numbered sequentially from one end to the other with integers. In top view, the even-numbered rows may be laterally offset with respect to the odd-numbered rows by half the regular pitch P.

An anisotropic etch process, which etches the material of the first mask material rails 124R selectively to the material of the alternating stack (132,142), silicon oxide layer 121, and diffusion barrier layer 123, may be performed to transfer the pattern of openings in the photoresist layer through the first mask material rails 124R. Each remaining portion of first mask material rail 124R may have a rectangular pillar shape and is referred to herein as a first mask material pillar 124. Adjacent pairs of first mask material pillars 124 in the line trenches 49 may be laterally spaced apart by first pillar shaped cavities 125'. Each of the first cylindrical cavities 125' may have a rectangular horizontal sectional shape. A two-dimensional array of first mask material pillars 124 may be formed within line trenches 49.

Referring to fig. 7A through 7C, an isotropic etching process may be performed that etches the material of the diffusion barrier layer 123 selectively to the material of the silicon oxide layer 121 and the first mask material pillar 124. The physically exposed portions of the diffusion barrier 123 not masked by the two-dimensional array of masking material pillars 125' may be removed by an isotropic etching process. For example, if the diffusion barrier layer 123 includes silicon nitride, a wet etch using hot phosphoric acid may be performed to isotropically etch the unmasked portions of the diffusion barrier layer 123. Each remaining portion of the diffusion barrier layer 123 extends vertically and is referred to herein as a diffusion barrier strip 123'. A row of diffusion barrier strips 123' may be formed on each sidewall of the line trenches 49. Thus, two rows of diffusion barrier strips 123' may be formed within each line trench 49.

Referring to fig. 8A through 8C, the first mask material pillar 124 may be removed selectively for the diffusion barrier stripe 123' and the silicon oxide layer 121. For example, the first mask material pillar 124 may be removed by performing an ashing process. A memory cavity 125 may be formed within each memory opening resulting from the removal of the first mask pillar 124. Each memory cavity 125 may include a volume of a pillar of mask material 125' and a volume of a void formed by removing a row of pillars 124 of first mask material within line trenches 49.

A thermal oxidation process (e.g., similar to a LOCOS process) may be performed to convert surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142 that are adjacent to portions of the silicon oxide layer 121 that are not covered by the diffusion barrier strips 123'. Oxygen atoms diffuse through the portions of the silicon oxide layer 121 not covered by the diffusion barrier strips 123' and into the surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142. The surface portions of the first and second sacrificial material strips 132,142 adjacent to the gaps between the diffusion barrier strips 123 'are oxidized at a higher oxidation rate than the surface portions of the first and second sacrificial material strips 132,142 adjacent to the diffusion barrier strips 123'. The oxidized surface portions of the first sacrificial material strips 132 and the second sacrificial material strips 142 are added to the silicon oxide layer 121 to form the semiconductor oxide layer 122.

Semiconductor oxide layer 122 may include a semiconductor oxide material including silicon, germanium, and oxygen with a compositional modulation. Semiconductor oxide layer 122 includes a higher atomic percentage of germanium atoms at thicker locations than at thinner locations (e.g., bird's beak locations). Because the diffusion barrier strips 123' prevent oxygen from diffusing therethrough, the semiconductor oxide layer 122 is formed with a lateral thickness modulation as shown in fig. 8B and 8C. Specifically, the semiconductor oxide layer 122 is thicker in the region without the diffusion barrier strips 123 'than in the region located behind the diffusion barrier strips 123'. In addition, the silicon germanium alloy oxidizes faster than silicon under the same oxidation conditions. Thus, the second sacrificial material strips 142 oxidize faster than the first sacrificial material strips 132, and the semiconductor oxide layer 122 is thicker at the level of the second sacrificial material strips 142 than at the level of the first sacrificial material strips 132. Thus, semiconductor oxide layer 122 has a vertical thickness modulation (i.e., a modulation of lateral thickness in the vertical direction) such that semiconductor oxide layer 122 is thicker at the level of second sacrificial material strips 142 than at the level of first sacrificial material strips 132.

The ratio of the maximum lateral thickness of the semiconductor oxide layer 122 at a level of the second sacrificial material strips 142 to the maximum lateral thickness of the semiconductor oxide layer 122 at a level of the first sacrificial material strips 132 may be in the range of 1.2 to 5.0, such as 1.5 to 3.0, although smaller and larger ratios may also be used. The ratio of the maximum lateral thickness of the semiconductor oxide layer 122 at a level of the second sacrificial material strips 142 to the minimum lateral thickness of the semiconductor oxide layer 122 at a level of the second sacrificial material strips 142 may be in the range of 1.5 to 10, such as 3 to 6, although smaller and larger ratios may also be used. The ratio of the maximum lateral thickness of the semiconductor oxide layer 122 at a level of the first sacrificial material strips 132 to the minimum lateral thickness of the semiconductor oxide layer 122 at a level of the first sacrificial material strips 132 may be in the range of 1.2 to 3, such as 1.3 to 2, although smaller and larger ratios may also be used. The maximum lateral thickness of the semiconductor oxide layer 122 (which occurs at the level of the second sacrificial material strips 142) may be in the range of 10nm to 60nm, such as 15nm to 30nm, although lesser and greater thicknesses may also be used. The interface between semiconductor oxide layer 122 and second sacrificial material strips 142 may have a greater profile (i.e., have a greater curvature) than the interface between semiconductor oxide layer 122 and first sacrificial material strips 132. Semiconductor oxide layer 122 may be formed as a two-dimensional array having vertically stacked thickened portions. A thickened portion occurs at each level of the second strip of sacrificial material 142.

Referring to fig. 9A to 9C, the diffusion barrier strips 123' may be removed by performing an isotropic etching process such as a wet etching process using hydrofluoric acid. The semiconductor oxide layer 122 may then be removed by another isotropic etch process, such as a wet etch process using dilute hydrofluoric acid. The memory cavity 125 may be expanded by the volume of the diffusion barrier strips 123' and the removed material portions of the semiconductor oxide layer 122. Accordingly, the wire trenches 49 may be modified to provide a two-dimensional array of lateral recesses on each sidewall of the wire trenches 49. Each two-dimensional array of lateral recesses may be laterally bounded by a respective two-dimensional array of lateral recess surfaces of the second strip of sacrificial material 142. Each two-dimensional array of lateral recesses may extend in a lateral direction parallel to the longitudinal direction of the wire groove 49 and in a vertical direction.

Referring to fig. 10A to 10C, the blocking dielectric layer 52 may be formed directly on the sidewalls and bottom surface of the line trench 49 by a conformal deposition process. The blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric materials. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one other non-metallic element, such as nitrogen. In one embodiment, the blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). Alternatively or in addition, the blocking dielectric layer 52 may comprise a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. The thickness of the blocking dielectric layer 52 may be in the range of 3nm to 20nm, although lesser and greater thicknesses may also be used.

Subsequently, a charge storage material layer 54L may be formed. After forming the two-dimensional array of lateral recesses, a layer of charge storage material 54L may be deposited over the blocking dielectric 52. In one embodiment, the charge storage material layer 54L may be a dielectric charge trapping material, which may be, for example, silicon nitride. The charge storage material layer 54L may be formed, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage material layer 54L may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be used.

Referring to fig. 11A through 11C, an anisotropic etching process may be performed to remove vertical portions of the charge storage material layer 54L that are not covered by the blocking dielectric layer 52. An anisotropic etching process is used to remove portions of the charge storage material layer 54L that lie outside the two-dimensional array of lateral recesses. Each remaining portion of the charge storage material layer 54L constitutes a discrete charge storage element 54. A two-dimensional array of discrete charge storage elements 54 may be formed on each longitudinal sidewall of the line trenches 49. Each two-dimensional array of discrete charge storage elements 54 may be formed into a vertical stack of strips 142 of second sacrificial material within a respective alternating stack (132,142) within a respective two-dimensional array of respective lateral recesses. Each discrete charge storage element 54 may have the shape of a curved sheet having curvature in a horizontal cross-section and curvature in a vertical cross-section. Each discrete charge storage element 54 may have a concave inner sidewall and a convex outer sidewall. During the anisotropic etching process, horizontal portions of the charge storage material layer 54L and the blocking dielectric layer 52 may be removed from the bottom of each line trench 49.

Referring to fig. 12A-12C, a tunneling dielectric layer 56 may be formed on physically exposed surfaces of the blocking dielectric layer 52 and the discrete charge storage elements 54. The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by Fowler-Nordheim (Fowler-Nordheim) tunneling. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxide (such as aluminum oxide or hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be used. A set of blocking dielectric layers 52, discrete charge storage elements 54, and tunneling dielectric layer 56 constitute the memory film 50.

A tunneling dielectric layer 56 may be formed over each two-dimensional array of discrete charge storage elements located within a respective two-dimensional array of lateral recesses. The horizontal portion of the tunnel dielectric layer 56 may be removed from the bottom portion of each line trench 49 by an anisotropic etching process. A layer of sacrificial capping material (not shown) may be used to protect the vertical portions of the tunneling dielectric layer 56 during the anisotropic etch process and may be subsequently removed.

Subsequently, a semiconductor channel material layer 60L may be optionally formed on the memory film 50. The semiconductor channel material layer 60L may directly contact the physically exposed top surface of the semiconductor material layer 10. The semiconductor channel material layer 60L includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In thatIn one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polysilicon. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2nm to 10nm, but lesser and greater thicknesses may also be used. In one embodiment, the semiconductor channel material layer 60L may have a doping of a first conductivity type that is the same as the doping of the semiconductor material layer 10. In one embodiment, the semiconductor channel material layer 60L may comprise a semiconductor material including an atomic concentration of 1.0 x 10¹⁴/cm³To 1.0X 10¹⁸/cm³Electrical dopants within the range.

A mask material may be deposited in the remaining volume of the line trenches 49. Excess portions of the mask material may be removed from over a top surface of horizontal portions of the semiconductor channel material layer 60L overlying the alternating stack (132, 142). The remaining portion of the mask material in the line trench 49 constitutes a second mask material rail 126R. The second mask material rail 126R may have a laterally modulated horizontal cross-sectional profile in a horizontal cross-section and may have a laterally modulated vertical cross-sectional profile in a vertical cross-section perpendicular to a longitudinal direction of the second mask material rail 126R. In one embodiment, the second mask material rail 126R may comprise a carbon-based material. In one embodiment, the second mask material rails 126R may comprise spin-on carbon that may be applied by spin-coating and subsequently dried.

Referring to fig. 13A-13C, a photoresist layer (not shown) may be applied over the first exemplary structure and may then be patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include a plurality of rows of openings overlying a respective one of the line trenches 49. The row-to-row spacing within the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the line trenches 49. Each row of openings may have a periodic one-dimensional array of openings having a regular pitch P, which is the lateral distance between the center points of the two-dimensional array of lateral recesses within the second strip of sacrificial material 142 in the alternating stack (132, 142). In one embodiment, the location of the openings in the photoresist layer may be laterally offset by half the regular pitch p from the location of the openings in the photoresist layer used at the processing steps of fig. 6A-6C.

An anisotropic etch process, which etches the material of the second mask material rails 124R selectively to the material of the alternating stack (132,142), memory film 50, and semiconductor channel material layer 60L, may be performed to transfer the pattern of openings in the photoresist layer through the second mask material rails 126R. Each remaining portion of the second mask material rail 126R may have a rectangular pillar shape and is referred to herein as a second mask material pillar 126. A two-dimensional array of second mask material pillars 126 may be formed. Adjacent pairs of second mask material posts 126 in line trenches 49 are laterally spaced apart by second cylindrical cavities 127. Each second cylindrical cavity 127 may have a rectangular horizontal cross-sectional shape. A row of pillars 126 of second mask material is formed in each line trench 49. Each row of second mask material pillars 126 may be interleaved with a row of second pillar cavities 127 within a respective line channel 49. The second pillar of mask material 126 may be formed in a region where a pair of concave sidewalls of two second rails 142 of sacrificial material facing the same line trench 49 are laterally spaced apart by a maximum lateral spacing. Second pillar cavities 127 may be formed in the gap regions between adjacent pairs of discrete charge storage elements 54.

Referring to fig. 14A-14C, an isotropic etching process may be performed to etch the physically exposed portions of semiconductor channel material layer 60L surrounding each second cylindrical cavity 127. For example, a wet etching process using tetramethylammonium hydroxide (TMAH) may be performed to etch the semiconductor material of the semiconductor channel material layer 60L. Each remaining portion of the semiconductor channel material layer 60L covered by the second mask material pillar 126 constitutes a vertical semiconductor channel 60. Each combination of a vertical semiconductor channel 60 and an adjacent portion of the memory film 50 constitutes a memory stack structure 55. Each memory stack structure 55 includes a vertical stack of memory elements embodied as a vertical stack of discrete charge storage elements 54. A row of vertical semiconductor channels 60 is formed over each tunnel dielectric layer 56. Each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60 laterally overlies a respective vertical stack of discrete charge storage elements 54.

Referring to fig. 15A through 15C, the second mask material pillar 126 may be selectively removed with respect to the vertical semiconductor channel 60 and the memory film 50. For example, the second mask material pillar 126 may be removed by ashing. A line cavity 129 may be formed within each unfilled volume of line trench 49.

Referring to fig. 16A-16C, 17A and 17B, a dielectric material such as undoped silicate glass or doped silicate glass may be deposited in the remaining volume of the line trench 49. The portion of the dielectric material above the horizontal plane including the topmost first sacrificial material strips 132 may be removed by a planarization process, such as recess etching or chemical mechanical planarization. Each remaining portion of the dielectric material constitutes a dielectric core 62. In one embodiment, each dielectric core 62 contacts two rows of vertical semiconductor channels 60 and two tunneling dielectric layers 56.

Referring to fig. 18A-18B, the upper end of each dielectric core 62 may be vertically recessed, for example, by applying a photoresist layer over the first exemplary structure and patterning it to form an opening overlying the dielectric core 62 and by performing an etching process, which may be an anisotropic etching process or an isotropic etching process. The photoresist layer may be removed and a doped semiconductor material having a doping of the second conductivity type may be deposited in the recess to form the drain region 63. The second conductive type may be opposite to the first conductive type, and the atomic concentration of the dopant of the second conductive type in the drain region 63 may be 5.0 × 10¹⁹/cm³To 2.0X 10²¹/cm³But smaller and larger atomic concentrations may also be used.

Referring to fig. 19A and 19B, the backside via cavities 79 may be formed through the isolation regions of the dielectric core 62 such that the remaining material portion within each line trench 49 includes at least one memory stack assembly 409. Each memory stack component 409 includes two rows of vertical semiconductor channels 60 connected to one row of drain regions 63. The locations of the backside via cavities 79 can be selected such that each second sacrificial material strip 142 contacts at least one of the backside via cavities 79. Additionally, the location of the backside via cavities 79 may be selected such that each point within the second strip of sacrificial material 142 is laterally spaced from a nearest one of the backside via cavities 79 by a lateral distance that does not exceed a lateral etch distance during a subsequent isotropic etch process.

The memory stack components 409 are formed in each volume comprising a combination of the volume of the initially formed line trenches 49 and the volume of two contiguous two-dimensional arrays of lateral recesses formed over the sidewalls of the second sacrificial material strips 142. Each of the memory stack components 409 includes two-dimensional arrays of lateral protruding regions, and each of the lateral protruding regions includes a respective charge storage element, i.e., a discrete charge storage element 54. Each of the memory stack components 409 includes two rows of vertical semiconductor channels 60.

Referring to fig. 20, an etchant may be introduced into the backside via cavities 79, for example using an isotropic etching process, which etches the material of the second sacrificial material strips 142 selectively to the material of the first sacrificial material strips 132, the barrier dielectric layer 52, and the dielectric core 62. Backside recesses 143 can be formed in the volume from which second sacrificial material strips 142 are removed. In one embodiment, the second sacrificial material strips 142 may comprise a silicon germanium alloy and the material of the first sacrificial material strips 132 may comprise silicon. In this case, the isotropic etching process may include a wet etching process using a combination of phosphoric acid and hydrogen peroxide.

The duration of the isotropic etching process may be selected such that the second strip of sacrificial material 142 is completely removed from each alternating stack (132,142) of first and second strips of

sacrificial material

132, 142. Each backside recess 143 can be a laterally extending cavity having a lateral dimension greater than a vertical extent of the cavity. In other words, the lateral dimension of each backside recess 143 may be greater than the height of the backside recess 143.

In one implementation, the memory array region 100 includes a monolithic three dimensional array of NAND strings having a plurality of device levels disposed above a substrate (9, 10). In this case, each backside recess 143 can define a space for receiving a respective word line of the monolithic three-dimensional NAND string array. Each backside recess of the plurality of backside recesses 143 may extend substantially parallel to a top surface of the substrate (9, 10). Backside recesses 143 can be vertically defined by a top surface of an underlying first sacrificial material strip 132 and a bottom surface of an overlying first sacrificial material strip 132. In one embodiment, each backside recess 143 can have a uniform height throughout. The memory stack component 409 provides structural support for the first exemplary structure during formation of the backside recesses 143.

Referring to fig. 21 and 22A-22C, a backside blocking dielectric layer (not shown) may optionally be formed in the backside recesses 143 by a conformal deposition process. For example, the backside blocking dielectric layer may comprise a dielectric metal oxide (such as aluminum oxide). The conformal deposition process may include, for example, an Atomic Layer Deposition (ALD) process. The thickness of the backside blocking dielectric layer may be in the range of 1nm to 6nm, but smaller and larger thicknesses may also be used.

At least one conductive material may be deposited in the remaining volume of the backside recess 143. For example, without the use of a backside blocking dielectric layer, metal barrier layer 146A may be deposited directly on the physically exposed surfaces of the backside blocking dielectric layer in backside recesses 143, or on the physically exposed surfaces of blocking dielectric 52 and first sacrificial material strips 132. The metal barrier layer 146A comprises a conductive metallic material that can act as a diffusion barrier and/or adhesion promoting layer for subsequently deposited metallic filler materials. The metallic barrier layer 146A may comprise a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, metallic barrier layer 146A may be deposited by a conformal deposition process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The thickness of the metallic barrier layer 146A may be in the range of 2nm to 8nm, such as 3nm to 6nm, although lesser and greater thicknesses may also be used. In one embodiment, metal barrier layer 146A may consist essentially of a conductive metal nitride such as TiN.

A metallic fill material 146B is deposited in the remaining volume of the backside recesses 143, on the sidewalls of the at least one backside via cavity 79, and over the topmost first sacrificial material strip 132. The metal fill material 146B can be deposited by a conformal deposition method, which can be, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroless plating, electroplating, or combinations thereof. In one embodiment, the metallic filler material 146B may consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material 146B may be selected from, for example, tungsten, cobalt, ruthenium, molybdenum, titanium, and tantalum. In one embodiment, the metallic filler material 146B may consist essentially of a single elemental metal. In one embodiment, the metallic filler material 146B may use a fluorine-containing precursor gas such as WF₆And (6) carrying out deposition. In one embodiment, the metallic fill material 146B may comprise tungsten including a residual level of boron, fluorine, or silicon atoms as impurities.

A plurality of conductive strips 146 (i.e., conductive strips having a strip shape) may be formed in the plurality of backside recesses 143, and a continuous layer of metallic material may be formed on the sidewalls of each backside via cavity 79 and over the topmost first sacrificial material strip 132. Each conductive strip 146 includes a portion of a metal barrier layer 146A and a metal fill material 146B located between vertically adjacent pairs of first sacrificial material strips 132.

The deposited metallic material of the continuous layer of conductive material is etched back, for example by isotropic wet etching, anisotropic dry etching, or a combination thereof, from the sidewalls of each backside via cavity 79 and from above the topmost first strip of sacrificial material 132. Each remaining portion of the deposited metallic material in the backside recesses 143 constitutes a conductive strip 146. Each conductive strip 146 may be a conductive line structure. Thus, second sacrificial material strip 142 may be replaced with conductive strip 146.

Each conductive strip 146 may function as a combination of a plurality of control gate electrodes at the same level and a word line electrically interconnected (i.e., electrically shorted) with the plurality of control gate electrodes at the same level. The plurality of control gate electrodes within each conductive strip 146 are the control gate electrodes for the NAND strings in the line trenches 49. In other words, each conductive stripe 146 may be a word line that serves as a common control gate electrode for the plurality of vertical memory devices. Each vertical semiconductor channel 60 has a laterally undulating vertical cross-sectional profile and includes a vertical stack of lateral bump portions at the level of the conductive strip 146 within the lateral recess, into the concave surface of the conductive strip 146. A two-dimensional array of transverse raised areas 410 is provided on each longitudinal side wall of the wire groove 49.

Referring to fig. 23 and 24A-24C, the first sacrificial material strips 132 may be removed selectively to the conductive strips 146, the layer of semiconductor material 10, and the outermost layer of the memory film 50 (i.e., the blocking dielectric layer 52). Cavities free of solid material may be formed in the volume from which the first strips of sacrificial material 132 are removed. Each of the cavities has the shape of a strip and is referred to herein as an air gap strip 133. As used herein, an "air gap" element refers to any element that does not contain any solid material therein. The air gap strips may be under vacuum or may be filled with at least one gas phase material, which may be an inert backfill gas or dry air.

Referring to fig. 25A and 25B, a dielectric material such as silicon oxide is anisotropically deposited within the backside via cavities 79 and in the volume of the topmost air gap strips 133. Anisotropic deposition of dielectric materials may be performed by Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the dielectric material is directionally deposited. Excess portions of the deposited dielectric material may be removed from above a horizontal plane including the top surface of the backward stepped dielectric material portion 65. Each portion of the dielectric material deposited in the backside via cavity 79 forms an air gap post 76 that encapsulates a void therein. The voids in the air-gap pillars 76 may be free of any solid phase material. The portion of the deposited dielectric material in the topmost air gap strip 133 constitutes the insulating cap layer 70. The curvature of the elements shown in the foregoing close-up figures is not shown in fig. 25B, as fig. 25B is an expanded top view in which the curvature is not visible in scale of the figure.

Referring to fig. 1-25B and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided that includes alternating stacks of conductive strips 146 and air gap strips 133 that are located over a substrate (9,10) and are laterally spaced from each other by a memory stack assembly 409. The memory stack assemblies 409 extend laterally along a first horizontal direction hd1 and are spaced apart from each other along a second horizontal direction hd 2. Each of the memory stack components 409 includes two-dimensional arrays (e.g., when viewed in vertical cross-section) of lateral protruding regions 410. Each lateral protruding region 410 protrudes laterally outward (i.e., away from the center of the memory stack assembly 409) from a respective vertical plane that includes the interface between a respective one of the memory stack assemblies 409 and the air gap strips within a respective one of the alternating stacks (146,133). Each of the lateral protruding regions 410 includes a respective charge storage element 54, each of the memory stack assemblies 409 includes two rows of vertical semiconductor channels 60, and each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60 laterally overlies a respective vertical stack of charge storage elements 54.

In one embodiment, each of the memory stack components 409 includes two tunneling dielectric layers 56; and each of the two tunneling dielectric layers 56 contacts a corresponding row of vertical semiconductor channels 60 selected from the two rows of vertical semiconductor channels 60.

In one embodiment, each of the memory stack assemblies 409 includes a dielectric core 62 that extends laterally along the first horizontal direction hd1 and contacts the inner sidewalls of each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60. In one embodiment, the vertical semiconductor channels 60 within each row of vertical semiconductor channels 60 are laterally spaced apart along the first horizontal direction hd1 by a vertically extending region in which the dielectric core 62 contacts one of the two tunneling dielectric layers 56.

In one embodiment, each of the two tunneling dielectric layers 56 contacts a two-dimensional array of charge storage elements 54 located in a two-dimensional array of lateral protrusion regions 410.

In one embodiment, each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60 includes a vertical stack of lateral bump portions at the level of the conductive strip 146.

In one embodiment, each of the memory stack components 409 includes two blocking dielectric layers 52; and each of the two blocking dielectric layers 52 contacts a respective one of the two tunneling dielectric layers 56 at each level of the air-gap strips 133 and between each adjacent pair of the vertical stacks of charge storage elements 54. In one embodiment, each of the conductive strips 146 includes a respective metal barrier layer 146A and a respective portion of a metallic fill material 146B formed within the respective metal barrier layer 146A; and each of the two barrier dielectric layers 52 contacts a sidewall of a subset of the metallic barrier layers 146A.

In one embodiment, the charge storage elements 54 comprise discrete floating gate or dielectric charge trapping material portions that do not contact each other. In one embodiment, each of the charge storage elements 54 includes a concave inner sidewall having a horizontal concave profile in a horizontal cross-section and a convex outer sidewall having a horizontal convex profile in a horizontal cross-section.

In one embodiment, in a vertical cross-sectional view, the concave inner sidewalls have vertical concave profiles at upper and lower edge regions of the respective charge storage elements 54; and in vertical cross-section the convex outer sidewall has a vertical convex profile at the upper and lower edge regions of the respective charge storage element 54.

In one embodiment, each of the charge storage elements 54 is located between a first horizontal plane including a top surface of a respective one of the conductive strips 146 and a second horizontal plane including a bottom surface of a respective one of the conductive strips 146.

Referring to fig. 26, a second exemplary structure according to a second embodiment of the present disclosure is shown, which includes a substrate (9,10), which may be the same as the substrate (9,10) of the first exemplary structure.

A vertically alternating sequence of first material layers, such as insulating layers 32L, and second material layers, such as spacer material layers, is formed over the substrates (9, 10). The vertically alternating sequence may include a stack of alternating pluralities of first material layers (which may be insulating layers 32L) and second material layers (which may be sacrificial material layers 42L). Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32L, and each second material layer may be a sacrificial material layer. In this case, the stack may include a plurality of alternating insulating layers 32L and sacrificial material layers 42L, and constitute a prototype stack including alternating layers of insulating layers 32L and sacrificial material layers 42L.

In one embodiment, the vertically alternating sequence (32L,42L) may include insulating layers 32L composed of a first material and sacrificial material layers 42L composed of a second material, wherein the second material is different from the material of the insulating layers 32L. The first material of the insulating layer 32L may be at least one insulating material. Accordingly, each insulating layer 32L may be a layer of insulating material. Insulating materials that may be used for the insulating layer 32L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 32L may be silicon oxide. The second material of the sacrificial material layer 42L is a sacrificial material that is selectively removable with respect to the first material of the insulating layer 32.

The sacrificial material layer 42L may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42L may then be replaced with a conductive electrode that may serve as, for example, a control gate electrode for a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polysilicon). In one embodiment, the sacrificial material layer 42L may be a spacer material layer comprising silicon nitride or a semiconductor material comprising at least one of silicon and germanium.

In one embodiment, the insulating layer 32L may comprise silicon oxide and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of the insulating layer 32L may be deposited, for example, by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the insulating layer 32L, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the sacrificial material layer 42L may be formed, such as CVD or Atomic Layer Deposition (ALD).

The thickness of the insulating layer 32L and the sacrificial material layer 42L may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each insulating layer 32L and each sacrificial material layer 42L. The number of repetitions of the pair of insulating layers 32L and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42L may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although greater numbers of repetitions may also be used. The top gate electrode and the bottom gate electrode in the stack may be used as select gate electrodes. In one embodiment, each sacrificial material layer 42L in the vertically alternating sequence (32L,42L) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42L.

Alternatively, successive insulating cap layers 70L may be formed over the vertically alternating sequence (32L, 42L). The continuous insulating cap layer 70L comprises a dielectric material that is different from the material of the sacrificial material layer 42L. In one embodiment, the continuous insulating cap layer 70L may comprise a dielectric material as may be used for the insulating layer 32L as described above. The continuous insulating cap layer 70L may have a greater thickness than each of the insulating layers 32L. The continuous insulating cap layer 70L may be deposited, for example, by chemical vapor deposition. In one embodiment, the continuous insulating cap layer 70L may be a silicon oxide layer.

Referring to fig. 27, the vertically alternating sequence of insulating layers 32L and spacer material layers (i.e., sacrificial material layers 42L) may be patterned to form a stepped surface that continuously extends from a bottommost layer of the vertically alternating sequence (32L,42L) to a topmost layer of the alternating sequence (32L,42L) in the contact region 300. The stepped cavity may be formed within a contact region 300 that may be located between the memory array region 100 and a peripheral device region (not shown) that contains at least one semiconductor device for peripheral circuitry. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity varies stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the cavity depth by one or more levels and a second type of etching process that laterally extends the region to be vertically etched in a subsequent etching process of the first type.

By forming stepped cavities, stepped surfaces are formed at peripheral portions of the vertically alternating series (32L, 42L). The land regions are formed by patterning vertically alternating sequences (32L, 42L). Each sacrificial material layer 42L within the vertically alternating sequence (32L,42L) except for the topmost sacrificial material layer 42L extends laterally further than any overlying sacrificial material layer 42L within the vertically alternating sequence (32L, 42L). The land areas include stepped surfaces of the vertically alternating series (32L,42L) that continuously extend from a bottom-most layer within the vertically alternating series (32L,42L) to a top-most layer within the vertically alternating series (32L, 42L).

The backward stepped dielectric material portion 65 (i.e., the insulating fill material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from over the top surface of the continuous insulating cap layer 70L, for example, by Chemical Mechanical Planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes a backward stepped dielectric material portion 65. If silicon oxide is used for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may or may not be doped with dopants, such as B, P and/or F.

Referring to fig. 28A, 28B, and 29A-29C, a photolithographic material stack (not shown) including at least a photoresist layer may be formed over the continuous insulating cap layer 70L and the retro-stepped dielectric material portion 65, and may be lithographically patterned to form linear openings therein. The linear opening extends laterally along the first horizontal direction hd1, and has a uniform width along the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. The pattern in the stack of photolithographic material can be transferred through the continuous insulating capping layer 70L or the retro-stepped dielectric material portions 65 and through the vertically alternating sequence (32L,42L) by at least one anisotropic etch using the patterned stack of photolithographic material as an etch mask. Portions of the vertically alternating sequence (32L,42L) underlying the line-shaped openings in the patterned stack of photolithographic material are etched to form line trenches 49. As used herein, "line trench" refers to a trench that extends transversely straight in the horizontal direction.

The line trenches 49 extend transversely across the vertically alternating series (32L,42L) in a first horizontal direction hd 1. In one embodiment, the wire groove 49 has a corresponding uniform width that is constant during translation in the first horizontal direction hd 1. In one embodiment, the wire grooves 49 may have the same width throughout, and the spacing between adjacent pairs of wire grooves 49 may be the same. In this case, the line trenches 49 may constitute a one-dimensional periodic array of line trenches 49 having a pitch in the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1. The width of the line trench 49 in the second horizontal direction hd2 may be in the range 30nm to 500nm, such as 60nm to 250nm, but smaller and larger widths may also be used.

The line trenches 49 extend through each layer of the vertically alternating sequence (32L,42L) and the rearwardly stepped dielectric material portions 65. The chemistry of the anisotropic etching process used to etch through the material of the vertically alternating series (32L,42L) can be alternated to optimize the etching of the first and second materials in the vertically alternating series (32L, 42L). The anisotropic etch may be, for example, a series of reactive ion etches. The sidewalls of the line trench 49 may be substantially vertical or may be tapered. The patterned stack of photolithographic material can then be removed, for example, by ashing.

The line trenches 49 extend laterally across the entire memory array region 100 and laterally into the contact regions 300. The line trench 49 may extend laterally across the entire contact region 300 in the first horizontal direction hd1, or may extend laterally across only a portion of the width of the contact region 300 instead of the entire width of the first horizontal direction hd1 of the contact region. In one embodiment, the overetch of the semiconductor material layer 10 may optionally be performed after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each line trench 49. The overetch may be performed before or after the stack of photolithographic materials is removed. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the un-recessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth may be in the range of, for example, 1nm to 50nm, although lesser and greater depths may also be used. The over-etching is optional and may be omitted. If no over-etching is performed, the bottom surface of the line trench 49 may be coplanar with the topmost surface of the layer of semiconductor material 10 (or coplanar with the substrate semiconductor layer 9 in embodiments where the layer of semiconductor material 10 is not used).

Each of the line trenches 49 may include a sidewall (or sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. The substrate semiconductor layer 9 and the semiconductor material layer 10 jointly constitute a substrate (9,10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the line trench 49 may extend to the top surface of the substrate semiconductor layer 9.

The vertically alternating series (32L,42L) and continuous insulating cap layer 70L are divided into discrete portions by the line trenches 49. Each remaining portion of the vertically alternating sequence (32L,42L) between a pair of line trenches 49 constitutes an alternating stack of remaining portions of the insulating layer 32L and remaining portions of the sacrificial material layer 42L. Each remaining portion of the insulating layer 32L may have a rectangular stripe shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as an insulating stripe 32. Each remaining portion of the sacrificial material layer 42L may have a rectangular strip shape extending laterally along the first horizontal direction hd1 and having a uniform width along the second horizontal direction hd2, and is referred to herein as a sacrificial material strip 42. An alternating stack of insulating strips 32 and sacrificial material strips 42 is formed between each adjacent pair of line trenches 49 above the substrates (9, 10). The alternating stacks (32,42) are laterally spaced from each other by a wire groove 49 extending laterally along the first horizontal direction hd 1. Each remaining portion of the continuous insulating cap layer 70L is referred to herein as an insulating cap layer 70 overlying a respective one of the alternating stacks (32, 42).

Referring to fig. 30A-30C, a mask material may be deposited in the remaining volume of the line trench 49. Excess portions of the masking material may be removed from above a horizontal plane including the top surface of the insulating cap layer 70. The remaining portion of the mask material in the line trench 49 constitutes a first mask material rail 222R. In one embodiment, the first mask material rail 222R may have a uniform vertical sectional shape in a plane perpendicular to the longitudinal direction of the wire groove 49. In one embodiment, the vertical cross-sectional shape of the first mask material rail 222R may be rectangular or trapezoidal with a top width greater than a bottom width. In one embodiment, the first mask material rail 222R may include a carbon-based material. In one embodiment, first mask material rails 222R may comprise spin-on carbon that may be applied by spin-coating and subsequently dried.

Referring to fig. 31A-31C, a photoresist layer (not shown) may be applied over the first exemplary structure, and may then be patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include a plurality of rows of openings overlying a respective one of the line trenches 49. The row-to-row spacing within the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the line trenches 49. Each row of openings may have a periodic one-dimensional array of openings with a regular pitch P, which is the center-to-center distance between adjacent pairs of openings in the photoresist layer. In one embodiment, the rows may be numbered sequentially from one end to the other with integers. In top view, the even-numbered rows may be laterally offset with respect to the odd-numbered rows by half the regular pitch P.

An anisotropic etch process, which etches the material of the first mask material rails 222R selectively to the material of the alternating stack (32,42), can be performed to transfer the pattern of openings in the photoresist layer through the first mask material rails 222R. Each remaining portion of first mask material rail 222R may have a rectangular pillar shape and is referred to herein as a first mask material pillar 222. Adjacent pairs of first mask material pillars 222 in the line trenches 49 are laterally spaced apart by first pillar-shaped cavities 223. Each of the first cylindrical cavities 223 may have a rectangular horizontal sectional shape. A two-dimensional array of first mask material pillars 222 is formed within line trenches 49.

Referring to fig. 32A-32C, an isotropic etching process is performed to laterally recess the physically exposed surfaces of the sacrificial material strips 42 selective to the material of the insulating strips 32, the insulating cap layer 70, and the semiconductor material layer 10. When the two-dimensional array of first mask material pillars 222 in the line trenches 49 is present within the line trenches 49, the sacrificial material strips 42 are laterally recessed selective to the insulating strips 32, thereby blocking isotropic etchant from reaching the mask portions of the sacrificial material strips 42. For example, if the sacrificial material strips 42 comprise silicon nitride, a wet etch process using hot phosphoric acid may be used to isotropically recess the sidewalls of the sacrificial material strips 42 to form lateral recesses, i.e., regions in which the sidewalls of the sacrificial material strips 42 are laterally recessed to the sidewalls of the overlying or underlying insulating strips 32. A two-dimensional array of lateral recesses may be formed on each sidewall of the line trenches 49. The lateral recess distance between the recess sidewalls of the sacrificial material strips 42 and the overlying or underlying insulating strips 32 may be in the range of 3nm to 60nm, such as 6nm to 30nm, although smaller and larger recess distances may also be used.

Referring to fig. 33A-33C, first masking material pillars 222 may be selectively removed for the alternating stack (32,42) and insulating capping layer 70. For example, the first mask material pillars 222 may be removed by performing an ashing process. The line trenches 49 are modified to provide a two-dimensional array of lateral recesses on each sidewall of the line trenches 49. Each two-dimensional array of lateral recesses may be laterally bounded by a respective two-dimensional array of lateral recess surfaces of the strip of sacrificial material 42. Each longitudinal sidewall of the wire groove 49 may include a two-dimensional array of transverse recesses.

Referring to fig. 34A-34C, a continuous layer stack of a blocking dielectric layer 52, a charge storage material layer 54L, and a tunneling dielectric layer 56 may be formed on the sidewalls of the line trenches 49. A barrier dielectric layer 52 is formed directly on the sidewalls and bottom surface of the line trenches 49 by a conformal deposition process. The blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric materials. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one other non-metallic element, such as nitrogen. In one embodiment, the blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). Alternatively or in addition, the blocking dielectric layer 52 may comprise a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. The thickness of the blocking dielectric layer 52 may be in the range of 3nm to 20nm, although lesser and greater thicknesses may also be used.

Subsequently, a charge storage material layer 54L may be formed. After forming the two-dimensional array of lateral recesses, a layer of charge storage material 54L may be deposited over the remaining portions of the alternating strips 42. In one embodiment, the charge storage material layer 54L may be a dielectric charge trapping material, which may be, for example, silicon nitride. The charge storage material layer 54L may be formed, for example, by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage material layer 54L may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be used.

In an alternative embodiment, the floating gate structure may be formed by anisotropically etching the charge storage material layer 54L. In this case, the portion of the charge storage material layer 54L located inside the lateral recess portion may not be removed by the anisotropic etching process, and the portion of the charge storage material layer 54L located outside the lateral recess portion may be removed by the anisotropic etching process. A two-dimensional array of discrete floating gate structures may be formed within each two-dimensional array of lateral recesses located on each longitudinal sidewall of the line trenches 49. The collection of all two-dimensional arrays of discrete floating gate structures constitutes a three-dimensional array of discrete floating gate structures.

A tunneling dielectric layer 56 is formed over the layer of charge storage material 54L or the three-dimensional array of discrete floating gate structures. The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by fowler-nordheim tunneling. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxide (such as aluminum oxide or hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, although lesser and greater thicknesses may also be used.

Referring to fig. 35A-35C, an anisotropic etch process may be performed to remove horizontal portions of the continuous layer stack of the blocking dielectric layer 52, the charge storage material layer 54L, and the tunneling dielectric layer 56. During the anisotropic etch process, horizontal portions of the continuous layer stack may be removed from the bottom of each line trench 49 and from above the insulating cap layer 70. A top surface of the semiconductor material layer 10 may be physically exposed at the bottom of each line trench 49. Each layer in the continuous layer stack of blocking dielectric layer 52, charge storage material layer 54L, and tunneling dielectric layer 56 is divided into a plurality of discrete portions. The layer stack of the blocking dielectric layer 52, the charge storage material layer 54L and the tunneling dielectric layer 56 on the longitudinal sidewalls of the line trench 49 is referred to herein as a memory film 50.

Referring to fig. 36A to 36C, a semiconductor channel material layer 60L may be optionally formed on the memory film 50. The semiconductor channel material layer 60L may directly contact the physically exposed top surface of the semiconductor material layer 10. The semiconductor channel material layer 60L includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polysilicon. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2nm to 10nm, but lesser and greater thicknesses may also be used. In one embodiment, the semiconductor channel material layer 60L may have a doping of a first conductivity type that is the same as the doping of the semiconductor material layer 10. In one embodiment, the semiconductor channel material layer 60L may comprise a semiconductor material including an atomic concentration of 1.0 x 10¹⁴A/cm to 1.0X 10¹⁸/cm³Electrical dopants within the range.

Referring to fig. 37A-37C, a mask material may be deposited in the remaining volume of the line trench 49 to form a mask material layer 226L. In one embodiment, the mask material may include a carbon-based material. In one embodiment, the mask material may comprise spin-on carbon that may be applied by spin-coating and subsequently dried.

Referring to fig. 38A-38C, excess portions of the mask material may be removed from over the top surface of the insulating cap layer 70. The remaining portion of the mask material in the line trench 49 constitutes a second mask material rail 226R. The second mask material rail 226R may have a laterally modulated horizontal cross-sectional profile in a horizontal cross-section and may have a laterally modulated vertical cross-sectional profile in a vertical cross-section perpendicular to a longitudinal direction of the second mask material rail 226R. The horizontal portions of the semiconductor channel material layer 60L overlying the insulating cap layer 70 may then be removed, for example, by a recess etch.

Referring to fig. 39A-39C, a photoresist layer (not shown) may be applied over the first exemplary structure, and may then be patterned to form an array of openings. In one embodiment, the array of openings in the photoresist layer may be a two-dimensional periodic array of discrete openings. In one embodiment, the two-dimensional periodic array of discrete openings may include a plurality of rows of openings overlying a respective one of the line trenches 49. The row-to-row spacing within the two-dimensional periodic array of discrete openings may be the same as the center-to-center spacing between the line trenches 49. Each row of openings may have a periodic one-dimensional array of openings having a regular pitch P, which is the lateral distance between the center points of the two-dimensional array of lateral recesses within the sacrificial material strips 42 in the alternating stack (32, 42). In one embodiment, the location of the openings in the photoresist layer may be laterally offset by half the regular pitch p from the location of the openings in the photoresist layer used at the processing steps of fig. 31A-31C.

An anisotropic etch process, which etches the material of the second mask material rails 222R selectively to the material of the alternating stack (32,42), memory film 50, and semiconductor channel material layer 60L, may be performed to transfer the pattern of openings in the photoresist layer through the second mask material rails 226R. Each remaining portion of second mask material rail 226R may have a rectangular pillar shape and is referred to herein as a second mask material pillar 226. A two-dimensional array of second mask material pillars 226 may be formed. Adjacent pairs of second mask material posts 226 in line trenches 49 are laterally spaced apart by second post cavities 227. Each second cylindrical cavity 227 may have a rectangular horizontal cross-sectional shape. A row of pillars 226 of second mask material is formed in each line trench 49. Each row of second mask material pillars 226 is interleaved with a row of second pillar cavities 227 within a respective line channel 49. The second masking material pillar 226 may be formed in a region where a pair of concave sidewalls of two second sacrificial material rails 42 facing the same line trench 49 are laterally spaced apart by a maximum lateral spacing. The second cylindrical cavities 227 may be formed in the gap regions between adjacent pairs of un-recessed sidewalls of the sacrificial material strips 42.

Referring to fig. 40A-40C, an isotropic etching process is performed to etch the physically exposed portions of semiconductor channel material layer 60L surrounding each second cylindrical cavity 227. For example, a wet etching process using tetramethylammonium hydroxide (TMAH) may be performed to etch the semiconductor material of the semiconductor channel material layer 60L. Each remaining portion of the semiconductor channel material layer 60L covered by the second mask material pillar 226 constitutes a vertical semiconductor channel 60. A row of vertical semiconductor channels 60 is formed over each tunnel dielectric layer 56. A two-dimensional array of transverse raised areas 510 is provided on each longitudinal sidewall of the wire groove 49.

At least one isotropic etching process is performed to etch unmasked portions of the memory film 50. For example, the unmasked portions of tunneling dielectric layer 56, charge storage material layer 54L, and blocking dielectric layer 52 around each second cylindrical cavity 227 may be sequentially etched using a series of wet etch processes. The portions of memory film 50 not masked by second masking material pillars 226 are isotropically etched. The remaining portions of the tunneling dielectric layer 56, the charge storage material layer 54L, and the blocking dielectric layer 52 have respective stripe shapes and are positioned adjacent to a respective one of the vertical semiconductor channels 60.

The remaining portions of the vertical semiconductor channel 60 and the memory film 50 constitute strips of material stack that extend into the strips of sacrificial material 42 over the vertical stacks of lateral recesses. Each of the strips of material stacks includes a blocking dielectric layer 52 contacting the insulating strip 32 within a respective one of the alternating stacks (32,42), a layer of charge storage material 54L contacting the blocking dielectric layer 52 and including the vertical stack of charge storage elements, a tunneling dielectric layer 56 contacting the layer of charge storage material 54L, and a vertical semiconductor channel 60 contacting the tunneling dielectric layer 56. Each strip of material stack is referred to herein as a memory stack structure 55 that includes a memory film 50 (as patterned into a strip shape) and a vertical semiconductor channel 60.

Each memory film 50 within the line trench 49 is divided into a laterally spaced row of memory films 50. Each combination of the vertical semiconductor channel 60 and the memory film 50 constitutes a memory stack structure 55. Each memory stack structure 55 includes a vertical stack of memory elements embodied as a portion of the layer of charge storage material 54L at the level of the strip of sacrificial material 42. Each vertical semiconductor channel 60 laterally overlies a respective vertical stack of charge storage material layers 54L. Each line trench 49 may include two rows of stacked strips of material (including memory stack structures 55) extending vertically and laterally overlying sidewalls of a respective one of the alternating stacks (32, 42). Each row of material stack strips includes a respective plurality of material stack strips spaced laterally apart along the first horizontal direction hd 1. Each of the strips of material stacks includes a respective layer of charge storage material 54L including charge storage elements within each respective vertical stack of lateral recesses selected from the two-dimensional array of lateral recesses.

Each charge storage element is embodied as part of a layer of charge storage material 54L located at a level of the strip of sacrificial material 42 and having a pair of concave inner side wall segments connected by a straight inner side wall segment, as shown in fig. 40C. The pair of concave inner sidewall sections of each charge storage element contacts the pair of convex outer sidewall sections of the vertical semiconductor channel 60. The straight inner sidewall segments of each charge storage element contact the straight outer sidewall segments of the vertical semiconductor channel 60, as shown in fig. 40C. Each charge storage element has a pair of convex outer sidewall sections having respective horizontal convex profiles in horizontal cross-section. The pair of convex outer side wall sections may be connected to each other by a straight outer side wall section. The pair of convex outer sidewall sections of each charge storage element contacts the pair of concave inner sidewall sections of blocking dielectric layer 52. The straight outer sidewall segments of each charge storage element contact the straight inner sidewall segments of the blocking dielectric layer 52, as shown in fig. 40C.

Referring to fig. 41A through 41C, the second mask material pillar 226 may be selectively removed with respect to the vertical semiconductor channel 60 and the memory film 50. For example, the second mask material pillar 226 may be removed by ashing.

Referring to fig. 42A-42C, a dielectric material such as undoped silicate glass or doped silicate glass may be deposited in the remaining volume of the line trench 49. Excess portions of the dielectric material above the horizontal plane including the insulating cap layer 70 may be removed by a planarization process, such as recess etching or chemical mechanical planarization. Each remaining portion of the dielectric material constitutes a dielectric core 62. In one embodiment, each dielectric core 62 contacts two rows of vertical semiconductor channels 60 and two tunneling dielectric layers 56.

In one embodiment, the dielectric core 62 may be formed in the unfilled volume of the line trench 49 after forming the material stack strip. Dielectric core 62 may be formed on physically exposed sidewall surfaces of the insulating strips 32 and sacrificial material strips 42 that lie outside the two-dimensional array of lateral recesses. Dielectric core 62 contacts blocking dielectric layer 52, charge storage material layer 54L, tunneling dielectric layer 56, and the subsurface of vertical semiconductor channel 60. As used herein, the minor surface of an element refers to a surface that comprises less than 25% of the entire surface area of the element. By contrast, a major surface of an element is meant to include a surface that is more than 25% of the entire surface area of the element. Dielectric core 62 contacts a major surface of each vertical semiconductor channel 60 and does not contact major surfaces of blocking dielectric layer 52, charge storage material layer 54L, and tunneling dielectric layer 56. A major surface of each barrier dielectric layer 52 contacts a respective one of the alternating stacks (32,42) of insulating strips 32 and sacrificial material strips 42.

Referring to fig. 43A-43D, 44A, and 44B, the upper end of each dielectric core 62 may be vertically recessed, for example, by applying and patterning a photoresist layer over the first exemplary structure to form an opening overlying the dielectric core 62 and by performing an etching process, which may be an anisotropic etching process or an isotropic etching process. The photoresist layer may be removed and a doped semiconductor material having a doping of the second conductivity type may be deposited in the recess to form the drain region 63. The second conductive type may be opposite to the first conductive type, and the atomic concentration of the dopant of the second conductive type in the drain region 63 may be 5.0 × 10¹⁹/cm³To 2.0X 10²¹/cm³But smaller and larger atomic concentrations may also be used.

Referring to fig. 45A and 45B, a backside via cavity 79 may be formed through the isolation regions of the dielectric core 62 such that the remaining material portion within each line trench 49 includes at least one memory stack assembly 509. Each memory stack component 509 includes two rows of vertical semiconductor channels 60 connected to one row of drain regions 63. The locations of the backside via cavities 79 can be selected such that each sacrificial material strip 42 contacts at least one of the backside via cavities 79. Additionally, the location of the backside via cavities 79 may be selected such that each point within the sacrificial material strip 42 is laterally spaced from a nearest one of the backside via cavities 79 by a lateral distance that does not exceed a lateral etch distance during a subsequent isotropic etch process.

Memory stack components 509 are formed in each volume comprising a combination of the volume of the initially formed line trenches 49 and the volume of two contiguous two-dimensional arrays of lateral recesses formed over the sidewalls of sacrificial material strips 42. Each of memory stack components 509 includes two-dimensional arrays of lateral protruding regions 510, and each of lateral protruding regions 510 includes a respective charge storage element, i.e., discrete charge storage element 54. Each of the memory stack components 509 includes two rows of vertical semiconductor channels 60.

Referring to fig. 46, an etchant may be introduced into the backside via cavities 79, for example using an isotropic etching process, which etches the material of the sacrificial material strips 42 selectively to the material of the insulating strips 32, the barrier dielectric layer 52, and the dielectric core 62. A backside recess 43 is formed in the volume from which the sacrificial material strips 42 are removed. In one embodiment, the sacrificial material strips 42 may comprise silicon nitride and the material of the insulating strips 32 may comprise silicon oxide. In this case, the isotropic etching process may include a wet etching process using hot phosphoric acid.

The duration of the isotropic etching process may be selected such that the sacrificial material strips 42 are completely removed from each alternating stack (32,42) of insulating strips 32 and sacrificial material strips 42. Each backside recess 43 may be a laterally extending cavity having a lateral dimension greater than a vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 may be greater than the height of the backside recess 43.

In one implementation, the memory array region 100 includes a monolithic three dimensional array of NAND strings having a plurality of device levels disposed above a substrate (9, 10). In this case, each backside recess 43 may define a space for receiving a respective word line of the monolithic three-dimensional NAND string array. Each backside recess of the plurality of backside recesses 43 may extend substantially parallel to a top surface of the substrate (9, 10). Backside recesses 43 may be vertically bounded by a top surface of an underlying insulative strip 32 and a bottom surface of an overlying insulative strip 32. In one embodiment, each of the backside recesses 43 may have a uniform height throughout. Memory stack component 509 provides structural support for the first exemplary structure during formation of backside recess 43.

Referring to fig. 47 and 48A-48C, a backside blocking dielectric layer (not shown) may optionally be formed in the backside recesses 43 by a conformal deposition process. For example, the backside blocking dielectric layer may comprise a dielectric metal oxide (such as aluminum oxide). The conformal deposition process may include, for example, an Atomic Layer Deposition (ALD) process. The thickness of the backside blocking dielectric layer may be in the range of 1nm to 6nm, but smaller and larger thicknesses may also be used.

At least one conductive material may be deposited in the remaining volume of the backside recess 43. For example, without the use of a backside blocking dielectric layer, the metallic barrier layer may be deposited directly on the physically exposed surfaces of the backside blocking dielectric layer in the backside recesses 43, or on the physically exposed surfaces of the blocking dielectric 52 and the insulating stripes 32. The metal barrier layer comprises a conductive metallic material that can act as a diffusion barrier and/or adhesion promoting layer for subsequently deposited metallic filler materials. The metallic barrier layer may comprise a conductive metal nitride material such as TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer may be deposited by a conformal deposition process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The thickness of the metallic barrier layer may be in the range of 2nm to 8nm, such as 3nm to 6nm, although lesser and greater thicknesses may also be used. In one embodiment, the metallic barrier layer may consist essentially of a conductive metal nitride such as TiN.

A metallic fill material is deposited in the remaining volume of the backside recess 43 on the sidewalls of the at least one backside via cavity 79 and over the insulating cap layer 70. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic filler material may consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material may be selected from, for example, tungsten, cobalt, ruthenium, molybdenum, titanium, and tantalum. In one embodiment, the metallic filler material may consist essentially of a single elemental metal. In one embodiment, the metallic filler material may use a fluorine-containing precursor gas such as WF₆And (6) carrying out deposition. In one embodiment, the metallic fill material may comprise tungsten including a residual level of boron, fluorine, or silicon atoms as impurities.

A plurality of conductive strips 46 (i.e., conductive strips having a strip shape) may be formed in the plurality of backside recesses 43, and a continuous layer of metallic material may be formed on the sidewalls of each backside via cavity 79 and over the insulating cap layer 70. Each conductive strip 46 includes a portion of a metal barrier layer and a metallic filler material located between vertically adjacent pairs of insulating strips 32.

The deposited metallic material of the continuous layer of conductive material is etched back from the sidewalls of each backside via cavity 79 and from above the insulating cap layer 70, such as by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses 43 constitutes a conductive strip 46. Each conductive strip 46 may be a conductive line structure. Thus, the sacrificial material strips 42 are replaced with conductive strips 46.

Each conductive strip 46 may function as a combination of a plurality of control gate electrodes at the same level and a word line electrically interconnected (i.e., electrically shorted) with the plurality of control gate electrodes at the same level. The plurality of control gate electrodes within each conductive stripe 46 are the control gate electrodes for the NAND strings in the line trenches 49. In other words, each conductive stripe 46 may be a word line that serves as a common control gate electrode for the plurality of vertical memory devices. Each vertical semiconductor channel 60 has a laterally undulating vertical cross-sectional profile and includes a vertical stack of lateral bump portions at the level of the conductive strip 46 within the lateral recess, into the concave surface of the conductive strip 46.

Referring to fig. 49A and 49B, a dielectric material, such as silicon oxide, is anisotropically deposited within the backside via cavity 79. Anisotropic deposition of dielectric materials may be performed by Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the dielectric material is directionally deposited. Excess portions of the deposited dielectric material may be removed from above a horizontal plane including the top surface of the backward stepped dielectric material portion 65. Each portion of the dielectric material deposited in the backside via cavity 79 forms a dielectric pillar 176. Alternatively, the dielectric posts 176 may be air gap posts including corresponding voids therein. The curvature of the elements shown in the aforementioned close-up figures is not shown in fig. 49B, as fig. 49B is an expanded top view in which the curvature is not visible in scale of the figure.

Referring to all of the drawings associated with the second embodiment, there is provided a three-dimensional memory device comprising: alternating stacks of conductive stripes 46 and insulating stripes 32 over substrates (9,10) and laterally spaced from each other by memory stack components 509, wherein the memory stack components 509 extend laterally along a first horizontal direction hd1 and are spaced from each other along a second horizontal direction hd2, wherein: each of memory stack components 509 includes two-dimensional arrays of lateral protruding regions 510; each of the two-dimensional arrays of lateral protruding regions 510 comprises a respective two-dimensional array of lateral protruding regions 510 that protrude laterally outward from a respective vertical plane that includes an interface between memory stack component 509 and the subset of insulating strips 32; and each of the lateral protruding regions 510 includes a respective charge storage element having a pair of concave inner side wall segments having a respective horizontal concave profile in horizontal cross-section and a pair of convex outer side wall segments having a respective horizontal convex profile in horizontal cross-section.

In one embodiment, the pair of concave inner side wall sections are connected to each other by a straight inner side wall section, and the pair of convex outer side wall sections are connected to each other by a straight outer side wall section.

In one embodiment, each of the memory stack components 509 includes two rows of charge storage material layers extending over a sidewall of a respective one of the alternating stacks (32, 42); and each of the charge storage material layers 54L includes a respective vertical stack of charge storage elements that is a portion of the respective charge storage material layer 54L that is located within a respective one of the two-dimensional array of lateral protruding regions 510.

In one embodiment, each of the memory stack components 509 includes two rows of vertical semiconductor channels 60; and each vertical semiconductor channel within the two rows of vertical semiconductor channels 60 laterally overlies a respective vertical stack of charge storage elements. In one embodiment, each of memory stack components 509 includes two tunneling dielectric layers 56; and each of the two tunnel dielectric layers 56 contacts a respective row of vertical semiconductor channels 60.

In one embodiment, each of the memory stack assemblies 509 includes a dielectric core 62 extending laterally along the first horizontal direction hd1 and contacting inner sidewalls of each vertical semiconductor channel 60 within the two rows of vertical semiconductor channels 60 of the respective memory stack assembly 509.

In one embodiment, the vertical semiconductor channels 60 within each row of vertical semiconductor channels 60 are laterally spaced along the first horizontal direction hd1 by a vertically extending region in which the dielectric core 62 contacts one of the alternating stacks of insulating strips 32.

In one embodiment, each charge storage material layer 54L within two rows of charge storage material layers 54L has: contacts the first major surface of the respective vertical semiconductor channel 60; contacting the second major surface of the respective barrier dielectric layer 52; and a pair of minor surfaces contacting the dielectric core 62. In one embodiment, the dielectric core 62 contacts both rows of vertical semiconductor channels 60 of the respective memory stack components 509.

In one embodiment, each of the memory stack components 509 includes two rows of material stack strips extending vertically and laterally overlying sidewalls of a respective one of the alternating stacks (32, 46); and each of the two rows of material stack strips comprises: a barrier dielectric layer 52 contacting the insulating strips 32 within a respective one of the alternating stacks (32, 46); a charge storage material layer 54L or floating gate contacting the blocking dielectric layer 52; a tunneling dielectric layer 56 contacting the charge storage material layer 54L or the floating gate; and a vertical semiconductor channel 60 contacting the tunnel dielectric layer 56.

In one embodiment, each of the blocking dielectric layer 52, the charge storage material layer 54L, the tunneling dielectric layer 56, and the vertical semiconductor channel 60 contacts the dielectric core 62. In one implementation, each of the blocking dielectric layer 52, the charge storage material layer 54L, the tunneling dielectric layer 56, and the vertical semiconductor channel 60 has a laterally undulating vertical cross-sectional profile such that sidewalls of the blocking dielectric layer 52, the charge storage material layer 54L, the tunneling dielectric layer 56, and the vertical semiconductor channel 60 comprise vertical straight segments at levels of the alternating stacked (32,46) insulating strips 32 and curved laterally protruding segments at levels of the alternating stacked (32,46) conductive strips 46.

The laterally recessed regions having curvature provide a geometry of increased local electric field strength. The curvature in the memory film 50 enhances electric field concentration during programming and erasing, thereby reducing the operating voltage of the three-dimensional memory device. The three-dimensional memory devices of various embodiments can provide lower programming voltages and lower erase voltages through a localized increase in electric field line density and, thus, through an increased local electric field strength. Power consumption of the three-dimensional memory device can be reduced by using low voltage programming. Various embodiments are disclosed that provide laterally recessed regions having curvature in multiple planes, such as the xy plane and the zx plane. By providing laterally recessed regions with curvature in multiple planes, the resulting structure may enhance control gate performance and provide improved channel corner effects. In addition, the stack of layers can be minimized to reduce production costs.

While the foregoing refers to certain preferred embodiments, it is to be understood that the disclosure is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the word "comprising" or "includes" contemplates all embodiments in which the word "consisting essentially of …" or the word "consisting of …" replaces the word "comprising" or "includes". Embodiments using specific structures and/or configurations are shown in the present disclosure, it being understood that the present disclosure may be practiced in any other compatible structures and/or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered to be impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising:

an alternating stack of conductive and air-gap strips over a substrate and laterally spaced from each other by a memory stack assembly, wherein the memory stack assembly extends laterally in a first horizontal direction and is spaced from each other in a second horizontal direction, wherein:

each of the memory stack components comprises two-dimensional arrays of lateral protrusion areas;

the lateral protruding regions protrude laterally outward from respective vertical planes that include interfaces between the memory stack components and the subset of air gap strips;

each of the lateral protruding regions comprises a respective curved charge storage element;

each of the memory stack assemblies includes two rows of vertical semiconductor channels; and is

Each vertical semiconductor channel within the two rows of vertical semiconductor channels laterally overlies a respective vertical stack of charge storage elements.

2. The three-dimensional memory device of claim 1, wherein:

each of the memory stack components includes two tunneling dielectric layers; and is

Each of the two tunneling dielectric layers contacts a respective row of vertical semiconductor channels selected from the two rows of vertical semiconductor channels.

3. The three-dimensional memory device of claim 2, wherein each of the memory stack assemblies includes a dielectric core extending laterally along the first horizontal direction and contacting an inner sidewall of each vertical semiconductor channel within the two rows of vertical semiconductor channels.

4. The three-dimensional memory device of claim 3, wherein the vertical semiconductor channels within each row of vertical semiconductor channels are laterally spaced along the first horizontal direction by a vertically extending region in which the dielectric core contacts one of the two tunneling dielectric layers.

5. The two-dimensional memory device of claim 2, wherein each of the two tunneling dielectric layers contacts the two-dimensional array of charge storage elements located in the two-dimensional array of laterally protruding regions.

6. The two-dimensional memory device of claim 2, wherein each vertical semiconductor channel within the two rows of vertical semiconductor channels comprises a vertical stack of lateral bump portions at a level of the conductive strip.

7. The three-dimensional memory device of claim 2, wherein:

each of the memory stack components comprises two blocking dielectric layers; and is

Each of the two blocking dielectric layers contacts a respective one of the two tunneling dielectric layers at each level of the air-gap strip and between each adjacent pair of vertical stacks of charge storage elements.

8. The three-dimensional memory device of claim 7, wherein:

each of the conductive strips including a respective metal barrier layer and a respective portion of a metallic filler material formed within the respective metal barrier layer; and is

Each of the two barrier dielectric layers contacts a sidewall of a subset of the metallic barrier layers.

9. The three-dimensional memory device of claim 1, wherein the charge storage elements comprise discrete floating gate or dielectric charge trapping material portions that are not in direct contact with each other.

10. The three-dimensional memory device of claim 9, wherein each of the charge storage elements comprises:

a concave interior sidewall having a horizontal concave profile in a horizontal cross-section; and

a convex outer sidewall having a horizontal convex profile in the horizontal cross-section.

11. The three-dimensional memory device of claim 9, wherein:

in a vertical cross-sectional view, the concave inner side walls have vertical concave profiles at upper and lower edge regions of the respective charge storage elements; and is

In the vertical cross-sectional view, the convex outer sidewall has a vertical convex contour at the upper edge region and at the lower edge region of the respective charge storage element.

12. The three-dimensional memory device of claim 9, wherein each of the charge storage elements is located between a first horizontal plane and a second horizontal plane, the first horizontal plane including a top surface of a respective one of the conductive strips, the second horizontal plane including a bottom surface of the respective one of the conductive strips.

13. A method of forming a three-dimensional memory device, comprising:

forming an alternating stack of strips of a first sacrificial material and strips of a second sacrificial material over a substrate, wherein the alternating stack is laterally spaced from each other by line trenches extending laterally in a first horizontal direction;

modifying the line trench to provide a two-dimensional array of lateral recesses on each sidewall of the line trench, wherein each two-dimensional array of lateral recesses is laterally bounded by a respective two-dimensional array of lateral recess surfaces of the second strip of sacrificial material;

forming a memory stack assembly in each volume, the each volume comprising a combination of a volume of wire trenches and a volume of two contiguous two-dimensional arrays of lateral recesses, wherein each of the memory stack assemblies comprises two-dimensional arrays of lateral protruding regions, and each of the lateral protruding regions comprises a respective charge storage element;

replacing a remaining portion of the second strip of sacrificial material with a conductive strip; and

an air gap strip is formed by removing the first strip of sacrificial material.

14. The method of claim 13, further comprising:

forming a diffusion barrier strip extending vertically and laterally spaced apart from each other on each sidewall of the line trench;

oxidizing a surface portion of the second strip of sacrificial material at a faster oxidation rate than a surface portion of the first strip of sacrificial material; and

removing the diffusion barrier strips, the oxidized portions of the second sacrificial material strips, and the oxidized portions of the first sacrificial material strips, wherein a two-dimensional array of the laterally recessed surfaces of the second sacrificial material strips is provided.

15. The method of claim 14, wherein:

the diffusion barrier strips comprise silicon nitride;

the first strip of sacrificial material comprises silicon; and is

The second strip of sacrificial material comprises a silicon-germanium alloy comprising a higher atomic concentration of germanium than the first strip of sacrificial material.

16. The method of claim 15, further comprising:

forming a diffusion barrier layer on each sidewall of the line trench;

forming a two-dimensional array of posts of mask material within the line trenches after forming the diffusion barrier layer; and

isotropically etching the physically exposed portions of the diffusion barrier layer not masked by the two-dimensional array of posts of mask material, wherein remaining portions of the diffusion barrier layer constitute the diffusion barrier strips.

17. The method of claim 13, further comprising:

depositing a layer of charge storage material over the remaining portions of the alternating strips after forming the two-dimensional array of lateral recesses; and

removing portions of the layer of charge storage material outside of the two-dimensional array of lateral recesses using an anisotropic etching process, wherein remaining portions of the layer of charge storage material in the two-dimensional array of lateral recesses constitute the charge storage elements.

18. The method of claim 17, further comprising:

forming a tunneling dielectric layer over each set of charge storage elements located within a respective two-dimensional array of lateral recesses; and

a row of vertical semiconductor channels is formed over each tunneling dielectric layer.

19. The method of claim 18, wherein:

20. The method of claim 19, further comprising forming a dielectric core in each remaining volume of the line trench after forming the vertical semiconductor channels, wherein each dielectric core contacts two rows of vertical semiconductor channels and two tunneling dielectric layers.

21. A three-dimensional memory device, comprising:

an alternating stack of conductive and insulative strips over a substrate and laterally spaced from each other by memory stack components, wherein the memory stack components extend laterally in a first horizontal direction and are spaced from each other in a second horizontal direction, wherein:

each laterally protruding region protrudes laterally outward from a respective vertical plane that includes an interface between a respective one of the memory stack assemblies and an insulating strip within a respective one of the alternating stacks; and is

Each of the lateral protruding regions includes a respective charge storage element having a pair of concave inner side wall segments having respective horizontal concave profiles in horizontal cross-section and a pair of convex outer side wall segments having respective horizontal convex profiles in horizontal cross-section.

22. The three-dimensional memory device of claim 21, wherein:

the pair of concave inner side wall sections are connected to each other by a straight inner side wall section; and is

The pair of convex outer side wall sections are connected to each other by a straight outer side wall section.

23. The three-dimensional memory device of claim 21, wherein:

each of the memory stack assemblies includes two rows of charge storage material layers extending over a sidewall of a respective one of the alternating stacks; and is

Each of the layers of charge storage material includes a respective vertical stack of charge storage elements that is a portion of the respective layer of charge storage material that is located within a respective one of the two-dimensional arrays of lateral raised regions.

24. The three-dimensional memory device of claim 23, wherein:

25. The three-dimensional memory device of claim 24, wherein:

Each of the two tunneling dielectric layers contacts a respective row of vertical semiconductor channels.

26. The three-dimensional memory device of claim 24, wherein each of the memory stack assemblies includes a dielectric core extending laterally along the first horizontal direction and contacting an inner sidewall of each vertical semiconductor channel within the two rows of vertical semiconductor channels of the respective memory stack assembly.

27. The three-dimensional memory device of claim 24, wherein vertical semiconductor channels within each row of vertical semiconductor channels are laterally spaced along the first horizontal direction by vertically extending regions in which a dielectric core contacts one of the alternating stacks of insulating strips.

28. The three-dimensional memory device of claim 23, wherein each charge storage material layer within the two rows of charge storage material layers has:

a first major surface contacting a respective vertical semiconductor channel;

a second major surface contacting a respective barrier dielectric layer; and

a pair of minor surfaces contacting the dielectric core.

29. The three-dimensional memory device of claim 28, wherein the dielectric core contacts two rows of vertical semiconductor channels of a respective memory stack assembly.

30. The three-dimensional memory device of claim 21, wherein:

each of the memory stack assemblies comprises two rows of material stack strips extending vertically and laterally overlying a sidewall of a respective one of the alternating stacks; and is

Each material stack strip of the two rows of material stack strips comprises:

a blocking dielectric layer contacting the insulating strips within the respective one of the alternating stacks;

a layer of charge storage material or a floating gate, the layer of charge storage material or the floating gate contacting the blocking dielectric layer;

a tunneling dielectric layer contacting the layer of charge storage material; and

a vertical semiconductor channel contacting the tunneling dielectric layer.

31. The three-dimensional memory device of claim 30, wherein each of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer, and the vertical semiconductor channel contacts a dielectric core.

32. The three-dimensional memory device of claim 31, wherein each of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer, and the vertical semiconductor channel has a laterally undulating vertical cross-sectional profile such that sidewalls of the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer, and the vertical semiconductor channel comprise vertical straight segments at levels of the alternating stack of the insulating strips and curved laterally protruding segments at levels of the alternating stack of the conductive strips.

33. A method of forming a three-dimensional memory device, comprising:

forming alternating stacks of insulating strips and sacrificial material strips over a substrate, wherein the alternating stacks are laterally spaced from each other by line trenches extending laterally in a first horizontal direction;

modifying the line trench to provide a two-dimensional array of lateral recesses on each sidewall of the line trench, wherein each two-dimensional array of lateral recesses is laterally bounded by a respective two-dimensional array of lateral recess surfaces of the strip of sacrificial material;

forming a memory stack assembly in each volume, the each volume comprising a combination of a volume of wire trenches and a volume of two contiguous two-dimensional arrays of lateral recesses, wherein each of the memory stack assemblies comprises two rows of material stack strips extending vertically and laterally overlying a sidewall of a respective one of the alternating stacks, and each row of material stack strips comprises a respective plurality of material stack strips laterally spaced along a first horizontal direction, and each of the material stack strips comprises a respective layer of charge storage material comprising charge storage elements within each respective vertical stack of lateral recesses selected from the two-dimensional arrays of lateral recesses; and

replacing the sacrificial material layer with a conductive strip.

34. The method of claim 33, wherein each of the material stack strips comprises:

a layer of charge storage material contacting the blocking dielectric layer and comprising a vertical stack of charge storage elements;

a vertical semiconductor channel contacting the tunneling dielectric layer.

35. The method of claim 34, further comprising forming dielectric cells in an unfilled volume of the line trench after forming the material stack strip, wherein each of the reservoir stack assemblies includes a respective one of the dielectric cells.

36. The method of claim 35, wherein the dielectric core is formed on physically exposed sidewall surfaces of the insulating strips and the sacrificial material strips that lie outside the two-dimensional array of lateral recesses, wherein the dielectric core contacts the blocking dielectric layer, the charge storage material layer, the tunneling dielectric layer, and a minor surface of the vertical semiconductor channel.

37. The method of claim 34, further comprising:

after forming the two-dimensional array of lateral recesses, forming a continuous layer stack of a blocking dielectric layer, a charge storage material layer, and a tunneling dielectric layer over the physically exposed surfaces of the alternating stack; and

anisotropically etching the continuous layer stack, wherein a semiconductor surface of the substrate is physically exposed at a bottom of each of the line trenches.

38. The method of claim 37, further comprising:

forming a layer of semiconductor channel material over remaining vertical portions of the continuous layer stack after anisotropically etching the continuous layer stack;

forming a two-dimensional array of pillars of mask material within unfilled volumes of the line trenches after forming the layer of semiconductor channel material; and

isotropically etching portions of the continuous layer stack that are not masked by the columns of masking material, wherein remaining portions of the continuous layer stack and the semiconductor channel material layer constitute the strips of material stack.

39. The method of claim 33, further comprising:

forming a two-dimensional array of pillars of mask material in the line trenches; and

the sacrificial material strips are selectively laterally recessed with respect to the insulating strips when the two-dimensional array of mask material pillars in the line trenches is present within the line trenches, wherein the two-dimensional array of lateral recesses is formed.

40. The method of claim 33, further comprising:

forming a backside via cavity after forming the memory stack component such that sidewalls of the insulating strips and the sacrificial material strips are physically exposed to the backside via cavity;

forming a backside recess by selectively removing the sacrificial material strip for the insulating strip; and

depositing at least one conductive material in the backside recesses to form the conductive strips.