CN113169181B

CN113169181B - Three-dimensional memory device with laterally confined dielectric core or carbon doped source contact layer and method of fabricating the same

Info

Publication number: CN113169181B
Application number: CN201980079428.0A
Authority: CN
Inventors: 嘉数学; 汤田隆; 深野勇二; 津美正典; R·S·马卡拉; S·卡纳卡梅达拉; 神原清彦; 东谷正明; 崔志欣
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2019-02-05
Filing date: 2019-11-25
Publication date: 2024-03-19
Anticipated expiration: 2039-11-25
Also published as: CN113169181A; WO2020163005A1

Abstract

A three-dimensional memory device may include a vertical semiconductor channel surrounding a vertical dielectric core. A laterally extending dielectric plug structurally supports the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystal semiconductor channel. The three-dimensional memory device can include a source level material layer positioned over the substrate. The source level material layer may include a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. Carbon atoms in the upper semiconductor layer and optionally the lower semiconductor layer may inhibit boron atoms from diffusing into the vertical semiconductor channel.

Description

Three-dimensional memory device with laterally confined dielectric core or carbon doped source contact layer and method of fabricating the same

RELATED APPLICATIONS

The present application claims priority from U.S. non-provisional application Ser. Nos. 16/268,132 and 16/268,183, filed on 5 months of 2019, and U.S. non-provisional application Ser. No. 16/408,722, filed on 5 months of 2019, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and in particular, to three-dimensional memory devices including carbon-doped source contact layers and methods of fabricating the same.

Background

A three-dimensional semiconductor device comprising a three-dimensional vertical NAND string having one bit per Cell is disclosed in the article by t.endoh et al entitled "novel ultra-high density memory (Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell) with stacked surrounding gate transistor (S-SGT) Structured cells," IEDM proc. (2001) 33-36.

Disclosure of Invention

According to one aspect of the present disclosure, there is provided a three-dimensional memory device including: a source-level material layer positioned over the substrate and comprising a lower semiconductor layer, a source contact layer, and an upper semiconductor layer, wherein the lower semiconductor layer comprises a first boron-doped semiconductor material, the upper semiconductor layer comprises a carbon-doped second boron-doped semiconductor material, and the source contact layer comprises a third boron-doped semiconductor material; an alternating stack of insulating layers and conductive layers, the alternating stack positioned over the source-level material layer; and memory stack structures extending vertically through the alternating stacks, the higher semiconductor layers, and the source contact layers, wherein each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel contacting the source contact layer.

According to one aspect of the present disclosure, there is provided a three-dimensional memory device including: a source-level material layer positioned over a substrate and comprising a lower semiconductor layer, a source contact layer, and an upper semiconductor layer, wherein the substrate comprises a single-crystalline semiconductor material, and the lower semiconductor layer comprises a first boron-doped semiconductor material comprising a doped single-crystalline semiconductor material that is epitaxially aligned with the single-crystalline semiconductor material of the substrate; an alternating stack of insulating layers and conductive layers, the alternating stack positioned over the source-level material layer; and memory stack structures extending vertically through the alternating stacks, the higher semiconductor layers, and the source contact layers, wherein each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel contacting the source contact layer.

According to another embodiment of the present disclosure, there is provided a method of forming a semiconductor structure, the method comprising: forming a lower semiconductor layer comprising a first boron doped semiconductor material over a substrate; forming a sacrificial source level material layer over the lower semiconductor layer; forming a higher semiconductor layer comprising a carbon doped second boron doped semiconductor material over the sacrificial source level material layer; forming an alternating stack of insulating layers and spacer material layers over the higher semiconductor layer, wherein the spacer material layers are formed as conductive layers or are subsequently replaced by the conductive layers; forming memory stack structures through the alternating stacks, the upper semiconductor layers, and the source contact layers and into the lower semiconductor layers, wherein each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel contacting the source contact layer; and replacing the sacrificial source-level material layer with a source contact layer comprising a third boron-doped semiconductor material.

According to one aspect of the present disclosure, a three-dimensional memory device includes: a first alternating stack of first insulating layers and first conductive layers, the first alternating stack positioned over the substrate; a second alternating stack of second insulating layers and second conductive layers, the second alternating stack positioned above and spaced apart from the first alternating stack; a memory opening extending vertically through the first alternating stack and the second alternating stack, wherein each of the memory openings includes one or more side apertures positioned between the first alternating stack and the second alternating stack; and a memory opening fill structure positioned in a respective one of the memory openings and including a memory film, a semiconductor channel, and a dielectric core including a dielectric fill material, wherein the dielectric core includes a dielectric pillar portion and one or more dielectric plug portions extending laterally from the dielectric pillar portion through one or more holes in the semiconductor channel and abutting respective side apertures.

According to another aspect of the present disclosure, there is provided a method of forming a three-dimensional memory device, the method comprising: forming a first alternating stack of first insulating layers and first sacrificial material layers positioned over the monocrystalline semiconductor material layers; forming a laterally alternating sequence of strips of insulating material and strips of sacrificial material over the first alternating stack; forming a second alternating stack of second insulating layers and second conductive layers over the laterally alternating sequence, wherein the first sacrificial material layers and the second material layers are subsequently replaced with conductive layers; forming a memory opening extending through the first alternating stack, the laterally alternating sequence, and the second alternating stack; forming a memory film and sacrificial conformal spacers within each memory opening; forming a network of cavities by removing the sacrificial material strips and the sacrificial conformal spacers; depositing a dielectric fill material in the network of cavities, wherein a dielectric core is formed in each memory opening and a dielectric stripe is formed in the volume of the sacrificial material stripe; forming a channel cavity in each memory opening by selectively removing the sacrificial conformal spacers for the dielectric core and the memory film; and forming an epitaxial semiconductor channel within each of the channel cavities, the epitaxial semiconductor channel being epitaxially aligned with the single crystal semiconductor material layer.

According to another aspect of the present disclosure, a three-dimensional memory device includes: a first layer of alternating stacks of first insulating layers and first conductive layers, the first layer of alternating stacks positioned over the substrate; an interlayer insulating assembly positioned above the first layer alternating stack and comprising a plurality of dielectric strips, wherein each of the plurality of dielectric strips comprises a dielectric plug portion protruding laterally from a dielectric rail portion; a second layer of alternating stacks of second insulating layers and second conductive layers, the second layer of alternating stacks positioned over the interlayer insulating assembly; a memory opening extending vertically through the first layer alternating stack, the interlayer insulating assembly, and the second layer alternating stack, wherein each of the memory openings includes a side aperture through which a respective one of the dielectric plug portions extends inwardly; and a memory opening fill structure positioned in a respective one of the memory openings and including a memory film, a semiconductor channel, and a dielectric core including a dielectric fill material and abutting the respective one of the dielectric plug portions.

According to another aspect of the present disclosure, there is provided a method of forming a three-dimensional memory device, the method comprising: first insulating layers and first sacrificial material layers formed over the single crystal semiconductor material layers are alternately stacked; forming a laterally alternating stack of strips of insulating material and strips of sacrificial material over the first layer alternating stack; forming a second layer alternating stack of second insulating layers and second sacrificial material layers positioned above the laterally alternating stack, wherein the first sacrificial material layers and the second sacrificial material layers are subsequently replaced with conductive layers; forming a memory opening through the first layer alternating stack, the lateral alternating stack, and the second layer alternating stack; and forming in each memory opening an in-process memory opening fill structure, wherein the in-process memory opening fill structure comprises a memory film, sacrificial conformal spacers, and a dielectric core; forming a laterally extending cavity by removing the strip of sacrificial material; removing portions of the memory film and the sacrificial conformal spacers adjacent to the laterally extending cavities; forming a dielectric strip in the laterally extending cavity and in the volume from which the memory film and the portion of the sacrificial conformal spacer are removed; and replacing the sacrificial conformal spacers with epitaxial semiconductor channels.

Drawings

Fig. 1A is a vertical cross-section of a first exemplary structure after forming a first alternating stack of first insulating layers and first sacrificial material layers and a first laterally alternating sequence of insulating material strips and sacrificial material strips according to a first embodiment of the present disclosure.

Fig. 1B is a top view of the first exemplary structure of fig. 1A.

Fig. 2 is a vertical cross-sectional view of a first exemplary structure after forming a second alternating stack of first insulating layers and first sacrificial material layers according to a first embodiment of the present disclosure.

Fig. 3 is a vertical cross-sectional view of a first exemplary structure after forming a first landing zone, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to a first embodiment of the present disclosure.

Fig. 4A is a vertical cross-section of a first exemplary structure after formation of a first layer of memory openings according to a first embodiment of the present disclosure.

Fig. 4B is a horizontal cross-sectional view of the first exemplary structure of fig. 4A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 4A.

Fig. 5 is a vertical cross-sectional view of a first exemplary structure after forming an epitaxial pedestal channel portion and a sacrificial semiconductor oxide plate according to a first embodiment of the present disclosure.

Fig. 6 is a vertical cross-section of a first exemplary structure after formation of various sacrificial fill structures in accordance with a first embodiment of the present disclosure.

Fig. 7 is a vertical cross-section of a first exemplary structure after forming a second layer of insulating material and two alternating stacks of second layers of sacrificial material layers with another laterally alternating sequence of strips of insulating material and strips of sacrificial material therebetween, a second layer of stepped surfaces, a second portion of rearwardly stepped dielectric material, and a second layer of insulating cap layer, according to a first embodiment of the present disclosure.

Fig. 8A is a vertical cross-section of a first exemplary structure after forming a second layer memory opening according to a first embodiment of the present disclosure.

Fig. 8B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 8A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 8A.

Fig. 9A is a horizontal cross-sectional view of a region of a first exemplary structure at a level of a laterally alternating sequence of strips of insulating material and strips of sacrificial material after formation of a memory opening in accordance with a first embodiment of the present disclosure.

Fig. 9B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 9A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 9A.

Fig. 9C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 9A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 9A.

Fig. 9D is a vertical cross-sectional view of the first exemplary structure at a processing step of fig. 9A-9C.

Fig. 10A is a horizontal cross-sectional view of a region of a first exemplary structure at a level of a laterally alternating sequence of strips of insulating material and strips of sacrificial material after formation of a continuous memory film stack and a continuous sacrificial spacer layer in accordance with a first embodiment of the present disclosure.

Fig. 10B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 10A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 10A.

Fig. 10C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 10A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 10A.

Fig. 10D is a vertical cross-sectional view of the first exemplary structure at a processing step of fig. 10A-10C.

Fig. 11A is a horizontal cross-sectional view of a region of a first exemplary structure at a level of a laterally alternating sequence of strips of insulating material and strips of sacrificial material after formation of a memory film and sacrificial conformal spacers according to a first embodiment of the present disclosure.

Fig. 11B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 11A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 11A.

Fig. 11C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 11A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 11A.

Fig. 11D is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure at a processing step of fig. 11A-11C.

Fig. 12A is a vertical cross-sectional view of a first exemplary structure after covering a memory opening with a sacrificial cover material and forming a support opening according to a first embodiment of the present disclosure.

Fig. 12B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 12A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 12A.

Fig. 12C is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure at a processing step of fig. 12A and 12B.

Fig. 13A is a vertical cross-section of a first exemplary structure after forming laterally extending cavities by selectively removing strips of sacrificial material according to a first embodiment of the present disclosure.

Fig. 13B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 13A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 13A.

Fig. 13C is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure at a processing step of fig. 13A and 13B.

Fig. 14A is a horizontal cross-sectional view of a region of a first exemplary structure at the level of the laterally alternating sequence of laterally extending cavities and strips of insulating material at the processing steps of fig. 13A-13C, according to a first embodiment of the present disclosure.

Fig. 14B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 14A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 14A.

Fig. 14C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 14A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 14A.

Fig. 15A is a horizontal cross-sectional view of a region of a first exemplary structure at a level of a laterally alternating sequence of laterally extending cavities and strips of insulating material after forming a network of cavities by removing portions of the memory film and sacrificial conformal spacers positioned adjacent to the laterally extending cavities in accordance with a first embodiment of the present disclosure.

Fig. 15B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 15A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 15A.

Fig. 15C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 15A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 15A.

Fig. 16A is a horizontal cross-sectional view of a region of a first exemplary structure at the level of a laterally alternating sequence of strips of insulating material and laterally extending cavities after removal of sacrificial cover material and removal of a bottom portion of each memory film, in accordance with a first embodiment of the present disclosure.

Fig. 16B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 16A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 16A.

Fig. 16C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 16A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 16A.

Fig. 17A is a horizontal cross-sectional view of a region of a first exemplary structure at a level of a laterally alternating sequence of dielectric strips of dielectric fill material and strips of insulating material after deposition of the dielectric fill material in a laterally extending cavity and a memory cavity within a memory opening, according to a first embodiment of the present disclosure.

Fig. 17B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 17A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 17A.

Fig. 17C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 17A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 17A.

Fig. 17D is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure at a processing step of fig. 17A-17C.

Fig. 18A is a horizontal cross-sectional view of a region of a first exemplary structure at a level of a laterally alternating sequence of strips of insulating material and strips of dielectric fill material after forming a channel cavity in accordance with a first embodiment of the present disclosure.

Fig. 18B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 18A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 18A.

Fig. 18C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 18A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 18A.

Fig. 18D is a vertical cross-sectional view of the horizontal plane D-D' of fig. 18B and 18C.

Fig. 18E is a vertical cross-sectional view of the first exemplary structure at a processing step of fig. 18A-18D.

Fig. 19A is a horizontal cross-sectional view of a region of a first exemplary structure at the level of a laterally alternating sequence of dielectric strips of dielectric fill material and strips of insulating material after forming epitaxial semiconductor channel and drain regions in accordance with a first embodiment of the present disclosure.

Fig. 19B is a vertical cross-sectional view taken along the vertical plane B-B' of fig. 19A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 19A.

Fig. 19C is a vertical cross-sectional view taken along the vertical plane C-C' of fig. 19A. The horizontal cross-sectional plane A-A' is the plane of the horizontal cross-sectional view of fig. 19A.

Fig. 19D is a vertical cross-sectional view of the horizontal plane D-D' of fig. 19B and 19C.

Fig. 19E is a vertical cross-sectional view of the first exemplary structure at the processing step of fig. 19A-19D.

Fig. 20A is a vertical cross-sectional view of a first exemplary structure after forming a first contact level dielectric layer and a backside trench in accordance with a first embodiment of the present disclosure.

Fig. 20B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 20A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 20A.

Fig. 21 is a vertical cross-sectional view of a first exemplary structure after formation of a backside recess according to a first embodiment of the present disclosure.

Fig. 22A is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer and a backside trench fill structure in accordance with a first embodiment of the present disclosure.

Fig. 22B is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 22A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 22A.

Fig. 22C is a horizontal cross-sectional view of the first exemplary structure taken along horizontal plane B-B' of fig. 22A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 22A.

Fig. 23 is a vertical cross-sectional view of a first exemplary structure after forming a second contact level dielectric layer, various contact via structures, through memory level via structures, and metal line structures in accordance with a first embodiment of the present disclosure.

Fig. 24 is a vertical cross-sectional view of a second exemplary structure after forming a semiconductor device, source level sacrificial layers, and first layers of first insulating layers and first sacrificial material layers alternately stacked, according to a second embodiment of the present disclosure.

Fig. 25 is a vertical cross-sectional view of a second exemplary structure after forming a first landing zone, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to a second embodiment of the present disclosure.

Fig. 26A is a vertical cross-sectional view of a second exemplary structure after forming a first layer of memory openings and a first layer of support openings according to a second embodiment of the present disclosure.

Fig. 26B is a top view of the second exemplary structure of fig. 26A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 26A.

Fig. 27A is a vertical cross-sectional view of a second exemplary structure after forming a sacrificial first layer memory opening filling portion and a sacrificial first layer support opening filling portion in accordance with a second embodiment of the present disclosure.

Fig. 27B is a top view of the second exemplary structure of fig. 27A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 27A.

Fig. 28A is a vertical cross-section of a second exemplary structure after forming a one-dimensional array of line trenches, in accordance with a second embodiment of the present disclosure.

Fig. 28B is a top view of the second exemplary structure of fig. 28A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 28A.

Fig. 29A is a vertical cross-section of a second exemplary structure after forming a strip of sacrificial material according to a second embodiment of the present disclosure.

Fig. 29B is a top view of the second exemplary structure of fig. 28A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 28A.

Fig. 30 is a vertical cross-section of a second exemplary structure after forming a second layer alternating stack of second insulating layers and second sacrificial material layers, second stepped surfaces, and second backward stepped dielectric material portions according to a second embodiment of the present disclosure.

Fig. 31A is a vertical cross-sectional view of a second exemplary structure after forming a second tier memory opening and a second tier support opening in accordance with a second embodiment of the present disclosure.

Fig. 31B is a horizontal cross-sectional view of the second exemplary structure taken along horizontal plane B-B' of fig. 31A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 31A.

Fig. 32 is a vertical cross-sectional view of a second exemplary structure after forming an interlayer memory opening and an interlayer support opening according to a second embodiment of the present disclosure.

Fig. 33A-33D illustrate sequential vertical cross-sectional views of a memory opening during formation of an in-process memory opening fill structure according to a second embodiment of the present disclosure.

Fig. 34 is a vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure and a support pillar structure according to a second embodiment of the present disclosure.

Fig. 35A is a horizontal cross-sectional view of a region of a second exemplary structure including a backside trench and an in-process memory opening fill structure along a horizontal plane including a strip of insulating material after formation of the backside trench, in accordance with a second embodiment of the present disclosure.

Fig. 35B is a vertical cross-sectional view of a region of the second exemplary structure taken along vertical plane B-B' of fig. 35A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 35A.

Fig. 35C is a vertical cross-sectional view of a region of the second exemplary structure taken along the vertical plane C-C' of fig. 35A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 35A.

Fig. 35D is a vertical cross-sectional view of a region of the second exemplary structure taken along the vertical plane D-D' of fig. 35A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 35A.

Fig. 35E is a vertical cross-sectional view of the second exemplary structure of fig. 35A-35D. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 35A.

Fig. 36A is a horizontal cross-sectional view of a region of a second exemplary structure including backside trenches and in-process memory opening fill structures along a horizontal plane including a strip of insulating material after forming laterally extending cavities and removing portions of the memory film and sacrificial conformal spacers proximate to the laterally extending cavities in accordance with a second embodiment of the present disclosure.

Fig. 36B is a vertical cross-sectional view of a region of the second exemplary structure taken along vertical plane B-B' of fig. 36A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 36A.

Fig. 36C is a vertical cross-sectional view of a region of the second exemplary structure taken along the vertical plane C-C' of fig. 36A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 36A.

Fig. 36D is a vertical cross-sectional view of a region of the second exemplary structure taken along the vertical plane D-D' of fig. 36A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 36A.

Fig. 36E is a vertical cross-sectional view of the second exemplary structure of fig. 36A-36D. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 36A.

Fig. 37A is a horizontal cross-sectional view of a region of a second exemplary structure including backside trenches and in-process memory opening fill structures along a horizontal plane including a strip of insulating material after formation of a dielectric strip in a laterally extending cavity and in a pocket cavity in accordance with a second embodiment of the present disclosure.

FIG. 37B is a vertical cross-sectional view of a region of the second exemplary structure taken along the vertical plane B-B' of FIG. 37A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 37A.

Fig. 37C is a vertical cross-sectional view of a region of the second exemplary structure taken along the vertical plane C-C' of fig. 37A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 37A.

Fig. 37D is a vertical cross-sectional view of a region of the second exemplary structure taken along the vertical plane D-D' of fig. 37A. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 37A.

Fig. 37E is a vertical cross-sectional view of the second exemplary structure of fig. 37A-37D. The horizontal plane A-A' is the plane of the horizontal cross-sectional view of fig. 37A.

Fig. 38A-38D illustrate sequential vertical cross-sectional views of a memory opening filling structure and backside trenches during formation of a source level material layer according to a second embodiment of the present disclosure.

Fig. 39A-39C illustrate sequential vertical cross-sectional views of a memory opening filling structure and backside trench during replacement of a sacrificial material layer with a conductive layer according to a second embodiment of the present disclosure.

Fig. 40A is a vertical cross-sectional view of a second exemplary structure after a backside trench fill structure is formed in the backside trench in accordance with a second embodiment of the present disclosure.

Fig. 40B is a horizontal cross-sectional view of a second exemplary structure taken along horizontal plane B-B' of fig. 40A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 40A.

Fig. 41A is a vertical cross-sectional view of a second exemplary structure after formation of a drain cavity according to a second embodiment of the present disclosure.

Fig. 41B is a top view of a second exemplary structure taken along horizontal plane B-B' of fig. 40A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 40A.

Fig. 42 is a vertical cross-section of a region of the second exemplary structure at a processing step of fig. 41A and 41B.

Fig. 43A is a vertical cross-section of a region of a second exemplary structure after forming a channel cavity in accordance with a second embodiment of the present disclosure.

FIG. 43B is a horizontal cross-sectional view of a region of the second exemplary structure taken along horizontal plane B-B' of FIG. 43A. The vertical plane A-A' is the plane of the vertical cross-sectional view of fig. 43A.

FIG. 43C is a horizontal cross-sectional view of a region of the second exemplary structure taken along horizontal plane C-C' of FIG. 43A. The vertical plane A-A' is the plane of the vertical cross-sectional view of fig. 43A.

Fig. 44 is a vertical cross-sectional view of a second exemplary structure after an epitaxial semiconductor channel is formed in accordance with a second embodiment of the present disclosure.

Fig. 45A is a vertical cross-sectional view of a region of a second exemplary structure after forming epitaxial semiconductor channel and drain regions in accordance with a second embodiment of the present disclosure.

FIG. 45B is a horizontal cross-sectional view of a region of the second exemplary structure taken along horizontal plane B-B' of FIG. 45A. The vertical plane A-A' is the plane of the vertical cross-sectional view of fig. 45A.

FIG. 45C is a horizontal cross-sectional view of a region of the second exemplary structure taken along horizontal plane C-C' of FIG. 45A. The vertical plane A-A' is the plane of the vertical cross-sectional view of fig. 45A.

Fig. 46A is a vertical cross-sectional view of a second exemplary structure at a processing step of fig. 45A-45C.

Fig. 46B is a horizontal cross-sectional view of the second exemplary structure taken along horizontal plane B-B' of fig. 46A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 46A.

Fig. 47 is a vertical cross-sectional view of a second exemplary structure after forming through memory level via structures, contact via structures, and metal line structures in accordance with a second embodiment of the present disclosure.

Fig. 48A is a vertical cross-section of a third exemplary structure after forming an in-process source-level material layer on a substrate according to a third embodiment of the present disclosure.

Fig. 48B is an enlarged view of a region of the third exemplary structure of fig. 48A.

Fig. 49 is a vertical cross-sectional view of a third exemplary structure after forming an alternating stack of first layers according to a third embodiment of the present disclosure.

Fig. 50 is a vertical cross-sectional view of a third exemplary structure after forming a first stepped surface, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to a third embodiment of the present disclosure.

Fig. 51A is a vertical cross-sectional view of a third exemplary structure after forming a first tier memory opening and a first tier support opening in accordance with a third embodiment of the present disclosure.

Fig. 51B is a horizontal cross-sectional view of the third exemplary structure of fig. 51A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 51A.

Fig. 52 is a vertical cross-sectional view of a third exemplary structure after formation of various sacrificial fill structures in accordance with a third embodiment of the present disclosure.

Fig. 53 is a vertical cross-sectional view of a third exemplary structure after forming a second layer alternating stack of second insulating layers and second spacer material layers, second stepped surfaces, and second backward stepped dielectric material portions according to a third embodiment of the present disclosure.

Fig. 54A is a vertical cross-sectional view of a third exemplary structure after forming a second tier memory opening and a second tier support opening in accordance with a third embodiment of the present disclosure.

Fig. 54B is a horizontal cross-sectional view of the third exemplary structure taken along horizontal plane B-B' of fig. 54A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 54A.

Fig. 55 is a vertical cross-sectional view of a third exemplary structure after forming an interlayer memory opening and an interlayer support opening according to a third embodiment of the present disclosure.

Fig. 56A-56D illustrate sequential vertical cross-sectional views of a memory opening during formation of a memory opening fill structure according to a third embodiment of the present disclosure.

Fig. 57 is a vertical cross-sectional view of a third exemplary structure after forming a memory opening filling structure and a support pillar structure according to a third embodiment of the present disclosure.

Fig. 58A is a vertical cross-section of a third exemplary structure after formation of a post cavity according to a third embodiment of the present disclosure.

Fig. 58B is a horizontal cross-sectional view of the third exemplary structure taken along horizontal plane B-B' of fig. 58A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 58A.

Fig. 59 is a vertical cross-sectional view of a third exemplary structure after forming a dielectric pillar structure according to a third embodiment of the present disclosure.

Fig. 60A is a vertical cross-sectional view of a third exemplary structure after forming a first contact level dielectric layer and a backside trench in accordance with a third embodiment of the present disclosure.

Fig. 60B is a horizontal cross-sectional view of the third exemplary structure taken along horizontal plane B-B' of fig. 60A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 60A.

Fig. 61 is a vertical cross-sectional view of a third exemplary structure after formation of a backside trench spacer according to a third embodiment of the present disclosure.

Fig. 62A-62E illustrate sequential vertical cross-sectional views of a memory opening filling structure and a backside trench during formation of a source-level material layer according to a third embodiment of the present disclosure.

Fig. 63 is a vertical cross-sectional view of a third exemplary structure after formation of a source-level material layer in accordance with a third embodiment of the present disclosure.

Fig. 64 is a vertical cross-sectional view of a third exemplary structure after formation of a backside recess according to a third embodiment of the present disclosure.

Fig. 65A is a vertical cross-sectional view of a third exemplary structure after forming a conductive layer according to a third embodiment of the present disclosure.

Fig. 65B is a vertical cross-section of a region of the third exemplary structure of fig. 65A including a backside trench and two memory opening fill structures.

Fig. 66A is a vertical cross-sectional view of a third exemplary structure after forming insulating spacers and backside contact via structures in each backside trench according to a third embodiment of the present disclosure.

FIG. 66B is a horizontal cross-sectional view of the third exemplary structure taken along horizontal plane B-B' of FIG. 66A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 66A.

FIG. 66C is a vertical cross-sectional view of the third exemplary structure taken along the vertical plane C-C' of FIG. 66B.

Fig. 66D is a vertical cross-sectional view of a region of the third exemplary structure of fig. 66A-66C including a backside trench and two memory opening filling structures.

Fig. 67A is a vertical cross-sectional view of a third exemplary structure after forming a second contact level dielectric layer and various contact via structures according to a third embodiment of the present disclosure.

Fig. 67B is a horizontal cross-sectional view of the third exemplary structure taken along the vertical plane B-B' of fig. 67A. The hinge vertical plane A-A' corresponds to the plane of the vertical cross-section of fig. 67A.

Fig. 68 is a vertical cross-sectional view of a third exemplary structure after forming a higher metal line structure according to a third embodiment of the present disclosure.

Detailed Description

Various embodiments provide three-dimensional memory devices and methods of fabricating such devices including carbon-doped and boron-doped source contact layers. Carbon doping reduces boron diffusion from the source contact layer into the semiconductor channel. Various semiconductor devices, such as three-dimensional monolithic memory array devices including a plurality of NAND memory strings, may be formed using embodiments of the present disclosure. The figures are not drawn to scale.

The figures are not drawn to scale. Multiple instances of an element may be repeated where a single instance of the element is illustrated therein unless repetition of the element is explicitly described or otherwise clearly indicated as not being present. Numbers such as "first," "second," and "third" are used merely to identify similar elements, and different numbers may be employed throughout the specification and claims of this disclosure. The same reference numerals indicate the same or similar elements. Elements having the same reference number are assumed to have the same composition and the same function unless otherwise specified. Unless otherwise indicated, "contact" between elements refers to direct contact between elements that provides a shared edge or surface of the elements. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, a first element is positioned "directly on" a second element if there is physical contact between the surface of the first element and the surface of the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

As used herein, "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. In addition, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be positioned between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along the tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, and/or thereunder.

As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane comprising the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical by an angle of less than 5 degrees. The vertical plane or substantially vertical plane is straight along a vertical direction or substantially vertical direction and may or may not include a bend along a direction perpendicular to the vertical direction or substantially vertical direction.

As used herein, "memory level" or "memory array level" refers to a level that corresponds to a general area between a first horizontal plane that includes the topmost surface of the array of memory elements (i.e., a plane parallel to the top surface of the substrate) and a second horizontal plane that includes the bottommost surface of the array of memory elements. As used herein, "through stack" elements refer to elements that extend vertically through a memory level.

As used herein, "semiconductor material" means a semiconductor material having a dielectric constant of between 1.0x10 ^-5 S/m to 1.0X10 ⁵ A material of conductivity in the range of S/m. As used herein, "semiconductor material" means having a composition of 1.0x10 in the absence of an electrical dopant therein ^-5 A material having a conductivity in the range of S/m to 1.0S/m and capable of producing a material having a conductivity in the range of S/m when appropriately doped with an electrical dopant1.0S/m to 1.0X10 ⁵ A doping material of conductivity in the range of S/m. As used herein, "electrical dopant" refers to either a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" means having a dielectric constant greater than 1.0x10 ⁵ S/m conductivity material. As used herein, "insulator material" or "dielectric material" means having less than 1.0x10 ^-5 S/m conductivity material. As used herein, "heavily doped semiconductor material" refers to a material that becomes conductive (i.e., has a concentration of more than 1.0x10) when formed into a crystalline material or when converted into a crystalline material by an annealing process (e.g., starting from an initial amorphous state) doped with an electrical dopant at a sufficiently high atomic concentration ⁵ Conductivity of S/m). The "doped semiconductor material" may be a heavily doped semiconductor material, or may be comprised of a material provided at 1.0X10 s ^-5 S/m to 1.0X10 ⁵ A semiconductor material of electrical dopant (i.e., p-type dopant and/or n-type dopant) at a concentration of conductivity in the range of S/m. "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconducting or conducting, and may be intrinsic or doped. The doped semiconductor material may be semiconducting or conducting depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element therein. All conductivity measurements were performed under standard conditions.

A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "monomer" refers to the layer of each level of the array deposited directly on the layer of each lower level of the array. Instead, the two-dimensional array may be formed separately and then packaged together to form a non-unitary memory device. For example, as described in U.S. Pat. No. 5,915,167 entitled "Three-dimensional Structure memory (Three-dimensional Structure Memory)", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels prior to bonding, but such memories are not truly monolithic three dimensional memory arrays because the memory levels are initially formed above separate substrates. The substrate may include integrated circuits fabricated thereon, such as driver circuits for memory devices.

The three-dimensional memory devices of the various embodiments of the present disclosure include monolithic three-dimensional NAND string memory devices, and can be fabricated using the various embodiment methods described herein. The monolithic three-dimensional NAND strings are positioned in a monolithic three-dimensional NAND string array positioned above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is positioned above another memory cell in a second device level of the three-dimensional NAND string array.

Generally, a semiconductor package (or "package") refers to a unitary semiconductor device that may be attached to a circuit board by a set of pins or solder balls. The semiconductor package may include one or more semiconductor chips (or "chips") bonded therein, such as by flip-chip bonding or another chip-to-chip bonding. The package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. The die is the smallest unit that can independently execute external commands or report status. Typically, packages or chips with multiple dies are capable of executing as many external commands as the total number of planes therein at the same time. Each die includes one or more planes. The same concurrent operation may be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die including memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations may be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks") that are the smallest unit that can be erased by a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming. The page is also the smallest unit that can be selected for a read operation.

Referring to fig. 1A and 1B, a first exemplary structure according to an embodiment of the present disclosure is shown, including a substrate 8. The substrate 8 includes a substrate semiconductor layer 10. The substrate 8 may comprise a commercially available semiconductor wafer such as a monocrystalline silicon wafer, and the substrate semiconductor layer 10 may be a monocrystalline semiconductor material layer such as a monocrystalline silicon layer.

The substrate semiconductor layer 10 is a doped semiconductor layer having a doping of a first conductivity type (which may be p-type or n-type). The substrate semiconductor layer 10 may include an atomic concentration of 1.0X10 ¹⁴ /cm ³ Up to 1.0X10 ¹⁸ /cm ³ Electrical dopants of the first conductivity type, but smaller and larger atomic concentrations may also be used. Optionally, a portion of the substrate semiconductor layer 10 may be vertically recessed in the peripheral device region 400, and the peripheral semiconductor device 700 may be formed on the recessed surface of the substrate semiconductor layer 10. The memory array region 100 in which the three-dimensional array of memory devices is formed is then disposed outside the peripheral device region 400. Stair regions 200 may be provided between memory array region 100 and peripheral device region 400.

By implanting a dopant of the second conductivity type, a second conductivity type doped well 201 having a doping of the second conductivity type may be formed in an upper portion of the substrate semiconductor layer 10. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type and vice versa.

By implanting dopants of the first conductivity type, a first conductivity type doped well 202 having a doping of the first conductivity type may be formed in an upper portion of the second conductivity type doped well 201. The combination of the remaining portion of the substrate semiconductor layer 10, the second conductivity-type doped well 201 and the first conductivity-type doped well 202 forms a nested p-n-p junction structure or a nested n-p-n junction structure such that the first conductivity-type doped well 202 may be independently electrically biased from the substrate semiconductor layer 10. In one embodiment, the substrate 8 may comprise a layer of monocrystalline semiconductor material (such as a layer of monocrystalline silicon) such that each of the substrate semiconductor layer 10, the second conductivity-type doped well 201, and the first conductivity-type doped well 202 is part of the layer of monocrystalline semiconductor material.

A first alternating stack of first material layers and second material layers is formed over the substrate 8. In one embodiment, the first and second material layers may be the first insulating layer 132 and the first sacrificial material layer 142, respectively. In one embodiment, each first layer of insulating layer 132 may include a first insulating material, and each first layer of sacrificial material layer 142 may include a first sacrificial material. As used herein, "sacrificial material" refers to material that is removed during subsequent processing steps.

As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of a first element that is not an end element of the alternating plurality of elements abuts on both sides two instances of a second element, and each instance of a second element that is not an end element of the alternating plurality of elements abuts on both ends two instances of the first element. The first elements may have the same thickness therein, or may have different thicknesses. The second elements may have the same thickness therein, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or an instance of a second material layer, and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, the instances of the first element and the instances of the second element may form a unit that repeats periodically within the alternating plurality of elements.

The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selective to the first material of the first insulating layer 132. As used herein, the removal of a first material is "selective" to a "second material" if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first layer of sacrificial material 142 may then be replaced with a conductive electrode, which may be used as a control gate electrode for a vertical NAND device, for example. In one embodiment, the first layer of sacrificial material 142 may be a layer of material including silicon nitride.

In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include silicon nitride. The first material of the first layer of insulating layer 132 may be deposited, for example, by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for a CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and first sacrificial material layer 142 pairs in the first alternating stack (132, 142) may be in the range of 2 to 256, and typically in the range of 8 to 64, although more repetitions may be used. In one embodiment, each first layer of sacrificial material layer 142 in the first layer alternating stack (132, 142) may have a substantially uniform thickness throughout each respective first layer of sacrificial material layer 142.

The first alternating sequence (132, 142) terminates in a first insulating layer 132. A first laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342 is formed over the topmost first layer of insulating layer 132. Each of the insulating material strips 332 and the sacrificial material strips 342 may extend laterally along the first horizontal direction hd1 at respective uniform widths, and may be laterally spaced from each other along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd 1.

The first laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342 may be formed by: a blanket (unpatterned) layer of insulating material comprising strips 332 of insulating material is deposited, line trenches having a pattern of strips 342 of sacrificial material are formed through the layer of insulating material by a combination of photolithographic patterning process and anisotropic etching process, and a sacrificial material different from the material of the first layer 142 of sacrificial material is deposited in the line trenches. Excess portions of the sacrificial material may be removed from above a horizontal plane including a top surface of the remaining portions of the layer of insulating material by a planarization process. The remaining parts of the insulating-material layer constitute strips of insulating-material. Alternatively, the first laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342 may be formed by: a blanket (unpatterned) layer of material comprising strips of sacrificial material 342 is deposited, line trenches having a pattern of strips of insulating material 332 are formed by a combination of photolithographic patterning process and anisotropic etching process, and insulating material is deposited in the line trenches.

In one embodiment, the insulating material of insulating material strips 332 may comprise undoped silicate glass or doped silicate glass, and the sacrificial material of sacrificial material strips 342 may comprise a semiconductor material, such as amorphous silicon, polysilicon, or a silicon-germanium alloy. In one embodiment, the strip of insulating material 332 may comprise undoped silicate glass, and the strip of sacrificial material 342 may comprise undoped amorphous silicon.

Referring to fig. 2, a second alternating stack of additional first insulating layers 132 and additional first sacrificial material layers 142 may be formed over the first laterally alternating sequence of insulating material strips 332 and sacrificial material strips 342. The process steps for forming the first laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342 may be repeated to form a second alternating stack of additional first layer insulating layers 132 and additional first layer sacrificial material layers 142. The second alternating stack of additional first layer insulating layers 132 and additional first layer sacrificial material layers 142 may include the first layer insulating layers 132 as the bottommost layer that contacts the first laterally alternating sequence of insulating material strips 332 and sacrificial material strips 342. The number of repetitions of the first insulating layer 132 and first sacrificial material layer 142 pairs in the second alternating stack (132, 142) may be in the range of 2 to 256, and typically in the range of 8 to 64, although more repetitions may be used.

Optionally, the processing steps for forming the first laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342 and the processing steps for forming the second alternating stack of additional first layer insulating layers 132 and additional first layer sacrificial material layers 142 may be repeated to provide more than one laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342.

A first insulating cap layer 170 is then formed over the second alternating stack of additional first insulating layers 132 and additional first sacrificial material layers 142 (and any additional alternating stacks, if present). The first insulating cap layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating cap layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating cap layer 170 may be in the range of 20nm to 300nm, but smaller and larger thicknesses may also be used. The alternating stack (132, 142) of layers within the first insulating cap layer 170, the first insulating layer 132, and the first sacrificial material layer 142, and the first laterally alternating sequence of layers comprising the insulating material strips 332 and the sacrificial material strips 342 are collectively referred to as a first material layer (132,142,332,342,170).

Referring to fig. 3, the alternating stack (132, 142) of first insulating cap layer 170, first insulating layer 132, and first sacrificial material layer 142, and the first laterally alternating sequence of insulating material strips 332 and sacrificial material strips 342 may be patterned to form a first stepped surface in stair-section 200. Stair-section 200 may include respective first stepped regions in which a first layer of stepped surfaces is formed and second stepped regions in which additional stepped surfaces are subsequently formed in a second layer of structure (which is subsequently formed over the first layer of structure) and/or additional layer of structure. The first layer stepped surface may be formed, for example, by: forming a mask layer having an opening therein, etching a cavity within the level of the first layer insulating cap layer 170 and iteratively expanding the etched region, and vertically recessing the cavity by etching a lower pair of material layers within the first layer of material (132,142,332,342,170) positioned directly below the bottom surface of the etched cavity. In one embodiment, the top surface of the first layer of sacrificial material 142 may be physically exposed at the first layer stepped surface. The cavity overlying the first layer stepped surface is referred to herein as a first stepped cavity.

A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the region overlying the first layer stepped surface constitutes a first rearwardly stepped dielectric material portion 165. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first layer of material (132,142,332,342,170) and the first rearwardly stepped dielectric material portion 165 together form a first layer structure, which is an in-process structure that is subsequently modified.

An interlayer dielectric layer 180 may optionally be deposited over the first layer structure (132,142,332,342,170,165). The interlayer dielectric layer 180 includes a dielectric material such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may comprise doped silicate glass having a greater etch rate than the material of the first insulating layer 132 (which may comprise undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

Referring to fig. 4A and 4B, a first layer of memory opening 149 may be formed through a first layer of material (132,142,332,342,170) and into the first-conductivity-type-doped well 202 in the memory array region 100. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be lithographically patterned to form various openings therethrough. The pattern of openings in the photoresist layer may be transferred through the first layer of material (132,142,332,342,170) and into the first-conductivity-type-doped well 202 by a first anisotropic etching process to form a first-layer memory opening 149. The position of the steps S in the first layer alternating stack (132, 142) is shown in dashed lines in fig. 4B.

The first layer memory openings 149 are openings formed in the memory array region 100 through each layer within the first layer alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. The first layer of memory openings 149 may be formed as clusters of first layer of memory openings 149 that are laterally spaced apart along the second horizontal direction hd 2. Each cluster of first tier memory openings 149 may be formed as a two-dimensional array of first tier memory openings 149.

According to one aspect of the present disclosure, the first layer of memory openings 149 may be formed in rows extending laterally along the first horizontal direction hd 1. In one implementation, each row of first layer memory openings 149 may be formed as a one-dimensional periodic array having a periodic center-to-center spacing along a first horizontal direction hd1 between the geometric centers of each adjacent pair of first layer memory openings 149 within a row. In one embodiment, the first layer of memory openings 149 may be formed as a two-dimensional periodic array of first layer of memory openings 149. In this case, the rows of the first layer of memory openings 149 within the two-dimensional periodic array of first layer of memory openings 149 may have a uniform row-to-row spacing along the second horizontal direction hd 2. The remaining portion of each strip of insulating material 332 includes a platelet of insulating material positioned between an adjacent pair of memory openings 149 within a row of memory openings 49 arranged along the first horizontal direction hd 1.

According to one embodiment of the present disclosure, the pattern of strips of sacrificial material 342 may be selected such that each set of strips of sacrificial material 342 has a periodic pitch along the second horizontal direction hd2 that is the same as the row-to-row pitch of a set of first layer memory openings 149 positioned within the same area. Additionally, the pattern of strips of sacrificial material 342 may be selected such that each first layer of memory openings 149 extends between and cuts through an adjacent pair of strips of sacrificial material 342. Thus, each first layer of memory openings 149 may include a pair of sidewalls of the sacrificial material strips 342 laterally spaced apart along the second horizontal direction hd 2. Further, each first layer of memory openings 149 may include a pair of sidewalls of the strips of insulating material 332 that are laterally spaced apart along the first horizontal direction hd 1.

The processing step of the first anisotropic etching process may include an etching chemistry for etching through each material in the first layer of material (132,142,332,342,170). The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF ₄ /O ₂ Ar etch). The sidewalls of the first layer of memory openings 149 may be substantially vertical or may be tapered. The photoresist layer may then be removed, for example, by ashing.

Optionally, the portion of the first layer memory opening 149 at the level of the interlayer dielectric layer 180 may be laterally expanded by isotropic etching. In this case, the interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etching rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). An isotropic etch, such as a wet etch using HF, may be used to expand the lateral dimensions of the first layer memory openings 149 at the level of the interlayer dielectric layer 180. Portions of the first layer memory openings 149 located at the level of the interlayer dielectric layer 180 may optionally be widened to provide a larger landing pad for second layer memory openings that will subsequently be formed through the second layer alternating stack (which will subsequently be formed prior to forming the second layer memory openings).

Referring to fig. 5, where the strip of sacrificial material 342 comprises a semiconductor material, the physically exposed surface of the strip of sacrificial material 342 may be converted to a semiconductor oxide surface. An anisotropic etching process may be performed to remove any semiconductor oxide material from the bottom surface of each first layer memory opening 149. A selective semiconductor deposition process, such as a selective epitaxial or selective polycrystalline semiconductor deposition process, may be performed to grow doped semiconductor material having a doping of the first conductivity type. The first exemplary structure may be placed in a vacuum-sealed Chemical Vapor Deposition (CVD) chamber and a combination of a semiconductor precursor gas (such as a precursor gas of silane, disilane, dichlorosilane, trichlorosilane, silicon tetrachloride, germanium, or a compound semiconductor material), a dopant gas comprising atoms of an electrical dopant of a first conductivity type (e.g., diborane for a p-type dopant, or phosphine, arsine, or stibine for an n-type dopant), and an etchant gas (such as hydrogen chloride) flowed into the CVD chamber when the first exemplary structure is at an elevated temperature. The elevated temperature may be in the range of 500 degrees celsius to 900 degrees celsius. The epitaxial pedestal channel portion 11 may be grown from the physically exposed semiconductor surface of the first conductivity type doped well 202 at the bottom of each first layer memory opening 149.

In one embodiment, the top surface of each epitaxial pedestal channel portion 11 may be formed above a horizontal plane including the top surface of the bottommost first layer of sacrificial material layer 142. In this case, the source select gate electrode may then be formed by replacing the bottommost first sacrificial material layer 142 with a conductive material layer. The epitaxial pedestal channel portion 11 may be a portion of the transistor channel extending between a source region, which will then be formed in the first conductivity type doped well 202, and a drain region, which will then be formed at the upper end of each epitaxial semiconductor channel. In one embodiment, the epitaxial pedestal channel portion 11 may have a doping of the first conductivity typeWhich is the same conductivity type as the first conductivity type doped well 202. The epitaxial base channel portion 11 may include an atomic concentration of 1.0X10 ¹⁴ /cm ³ Up to 1.0X10 ¹⁸ /cm ³ Electrical dopants of the first conductivity type, but smaller and larger atomic concentrations may also be used.

An oxidation process may be performed to convert the upper surface region of the epitaxial pedestal channel portion 11 into a semiconductor oxide plate 13. A thermal oxidation process or a plasma oxidation process may be used to convert the upper surface region of the epitaxial pedestal channel portion 11 into a semiconductor oxide plate 13. Each semiconductor oxide plate 13 may have a vertical thickness in the range of 3nm to 10nm (such as 4nm to 8 nm), but smaller and larger thicknesses may also be used. A semiconductor oxide plate 13 may be formed within each of the first layer memory openings 149 and may contact sidewalls of the first layer of insulation 132 that contacts a top surface of a bottommost one of the first layer of sacrificial material 142. In other words, the semiconductor oxide plate 13 may contact the sidewall of the second bottommost layer in the first layer insulating layer 132. In one embodiment, the semiconductor oxide plate 13 may consist essentially of silicon oxide.

Referring to fig. 6, a sacrificial first layer memory opening filling portion 148 may be formed in the first layer memory opening 149 directly on and over the semiconductor oxide plate 13. For example, a sacrificial first layer of fill material is deposited simultaneously in each of the first layer of memory openings 149. The sacrificial first layer fill material includes a material that is subsequently removable selective to the material of the first layer insulating layer 132 and the first layer sacrificial material layer 142. A subset of the semiconductor oxide plates 13 disposed in the stair region 200 may be used as an etch stop structure in a subsequent etching process.

In one embodiment, the sacrificial first layer fill material may comprise a semiconductor material, such as silicon (e.g., a-Si or polysilicon), a silicon germanium alloy, germanium, a group III-V compound semiconductor material, or a combination thereof. In one embodiment, the sacrificial first layer fill material may comprise amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently removed selective to the first layer insulating layer 132 and the first layer sacrificial material layer 142.

Excess portions of the deposited sacrificial first layer fill material may be removed from over the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical Mechanical Planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may serve as an etch stop layer or a planarization stop layer.

Each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening fill portion 148. The top surface of the sacrificial first layer memory opening fill portion 148 may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer memory opening fill portions 148 may or may not include a cavity therein.

Referring to fig. 7, the process steps of fig. 1A and 1B and 2 may be repeated to form a third alternating sequence of second layer insulating layers 232 and second layer of sacrificial material layers 242, a second laterally alternating sequence of insulating material strips 332 and sacrificial material strips 342, and a fourth alternating sequence of second layer insulating layers 232 and second layer of sacrificial material layers 242. The second insulating layer 232 may have the same material composition and the same thickness as the first insulating layer 132. The second sacrificial material layer 242 may have the same material composition and the same thickness as the second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and second sacrificial material layer 242 pairs in the third alternating stack (232, 242) or in the fourth alternating stack (232, 242) may be in the range of 2 to 256, and typically in the range of 8 to 64, although more repetitions may be used. The second laterally alternating sequence of insulative material strips 332 and sacrificial material strips 342 may have the same pattern, the same thickness, and the same material composition as the first laterally alternating sequence of insulative material strips 332 and sacrificial material strips 342.

The process steps of fig. 3 may be performed to pattern a layer stack comprising an alternating stack (232, 242) of second layer insulating layers 232 and second layer sacrificial material layers 242, and a second laterally alternating sequence of layers comprising strips 332 of insulating material and strips 342 of sacrificial material, thereby forming a second stepped surface thereon. A dielectric material may be deposited and planarized to form second backward stepped dielectric material portions 265.

A second insulating cap layer 270 may then be formed over the alternating stacks (232, 242) of second insulating layers 232 and second sacrificial material layers 242. The second insulating cap 270 comprises a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating cap layer 270 may comprise silicon oxide.

Optionally, drain select level isolation structures 72 may be formed through a subset of layers in an upper portion of the fourth alternating stack (232, 242). The second sacrificial material layer 242 cut by the drain select level isolation structures 72 corresponds to the level at which the drain select level conductive layer is subsequently formed. The drain select level isolation structure 72 comprises a dielectric material, such as silicon oxide. The drain select level isolation structures 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd 1.

The layers within the second insulating cap 270, the alternating stack of second insulating layers 232 and second sacrificial material layers 242 (232, 242), and the second laterally alternating sequence of layers comprising strips 332 of insulating material and strips 342 of sacrificial material are collectively referred to as second layer material layers (232,242,332,342,270). The combination of the second layer of material (232,242,332,342,270), the second rearwardly stepped dielectric material portions 265 and the optional drain select level isolation structure 72 together constitute a second layer structure (232,242,332,342,270,265,72).

Referring to fig. 8A and 8B, a second layer memory opening 249 may be formed through a second layer structure (232,242,332,342,270,265,72). For example, a photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be lithographically patterned to form openings therethrough. The pattern of openings may be the same as the pattern of first layer memory openings 149, which is the same as sacrificial first layer memory opening fill portion 148. Thus, the photoresist layer may be patterned using a photolithographic mask for patterning the first layer memory openings 149.

The pattern of openings in the photoresist layer may be transferred through the second layer structure (232,242,332,342,270,265,72) by a second anisotropic etching process to form a second layer memory opening 249. The second layer memory openings 249 are formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening fill portions 148.

The second anisotropic etching process includes an etching step for etching a material of the second layer material layer (232,242,332,342,270). The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF ₄ /O ₂ Ar etch). The sidewalls of the second layer of memory openings 249 may be substantially vertical, or may be tapered. The bottom perimeter of each second layer memory opening 249 may be laterally offset and/or may be positioned entirely within the perimeter of the top surface of the underlying sacrificial first layer memory opening fill portion 148. Each second layer of memory openings 149 may include a pair of sidewalls of the sacrificial material strips 342 laterally spaced apart along a second horizontal direction hd 2. Each second layer of memory openings 149 may include a pair of sidewalls of the strip of insulating material 332 laterally spaced apart along the first horizontal direction hd 1. The remaining portion of each strip of insulating material 332 includes a platelet of insulating material positioned between an adjacent pair of memory openings 249 within a row of memory openings 249 arranged along the first horizontal direction hd 1. The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 9A-9D, the sacrificial first layer fill material of the sacrificial first layer memory opening fill portion 148 may be removed using an etching process that etches the sacrificial first layer fill material selective to the materials of the insulating layer (132, 232), the sacrificial material layer (142, 242), the insulating cap layer (170, 270), the interlayer dielectric layer 180, and the semiconductor oxide plate 13. In an illustrative example, if the sacrificial first layer memory opening filling portion 148 includes amorphous carbon, the sacrificial first layer memory opening filling portion 148 may be removed by an ashing process. If the sacrificial first layer memory opening fill portion 148 comprises amorphous silicon, the sacrificial first layer memory opening fill portion 148 may be removed by a wet etch process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide ("thermal TMY") or tetramethyl ammonium hydroxide (TMAH). Subsequently, the semiconductor oxide plates 13 may be removed by an etching process, which may use an isotropic etching process or an anisotropic etching process. For example, wet etching using dilute hydrofluoric acid may be used to remove the semiconductor oxide plates 13.

Each vertical stack of volumes of the first layer of memory openings 149 and the second layer of memory openings 249 constitutes a memory opening 49, which is also referred to as an inter-layer memory opening. The bottom portion of each memory opening 49 is filled within the epitaxial pedestal channel portion 11.

Generally, a first alternating stack of first insulating layers (such as first layer insulating layer 132 or second layer insulating layer 232) and first sacrificial material layers (such as first layer sacrificial material layers 142 or second layer sacrificial material layers 242) is formed over substrate 8. A laterally alternating sequence of insulative material strips 332 and sacrificial material strips 342 is formed over the first alternating stack. A second alternating stack of second insulating layers, such as first insulating layer 132 or second insulating layer 232, and second sacrificial material layers, such as first sacrificial material layers 142 or second sacrificial material layers 242, is formed over the laterally alternating sequence. The memory openings 19 are formed through at least the second alternating stack, the laterally alternating sequence, and the first alternating stack.

In one embodiment, each inter-layer memory opening may include a pair of sidewalls of the strip of sacrificial material 342 that are laterally spaced apart along the second horizontal direction hd2 at each level including a laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342. In addition, each of the interlayer memory openings may include a pair of sidewalls of the strip of insulating material 332 that are laterally spaced apart along the first horizontal direction hd1 at each level including a laterally alternating sequence of strips of insulating material 332 and strips of sacrificial material 342.

Referring to fig. 10A-10D, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a continuous sacrificial spacer material layer 160L may be sequentially deposited in each of the memory openings 49. Blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks leakage of stored charge to the control gate electrode. In one embodiment, blocking dielectric layer 52 comprises aluminum oxide. Alternatively or in addition, blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

Subsequently, the charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portion of charge trapping material including a dielectric charge trapping material (which may be silicon nitride, for example). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of conductive material, such as doped polysilicon or a metallic material, that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by forming into a sacrificial material layer (142, 242) within the lateral recess. In one embodiment, charge storage layer 54 comprises a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242) may be recessed laterally relative to the sidewalls of the insulating layer (132, 232), and the charge storage layer 54 may be formed as a plurality of memory material portions vertically spaced apart using a combination of a deposition process and an anisotropic etching process. The thickness of the charge storage layer 54 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used.

The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling may be performed under suitable electrical bias conditions. Charge tunneling may be performed by hot carrier injection or by fowler-nordheim tunneling induced charge transfer, depending on the mode of operation of the unitary three-dimensional NAND string memory device to be formed. Tunnel dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, tunnel dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, tunnel dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunnel dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used.

The stack of layers of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 forms memory film 50. A continuous layer 160L of sacrificial spacer material is deposited over the memory film 50. The continuous sacrificial spacer material layer 160L includes a material that is selectively removable with respect to the material of the memory film 50. For example, the continuous sacrificial spacer material layer I60L may comprise amorphous silicon, a silicon germanium alloy, or amorphous carbon. The continuous sacrificial spacer material layer 160L may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the continuous sacrificial spacer material layer 160L may be in the range of 2nm to 10nm, although lesser and greater thicknesses may also be used. Memory cavity 49' is stored within each volume of memory opening 49 that is not filled with a deposited material layer (52,54,56,160L).

In one implementation, the sacrificial contact via structure 718 may optionally be formed after forming the first backward stepped dielectric material portion 165 and before forming the second layer of material (232,242,332,342,270). The sacrificial contact via structure 718 may be formed by forming a contact via cavity through the first backward stepped dielectric material portion 165 on the peripheral semiconductor device 700 (such as a field effect transistor) and by filling the contact via cavity with a sacrificial material such as amorphous silicon.

Referring to fig. 11A to 11D, anisotropic etching of etching the material of the continuous sacrificial spacer material layer 160L and the memory film 50 may be performed to remove horizontal portions of the continuous sacrificial spacer material layer 160L and the memory film 50. The continuous sacrificial spacer material layer 160L and the memory film 50 are removed from over the second insulating cap layer 270 and at the bottom of each memory opening 49. The top surface of epitaxial pedestal channel portion 11 is physically exposed at the bottom of each memory cavity 49'. Each remaining portion of the continuous sacrificial spacer material layer 160L is referred to herein as a sacrificial conformal spacer 160. A set of all material portions within memory opening 49, referred to herein as in-process memory opening fill structure 158, may include epitaxial pedestal channel portion 11, memory film 50, and sacrificial conformal spacers 160.

Referring to fig. 12A-12C, a sacrificial capping material layer 137 may be anisotropically deposited over the second insulating cap layer 270. The sacrificial cover material layer 137 includes a sacrificial cover material that is a material that can enhance the etch profile of the underlying material portion in a subsequent anisotropic etching process by maintaining a straight sidewall profile during the subsequent anisotropic etching. In one embodiment, the sacrificial cover material layer 137 may comprise an amorphous carbon-based material. For example, sacrificial cover material layer 137 may comprise a material manufactured by America applications Material Inc ^TM Advanced patterned films are provided ^TM (APF). The memory opening 49 is covered with a sacrificial covering material. Each memory cavity 49' may be surrounded by a sacrificial conformal spacer 160 that resides within the corresponding memory opening 49 and is covered by the sacrificial cover material layer 137.

A photoresist layer (not shown) may be applied over sacrificial cover material layer 137 and may be lithographically patterned to form an array of openings in stair region 200. An anisotropic etching process is performed to transfer the pattern of the array of openings in the photoresist layer through the sacrificial cover material layer 137, the second layer structure (232,242,332,342,270,265,72), the first layer structure (132,142,332,342,170,165), and optionally into the substrate 8. The support opening 19 is formed by the second layer structure (232,242,332,342,270,265,72) and the first layer structure (132,142,332,342,170,165). In one implementation, each of the strips of sacrificial material 342 is at least partially cut through by at least one of the support openings 19. In one implementation, each of the strips of sacrificial material 342 includes at least one concave sidewall physically exposed to one of the support openings 19. The photoresist layer may then be removed.

In general, at least a subset of the support openings 19 may be formed through at least one of a first alternating stack of insulating layers (132 or 232) and sacrificial material layers (142 or 242), a laterally alternating sequence of insulating material strips 332 and sacrificial material strips 342, and a second alternating stack of additional insulating layers (132 or 232) and additional sacrificial material layers (142 or 242) overlying the laterally alternating sequence. In one embodiment, each support opening 19 may be cut through a respective one of the strips of sacrificial material 342.

Referring to fig. 13A-13C and 14A-14C, an isotropic etching process may be performed to etch the material of the sacrificial material strips 342 selective to the material of the insulating layer (132, 232), the sacrificial material layer (142, 242), the insulating cap layer (170, 270), and the first and second backward stepped dielectric material portions (165, 265). In one embodiment, if the strips of sacrificial material 342 comprise amorphous undoped silicon or silicon germanium alloy, a wet etch process may be performed to remove the strips of sacrificial material 342 along the longitudinal direction (i.e., the first horizontal direction hd 1) of each strip of sacrificial material 342, using hot trimethyl-2-hydroxyethyl ammonium hydroxide ("hot TMY") or tetramethyl ammonium hydroxide (TMAH). The void created by removing the strip of sacrificial material 342 is referred to herein as a laterally extending cavity 343. The sacrificial material strips 342 may be removed selective to the material of the memory film 50. In this case, the laterally extending cavity 343 may be laterally defined by the memory film 50 of the in-process memory opening fill structure 158.

Referring to fig. 15A-15C, when a sacrificial capping material layer 137 is present over the second layer insulating cap layer 270, at least one isotropic etching process may be performed to sequentially etch portions of the blocking dielectric layer 52, the charge storage layer 54, the tunneling dielectric layer 56, and the sacrificial conformal spacers 160 adjacent to the laterally extending cavities 343. The at least one isotropic etching process may be a sequence of isotropic etching processes. Upon lateral expansion of the laterally extending cavities 343, one or more (e.g., a pair of) side apertures are formed in the sidewalls of each memory opening 49 by etching each adjacent portion of the memory film 50 and the sacrificial conformal spacers 160. The laterally extending cavities 343 are connected to each reservoir cavity 49' through side apertures in the side walls of the reservoir openings 49. After at least one isotropic etching process, the memory cavity 49 'is combined with the laterally extending cavity 343 to form a network of cavities (343,49').

As shown with reference to fig. 16A to 16C, the sacrificial cover material layer 137 may be removed, for example, by ashing. An isotropic etching process of etching the material of the memory film 50 may be performed to remove the portion of the memory film 50 contacting the epitaxial pedestal channel portion 11. After removing the bottom portion of each memory film 50 over the peripheral portion of each epitaxial pedestal channel portion 11, an annular cavity 119 may be formed over the peripheral portion of each epitaxial pedestal channel portion 11. The entire topmost surface of each epitaxial pedestal channel portion 11 may be physically exposed after the isotropic etching process.

Referring to fig. 17A-17D, a dielectric material such as undoped silicate glass or doped silicate glass may be conformally deposited in the network (343,49') of cavities and in the support openings 19. In one embodiment, the dielectric material may include a doped silicate glass (such as borosilicate glass) that may then be etched selective to undoped silicate glass. Excess portions of the dielectric material may be removed from above a horizontal plane including the top surface of the second insulating cap layer 270. Each remaining portion of the dielectric material filling the support openings 19 constitutes a support column structure 120. The remainder of the dielectric material deposited in the volume of the laterally extending cavity 343 constitutes the dielectric strip 346. The remainder of the dielectric material deposited in the memory cavity 49' (i.e., within the volume of the memory opening 49) constitutes the dielectric core 62. The support post structure 120, the dielectric strips 346, and the dielectric core 62 are formed simultaneously. The support post structures 120, dielectric strips 346, and dielectric core 62 are interconnected to form a single unitary structure, i.e., a single continuous structure, without any physically visible interface structures therein. In one implementation, each of the dielectric cores 62 includes dielectric post portions 62P extending vertically through the first and second alternating stacks (132,146, 232, 246) of layers, and includes dielectric plug portions 62G extending laterally from the dielectric post portions 62P to respective side apertures to abut the respective dielectric strips 346 at each level of the dielectric strips 346. As used herein, the term "peg" refers to an outward protrusion of any shape, which is not limited to a cylindrical protrusion. In one embodiment, the peg may be a bracket or a post that supports the vertical column-shaped component in a lateral direction. In one embodiment, a pair of dielectric plug portions 62G extend laterally from the dielectric post portions 62P to respective side apertures to abut a respective pair of dielectric strips 346 at each level of the dielectric strips 346. However, in alternative embodiments, one dielectric plug portion or more than two dielectric plug portions may be formed. In one implementation, each of the dielectric strips 346 may encapsulate at least one laterally extending void extending along the first horizontal direction hd 1. Each laterally extending void may be laterally spaced from a sidewall of the reservoir opening 49.

Referring to fig. 18A-18E, an etching process is performed that etches the material of the sacrificial conformal spacers 160 selective to the material of the memory film 50, the dielectric core 62, the second insulating cap layer 270, and the support post structures 120. The etching process may be an isotropic etching process such as a wet etching process. In one embodiment, the sacrificial conformal spacers 160 can comprise undoped amorphous silicon or a silicon germanium alloy, and the etching process can comprise a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide ("thermal TMY") or tetramethyl ammonium hydroxide (TMAH).

Channel cavity 159 is formed, which includes the combined volume of sacrificial conformal spacer 160 and annular cavity 119. Each channel cavity 159 may include a void that includes the removed sacrificial conformal spacers 160 and the volume of the underlying annular cavity 119. The annular top surface of epitaxial pedestal channel portion 11 may be physically exposed at the bottom of each channel cavity 159. Each channel cavity 159 laterally surrounds the dielectric core 62. Each vertically extending portion of the channel cavity 159 may have a uniform lateral width that may be in the range of 10nm to 120nm, such as 20nm to 80nm, although smaller and larger uniform lateral widths may also be used. The dielectric plug portions 62G of the dielectric cores 62 provide structural support to the dielectric cores 62 by fixing the position of each dielectric core 62 relative to the dielectric strips 346 and insulating material strips 332 at each level at which the dielectric plug portions 62G are positioned during and after formation of the channel cavities 159.

Referring to fig. 19A to 19E, a selective epitaxial process may be performed to grow a doped single crystal semiconductor material having a first conductivity type in the channel cavity 159. For example, the first exemplary structure may be placed in a vacuum sealed selective epitaxial processing chamber and a combination of a semiconductor precursor gas (such as a precursor gas of silane, disilane, dichlorosilane, trichlorosilane, silicon tetrachloride, germanium, or a compound semiconductor material), a dopant gas comprising atoms of an electrical dopant of a first conductivity type (e.g., diborane for a p-type dopant, or phosphine, arsine, or stibine for an n-type dopant), and an etchant gas (such as hydrogen chloride) flowed into the selective epitaxial processing chamber while the first exemplary structure is maintained at an elevated temperature. The elevated temperature may be in the range of 500 degrees celsius to 900 degrees celsius. Epitaxial semiconductor channel 60 may be grown upward from the physically exposed semiconductor surface of epitaxial pedestal channel portion 11 within each memory opening 49 during a selective epitaxial process. The selective epitaxial process causes single crystal semiconductor material to grow up through the channel cavity 159 and around each of the dielectric plug portions 62G of the dielectric core 62. The epitaxial semiconductor channel 60 may fill the entire volume of the channel cavity 159. The dielectric plug portions 62G of the dielectric cores 62 provide structural support to the dielectric cores 62 by fixing the position of each dielectric core 62 relative to the dielectric strips 346 and insulating material strips 332 at each level at which the dielectric plug portions 62G are positioned during the selective epitaxy process.

The excess portion of monocrystalline semiconductor material grown above the horizontal plane including the top surface of the second insulating cap layer 270 may be removed by a planarization process, which may use chemical mechanical planarization. Each epitaxial semiconductor channel 60 may be epitaxially aligned with a layer of monocrystalline semiconductor material of substrate 8 (such as monocrystalline semiconductor material of first conductivity-type doped well 202) by intermediate monocrystalline material of intermediate epitaxial pedestal channel portion 11.

The top portion of each dielectric core 62 may be recessed vertically selective to the second insulating cap layer 270. In one embodiment, the second insulating cap layer 270 may comprise undoped silicate glass, and the dielectric core 62 may comprise doped silicate glass, such as borosilicate glass. In this case, wet etching using dilute hydrofluoric acid may be performed to vertically recess the dielectric core 62 selectively to the second insulating cap layer 270.

Doped semiconductor material having a second conductivity type doping may be deposited in the recessed volume overlying dielectric core 62. Excess portions of the deposited doped semiconductor material may be removed from above the horizontal plane including the top surface of the second layer of insulating cap layer 270, for example, by recess etching. Each remaining portion of doped semiconductor material having a doping of the second conductivity type constitutes a drain region 63. Drain region 63 may comprise a polycrystalline doped semiconductor material or a monocrystalline doped semiconductor material. The dopant concentration in the drain region 63 may be 5.0x10 ¹⁹ /cm ³ Up to 2.0X10 ²¹ /cm ³ But smaller and larger dopant concentrations may be used.

Each successive combination of memory film 50 and epitaxial semiconductor channel 60 constitutes a memory stack structure 55 that includes a vertical stack of memory elements therein. The vertical stack of memory elements may include portions of a charge storage layer positioned at each level of a sacrificial material layer (142, 242) that is subsequently replaced with a conductive layer. A set of all material portions that fill the memory opening after the formation of drain region 63 constitute memory opening fill structure 58. Each memory opening fill structure 58 includes an epitaxial pedestal channel portion 11, a memory film 50, an epitaxial semiconductor channel 60, a dielectric core 62, and a drain region 63. Each dielectric core 62 includes a dielectric post portion 62P and at least one pair of dielectric plug portions 62G. Each dielectric core 62 includes as many pairs of dielectric plug portions 62G as there are laterally alternating sequences of layers comprising insulating material strips 332 and dielectric strips 346. In one embodiment, each dielectric core 62 includes a dielectric post portion 62P and a plurality of dielectric plug portions 62G.

Referring to fig. 20A and 20B, a first contact level dielectric layer 280 may be formed over the second insulating cap layer 270. The first contact level dielectric layer 280 comprises a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100nm to 600nm, although lesser and greater thicknesses may also be used.

A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be lithographically patterned to form elongated openings extending along the first horizontal direction hd1 in the areas of the memory array region 100 and the stair region 200. An anisotropic etch may be performed to form a backside trench 79 having substantially vertical sidewalls extending through the first contact level dielectric layer 280, and a second layer structure (232,242,332,346,270,265,72) and a first layer structure (132,142,332,346,170,165) may be formed below the opening in the photoresist layer. A top surface of the first conductivity-type doped well 202 may be physically exposed at the bottom of each backside trench 79. In one embodiment, backside trenches 79 may be formed between clusters of memory stack structures 55. The clusters of memory stack structures 55 may be laterally spaced apart along the second horizontal direction hd2 by backside trenches 79. The photoresist layer may be removed, for example, by ashing.

Referring to fig. 21, the sacrificial material layer (142, 242) may be selectively removed for the insulating layer (132, 232), the insulating cap layer (170, 270), the first contact level dielectric layer 280, and the first conductivity type doped well 202. In particular, an etchant that selectively etches the material of the sacrificial material layer (142, 242) may be introduced into the backside trench 79, for example using an isotropic etching process, relative to the material of the insulating layer (132, 232), the insulating cap layer (170, 270), the back-step dielectric material portion (165, 265), and the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer (142, 242) may comprise silicon nitride, and the materials of the insulating layer (132, 232), the first and second insulating cap layers (170, 270), the portion of the rearwardly stepped dielectric material (165, 265), and the outermost layer of the memory film 50 may comprise a silicon oxide material.

The isotropic etching process may be a wet etching process using a wet etching solution, or may be a gas phase (dry) etching process in which an etchant is introduced into the backside trench 79 in a gas phase. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etch bath comprising phosphoric acid, the wet etching process etching silicon nitride selectively to silicon oxide, silicon, and various other materials used in the art.

A backside recess (143,243) is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recesses (143,243) include a first backside recess 143 formed in the volume from which the first layer of sacrificial material 142 is removed and a second backside recess 243 formed in the volume from which the second layer of sacrificial material 242 is removed. Each of the backside recesses (143,243) can be a laterally extending cavity having a lateral dimension that is greater than a vertical extent of the cavity. In other words, each of the backside recesses (143,243) can have a lateral dimension that is greater than a height of the respective backside recess (143,243). A plurality of backside recesses (143,243) can be formed in a volume of material from which the sacrificial material layers (142, 242) are removed. Each of the backside recesses (143,243) can extend substantially parallel to the top surface of the first-conductivity-type-doped well 202. The backside recess (143,243) can be vertically defined by a top surface of the underlying insulating layer (132, 232) and a bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143,243) can have a uniform height throughout.

An oxidation process may be performed to oxidize the physically exposed portions of epitaxial pedestal channel portions 11. A tubular semiconductor oxide spacer (not shown) may be formed around each epitaxial pedestal channel portion 11. A backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses (143,243) and backside trenches 79 and over the first contact level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the backside blocking dielectric layer may comprise aluminum oxide.

Referring to fig. 22A-22C, at least one conductive material may be deposited in the plurality of backside recesses (243), on the sidewalls of the backside trench 79, and over the first contact level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may comprise an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

In one embodiment, the at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recesses (143,243) include tungsten, tungsten nitride, titanium nitride, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, taN, WN or a combination thereof, and a conductive filler material such as W, co, ru, mo, cu or a combination thereof. In one embodiment, the at least one conductive material used to fill the backside recesses (143,243) can be a combination of a titanium nitride layer and a tungsten fill material.

A conductive layer (146,246) may be formed by depositing at least one conductive material in the backside recess (143,243). A plurality of first layer conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second layer conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous layer of metal material (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact level dielectric layer 280. Each of the first and second conductive layers 146 and 246 may include a respective conductive metal nitride liner and a respective conductive filler material. Thus, the first and second sacrificial material layers (142, 242) may be replaced with conductive layers (146,246), respectively. Specifically, each first layer of sacrificial material 142 may be replaced with an optional portion of a backside blocking dielectric layer and first layer of conductive layer 146, and each second layer of sacrificial material 242 may be replaced with an optional portion of a backside blocking dielectric layer and second layer of conductive layer 246. A backside cavity is present within the portion of each backside trench 79 that is not filled with a continuous layer of metal material.

Residual conductive material may be removed from inside the backside trench 79. In particular, the deposited metal material of the continuous metal material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metallic material in the first backside recess constitutes a first layer of conductive layer 146. Each remaining portion of the deposited metallic material in the second backside recess constitutes a second layer of conductive layer 246. The sidewalls of the first and second conductive material layers 146, 79 may be physically exposed to the respective backside trenches. The backside trench may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.

Each conductive layer (146,246) can be a conductive sheet including an opening therein. A first subset of the openings through each conductive layer (146,246) can be filled with memory opening fill structures 58. A second subset of the openings through each conductive layer (146,246) can be filled with support post structures 120. Each conductive layer (146,246) can have a smaller area than any underlying conductive layer (146,246) due to the first and second stepped surfaces. Each conductive layer (146,246) can have a larger area than any overlying conductive layer (146,246) due to the first and second stepped surfaces.

In some embodiments, drain select level isolation structures 72 may be provided at the topmost level of the second layer of conductive layer 246. A subset of the second conductive layers 246 positioned at the level of the drain select level isolation structure 72 constitute a drain select gate electrode. A subset of the conductive layers (146,246) positioned under the drain select gate electrode can be used as a combination of control gates and word lines positioned at the same level. The control gate electrode within each conductive layer (146,246) is a control gate electrode for a vertical memory device comprising a memory stack structure 55.

A backside trench fill structure 76 may be formed within each backside trench 79. Each backside trench fill structure 76 may be comprised of at least one dielectric fill material such as silicon oxide, silicon nitride, and/or dielectric metal oxide material. Alternatively, the backside trench fill structure 76 may include a laterally insulated source contact via structure including a conductive via structure contacting the first conductivity-type doped well 202 and a dielectric spacer laterally surrounding the conductive via structure.

Referring to fig. 23, a second contact level dielectric layer 282 may be formed over the first contact level dielectric layer 280. The second contact level dielectric layer 282 comprises a dielectric material such as silicon oxide and may have a thickness in the range of 100nm to 600nm, although lesser and greater thicknesses may also be used.

A photoresist layer (not shown) may be applied over the second contact level dielectric layer 282 and may be lithographically patterned to form various contact via openings. For example, an opening for forming drain contact via structure 88 may be formed in memory array region 100 and an opening for forming stair-case contact via structure 86 may be formed in stair-case region 200. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the second and first contact level dielectric layers (282,280) and underlying portions of dielectric material. The drain region 63 and the conductive layer (146,246) can function as an etch stop structure. A drain contact via cavity may be formed over each drain region 63 and a stair-step region contact via cavity may be formed over each conductive layer (146,246) at a stair-step surface under the first and second rearwardly-directed stair-step dielectric material portions (165, 265). The photoresist layer may then be removed, for example, by ashing.

A drain contact via structure 88 is formed in the drain contact via cavity and on a top surface of a respective one of the drain regions 63. A stair-region contact via structure 86 is formed in the stair-region contact via cavity and on a top surface of a respective one of the conductive layers (146,246). Stair-region contact via structures 86 may include drain select level contact via structures that contact a subset of second layer conductive layer 246 that serves as a drain select level gate electrode. Furthermore, the stair-region contact via structures 86 may include word line contact via structures that contact the conductive layer (146,246) under the drain select level gate electrode and serve as word lines for the memory stack structure 55.

A first through memory level via cavity may be formed through the second and first contact level dielectric layers (282,280) and the second and first backward stepped dielectric material portions (265,165) and to a respective one of the peripheral semiconductor devices 700. A second through memory level via cavity may be formed through the interconnect region dielectric fill material portion 584 to a respective one of the additional peripheral semiconductor devices 700. At least one conductive material may be deposited in the first through memory level via cavity and in the second through memory level via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the second contact level dielectric layer 282. Each remaining portion of the at least one conductive material in the first through memory level via cavity constitutes a first through memory level via structure 488. Each remaining portion of the at least one conductive material in the second through memory level via cavity constitutes a second through memory level via structure 588.

At least one additional dielectric layer may be formed over the contact level dielectric layer (280, 282), and additional metal interconnect structures (referred to herein as higher level metal interconnect structures) may be formed in the at least one additional dielectric layer. For example, the at least one additional dielectric layer may include a line level dielectric layer 290 formed over the contact level dielectric layer (280, 282). The higher level metal interconnect structure may include: a bit line 98 contacting a respective one of the drain contact via structures 88; and an interconnect line structure 96 that contacts and/or electrically connects to at least one of the stair-section contact via structure 86 and/or the first pass-through memory level via structure 488 and/or the second pass-through memory level via structure 588.

In one embodiment, the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device, the conductive strips (146,246) comprise or are electrically connected to respective word lines of the monolithic three-dimensional NAND memory device, the substrate 8 comprises a silicon substrate, the monolithic three-dimensional NAND memory device comprises a monolithic three-dimensional NAND string array over the silicon substrate, and at least one memory cell in a first device level of the monolithic three-dimensional NAND string array is positioned over another memory cell in a second device level of the monolithic three-dimensional NAND string array. The silicon substrate may contain an integrated circuit including driver circuitry for a memory device positioned thereon, the conductive stripe (146,246) comprising a plurality of control gate electrodes having a stripe shape extending substantially parallel to a top surface of the substrate 8, the plurality of control gate electrodes comprising at least a first control gate electrode positioned in a first device level and a second control gate electrode positioned in a second device level. The monolithic three dimensional NAND string array comprises a plurality of epitaxial semiconductor channels 60 extending substantially perpendicular to the top surface of substrate 8. The monolithic three dimensional NAND string array comprises a plurality of charge storage elements (including portions of memory film 50). Each charge storage element may be positioned adjacent a respective one of the plurality of epitaxial semiconductor channels 60.

Referring collectively to fig. 1A-23 and according to various embodiments of the present disclosure, there is provided a three-dimensional memory device comprising: a first alternating stack of first insulating layers (such as first layer insulating layers 132 or second layer insulating layers 232 positioned under the laterally alternating sequence of insulating material strips 332 and dielectric strips 346) and first conductive layers (such as first layer conductive layers 146 or second layer conductive layers 246 positioned under the laterally alternating sequence of insulating material strips 332 and dielectric strips 346), the first alternating stack being positioned above substrate 8; a second alternating stack of second insulating layers (such as first layer insulating layers 132 or second layer insulating layers 232 positioned over the laterally alternating sequences of insulating material strips 332 and dielectric strips 346) and second conductive layers (such as first layer conductive layers 146 or second layer conductive layers 246 positioned over the laterally alternating sequences of insulating material strips 332 and dielectric strips 346) positioned over and spaced apart from the first alternating stack; a reservoir opening 49 extending vertically through the first alternating stack and the second alternating stack, wherein each of the reservoir openings 49 includes a pair of side apertures positioned between the first alternating stack and the second alternating stack; and a memory opening fill structure 58 positioned in a respective one of the memory openings 49 and including a memory film 50, a semiconductor channel, and a dielectric core 62 including a dielectric fill material, wherein the dielectric core 62 includes a dielectric post portion 62P and a dielectric plug portion 62G extending laterally from the dielectric post portion 62P through a hole in the semiconductor channel and abutting the respective side aperture.

In one embodiment, the dielectric plug portion 62G is connected to a dielectric strip 346 of dielectric fill material positioned outside the memory opening 49 and positioned between the first alternating stack and the second alternating stack. The dielectric strips 146 of dielectric filler material include a plurality of dielectric strips 146 extending laterally along a first horizontal direction hd1 and spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd 2.

In one embodiment, the three-dimensional memory device includes a support pillar structure 120 that extends vertically through at least a subset of layers (including dielectric fill material) within the first and second alternating stacks and abuts a respective one of the plurality of dielectric strips 346.

In one embodiment, the first alternating stack comprises a first stepped surface, wherein the first conductive layer has a lateral extent that decreases with vertical distance from the substrate 8; the second alternating stack comprises a second stepped surface, wherein the second conductive layer has a lateral extent that decreases with vertical distance from the substrate 8; and a backward stepped dielectric material portion (such as a first backward stepped dielectric material portion 165 and a second backward stepped dielectric material portion 265) overlying the first stepped surface and the second stepped surface, wherein the support post structures 120 extend vertically through the backward stepped dielectric material portion.

In one implementation, each of the plurality of dielectric strips 346 has two sets of straight sidewall sections (extending laterally along the first horizontal direction hd 1), where each set of straight sidewall sections includes a plurality of straight sidewall sections positioned within a respective vertical plane extending along the first horizontal direction hd 1. A subset of the sidewall segments may extend laterally between an adjacent pair of the memory openings 49 within a row of memory openings 49.

The subset of the remaining portions of the strips of insulating material 332 may include a sheet of insulating material positioned between an adjacent pair of memory openings 49, the sheet of insulating material being laterally spaced apart along the first horizontal direction hd1 and positioned between an adjacent pair of dielectric strips 346. Each of the insulating-material platelets may include a pair of concave sidewalls that conform to the sidewalls of a pair of memory openings 49. In one embodiment, a three-dimensional memory device includes a two-dimensional array of insulating material platelets, with one row of insulating material platelets positioned between each adjacent pair of dielectric strips.

In one implementation, the three-dimensional memory device includes drain regions 63 that contact the upper ends of respective ones of the semiconductor channels and contact the top surfaces of respective ones of the dielectric pillar portions 62P.

In one embodiment, a layer of monocrystalline semiconductor material (e.g., substrate semiconductor layer 10) is positioned in or over substrate 8, wherein the semiconductor channel comprises an epitaxial semiconductor channel epitaxially aligned with the layer of monocrystalline semiconductor material. The three-dimensional memory device includes an epitaxial pedestal channel portion 11 that contacts and is epitaxially aligned with a respective one of the monocrystalline semiconductor material layer and the epitaxial semiconductor channel 60. In one implementation, each of epitaxial pedestal channel portions 11 includes an annular top surface that contacts an annular bottom surface of a respective one of epitaxial semiconductor channels 60. The periphery of the annular bottom surface of a respective one of the epitaxial semiconductor channels 60 contacts one of the first insulating layers.

In one implementation, each of the epitaxial pedestal channel portions 11 contacts a bottom surface of a respective one of the dielectric pillar portions 62P and a bottom portion of a cylindrical sidewall of the dielectric pillar portion 62P.

In one embodiment, epitaxial semiconductor channel 60 comprises a material selected from monocrystalline silicon, monocrystalline silicon germanium alloy, or monocrystalline group III-V compound semiconductor material; and the dielectric filler material is selected from undoped silicate glass, doped silicate glass or organosilicate glass.

In one implementation, each of the semiconductor channels has a circular horizontal cross-sectional shape at a first alternating stacked level and at a second alternating stacked level, and a pair of block-arc horizontal cross-sectional shapes at the level of the dielectric plug portion 62G. As used herein, a block arc refers to a shape derived from the shape of a ring by limiting the range of azimuth angles of the shape to less than 360 degrees around the geometric center of the ring.

In one embodiment, each of the side apertures in the reservoir opening 49 has a rectangular shape with the same height as the vertical separation distance between the first and second alternating stacks, which is the same height as the insulating material strips 332.

In one embodiment, the three-dimensional memory device includes at least one additional alternating stack of additional insulating layers (such as a third alternating stack of second insulating layers 232 and second conductive layers 246) and additional conductive layers (such as a fourth alternating stack of additional second insulating layers 232 and additional second conductive layers 246) positioned over the second alternating stack (which may be the second alternating stack of first insulating layers 132 and first conductive layers 146 overlying the level of the set of insulating material strips 332 and dielectric strips 346 in the first layer structure), wherein each of the dielectric cores 62 includes additional dielectric plug portions 62G extending laterally from the respective dielectric post portions 62P over the at least one additional alternating stack.

Referring to fig. 24, a second exemplary structure according to a second embodiment of the present disclosure includes a substrate 8. The substrate 8 includes a substrate semiconductor layer 10, which may be a layer of monocrystalline semiconductor material, such as a layer of monocrystalline silicon. The substrate semiconductor layer 10 may have a doping of the first conductivity type. The atomic concentration of the dopant of the first conductivity type in the substrate semiconductor layer 10 may be 1.0X10 ¹⁴ /cm ³ Up to 1.0X10 ¹⁷ /cm ³ Although smaller and larger dopant concentrations may be used. The peripheral semiconductor device 700 may be formed on the concave surface of the substrate semiconductor layer 10 in the peripheral device region 400. Shallow trench isolation structures 12 may be provided to provide electrical isolation between the peripheral semiconductor device 700 and devices that will be subsequently formed in the memory array region 100 and the stair region 200.

Sacrificial etch stop liner and source level sacrificial layer 104 may be formed in memory array region 100 and in stair region 200. The sacrificial etch stop liner comprises a material that can be used as an etch stop material during removal of the source level sacrificial layer 104. For example, the sacrificial etch stop liner may comprise silicon oxide, silicon nitride, and/or a dielectric metal oxide. In one embodiment, the sacrificial etch stop liner may comprise a silicon oxide layer having a thickness in the range of 2nm to 30nm, although lesser and greater thicknesses may also be used.

Source level sacrificial layer 104 includes a sacrificial material that is selectively removable with respect to a sacrificial etch stop liner and a subsequently formed first layer of insulating layer 132. In one implementation, source-level sacrificial layer 104 may comprise amorphous carbon. Alternatively, source-level sacrificial layer 104 may comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy having an atomic concentration of germanium greater than 20%. The thickness of source level sacrificial layer 104 may be in the range of 30nm to 400nm, such as 60nm to 200nm, although lesser and greater thicknesses may also be used.

An alternating stack of first insulating layers 132 and first sacrificial material layers 142 may be formed over source-level sacrificial layers 104. The first insulating layer 132 and the first sacrificial material layer 142 may have the same composition and the same thickness as those in the first embodiment. The process steps of fig. 1 may be performed to form an alternating stack of first insulating layers 132 and first sacrificial material layers 142, which are referred to herein as first layer alternating stacks (132, 142). The number of repetitions of the first insulating layer 132 and first sacrificial material layer 142 pairs in the first layer alternating stack (132, 142) may be in the range of 16 to 1,024, and typically in the range of 32 to 256, although more repetitions may be used.

A first insulating cap layer 170 is then formed over the first alternating stack of layers (132, 142). In one embodiment, the first insulating cap layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating cap layer 170 may be in the range of 20nm to 300nm, but smaller and larger thicknesses may also be used.

Referring to fig. 25, the first insulating cap layer 170 and the first alternating stack of layers (132, 142) may be patterned to form a first stepped surface in the stair region 200. The stair region 200 may include respective first stepped regions in which a first stepped surface is formed and second stepped regions in which additional stepped surfaces are subsequently formed in a second layer structure (which is subsequently formed over the first layer structure) and/or an additional layer structure. The first stepped surface may be formed, for example, by forming a mask layer (not shown) having openings therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively expanding the etched region, and vertically recessing the cavity by etching each of the first insulating layer 132 and first sacrificial material layer 142 pairs positioned directly below the bottom surface of the etched cavity within the etched region. In one embodiment, the top surface of the first layer of sacrificial material 142 may be physically exposed at the first stepped surface. The cavity overlying the first stepped surface is referred to herein as a first stepped cavity.

A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the region overlying the first stepped surface constitutes a first rearwardly stepped dielectric material portion 165. As used herein, a "rearwardly stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first alternating stack of layers (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is an in-process structure that is subsequently modified.

An interlayer dielectric layer 180 may optionally be deposited over the first layer structure (132,142,170,165). The interlayer dielectric layer 180 includes a dielectric material such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may comprise doped silicate glass having a greater etch rate than the material of the first insulating layer 132 (which may comprise undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

Referring to fig. 26A and 26B, various first layer openings (149,129) can be formed through the interlayer dielectric layer 180, the first layer structure (132,142,170,165), the source-level sacrificial layer 104, and into the substrate semiconductor layer 10. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be lithographically patterned to form various openings therethrough. The pattern of openings in the photoresist layer may be transferred through the interlayer dielectric layer 180 and the first layer structure (132,142,170,165) and into the source-level sacrificial layer 104 by a first anisotropic etching process to simultaneously (i.e., during the first isotropic etching process) form various first layer openings (149,129). Various first layer openings (149,129) can include a first layer reservoir opening 149 and a first layer support opening 129. The position of the steps S in the first alternating stack (132, 142) is shown in dashed lines in fig. 26B.

The first layer memory openings 149 are openings formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. The first layer of memory openings 149 may be formed as clusters of first layer of memory openings 149 that are laterally spaced apart along the second horizontal direction hd 2. Each cluster of first tier memory openings 149 may be formed as a two-dimensional array of first tier memory openings 149.

The first layer support openings 129 are openings formed in the stairway area 200 and subsequently used to form the support column structures. A subset of the first layer support openings 129 formed through the first rearwardly stepped dielectric material portion 165 may be formed through a corresponding horizontal surface of the first stepped surface.

In one embodiment, the first anisotropic etching process may include an initial step in which the material of the first layer alternating stack (132, 142) is etched simultaneously with the material of the first backward stepped dielectric material portion 165. The chemistry of the initial etching step may be alternated to optimize etching of the first material and the second material in the first layer alternating stack (132, 142) while providing an average etch rate comparable to the material of the first backward stepped dielectric material portion 165. The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF ₄ /O ₂ Ar etch). The sidewalls of the various first layer openings (149,129) can be substantially vertical or can be tapered.

Optionally, portions of the first layer memory openings 149 and the first layer support openings 129 at the level of the interlayer dielectric layer 180 may be laterally expanded by isotropic etching. In this case, the interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etching rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). An isotropic etch, such as a wet etch using HF, may be used to expand the lateral dimensions of the first layer memory openings 149 at the level of the interlayer dielectric layer 180. Portions of the first layer memory openings 149 located at the level of the interlayer dielectric layer 180 may optionally be widened to provide a larger landing pad for second layer memory openings that will subsequently be formed through the second layer alternating stack (which will subsequently be formed prior to forming the second layer memory openings).

Referring to fig. 27A and 27B, a sacrificial first layer opening filling portion (148,128) may be formed in various first layer openings (149,129).

For example, a sacrificial first layer fill material is deposited simultaneously in each of the first layer openings (149,129). The sacrificial first layer fill material includes a material that is subsequently removable selective to the material of the first layer insulating layer 132 and the first layer sacrificial material layer 142.

In one embodiment, the sacrificial first layer fill material may comprise a semiconductor material, such as silicon (e.g., a-Si or polysilicon), a silicon germanium alloy, germanium, a group III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1nm to 3 nm) may be used prior to depositing the sacrificial first layer fill material. The sacrificial first layer of filler material may be formed by non-conformal deposition or conformal deposition methods.

In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the materials of the first layer insulating layer 132, the first layer insulating cap layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may comprise borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times greater than the etch rate of dense TEOS oxide in 100:1 diluted hydrofluoric acid (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densification in an annealing process). In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1nm to 3 nm) may be used prior to depositing the sacrificial first layer fill material. The sacrificial first layer of filler material may be formed by non-conformal deposition or conformal deposition methods.

In yet another embodiment, the sacrificial first layer of filler material may comprise amorphous silicon or a carbonaceous material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently removed selective to the material of the first alternating stack (132, 142).

Portions of the deposited sacrificial material may be removed from over the topmost layer of the first layer alternating stack (132, 142), such as from over the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical Mechanical Planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may serve as an etch stop layer or a planarization stop layer.

The remaining portion of the sacrificial first layer fill material includes a sacrificial first layer opening fill portion (148,128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support openings 129 constitutes a sacrificial first layer support opening fill portion 128. The various sacrificial first layer opening fill portions (148,128) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from over the first alternating stack (132, 142), such as from over the top surface of the inter-layer dielectric layer 180. A top surface of the sacrificial first layer opening filling portion (148,128) may be coplanar with a top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening fill portions (148,128) may or may not include a cavity therein.

Referring to fig. 28A and 28B, a photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and lithographically patterned to form a pattern of line-shaped openings extending laterally along the second horizontal direction hd 2. The location and width of the line-shaped openings in the photoresist layer are selected such that each sacrificial first layer memory opening fill portion 148 includes a peripheral region positioned under a respective one of the line-shaped openings in the photoresist layer. In one implementation, each overlapping region between the top surface of the sacrificial first layer memory opening fill portion 148 and the region of the linear opening in the photoresist layer may have the shape of a circular segment. As used herein, a "circular segment" is a circular region "cut" from the remainder of the circle by a secant or chord.

An anisotropic etching process is performed to etch the material of the inter-layer dielectric layer 180 selective to the material of the sacrificial first layer memory opening fill portion 148. For example, the interlayer dielectric layer 180 may include silicon oxide, and the sacrificial first layer memory opening filling portion 148 may include amorphous silicon. In this case, the anisotropic etching process may use an etching chemistry that selectively etches silicon oxide with respect to silicon. A line trench 181 is formed through the interlayer dielectric layer 180. Each of the line trenches 181 may include a laterally alternating sequence of planar sidewall sections and convex sidewall sections. Each of the convex sidewall sections may be part of a cylindrical sidewall of the sacrificial first layer memory opening fill portion 148.

The line trenches 181 may be formed as a one-dimensional array of line trenches 181 having a uniform center-to-center spacing along the first horizontal direction. In one embodiment, the sacrificial first layer memory opening fill portions 148 may be formed in columns extending laterally along the second horizontal direction hd 2. In one implementation, the uniform center-to-center spacing within the one-dimensional array of line trenches 181 may be twice the column-to-column spacing of the sacrificial first layer memory opening fill portions 148. In one implementation, only one side of each sacrificial first layer memory opening fill portion 148 may be physically exposed to a respective one of the line trenches 181. Each patterned portion of the interlayer dielectric layer 180 between an adjacent pair of line trenches 181 is referred to herein as a strip 182 of insulating material. A laterally alternating sequence of strips 182 of insulating material and wire trenches 181 are formed in the area of the memory array region 100.

Referring to fig. 29A and 29B, a sacrificial material is deposited in the line trenches 181 and over the interlayer dielectric layer 180. The sacrificial material includes a material different from that of the first insulating layer 132, the first sacrificial material layer 142, the first insulating cap layer 170, and the interlayer dielectric layer 180. In one embodiment, the sacrificial material may comprise amorphous carbon, organosilicate glass, amorphous undoped silicon, or a silicon germanium alloy. Excess portions of the sacrificial material may be removed from above a horizontal plane including the top surface of the interlayer dielectric layer 180. Each remaining portion of the sacrificial material in a respective one of the line trenches 181 constitutes a strip 183 of sacrificial material. A laterally alternating sequence of strips 182 of insulating material and strips 183 of sacrificial material are formed over the first insulating cap layer 170, i.e., at the level of the interlayer dielectric layer 180. The remaining portion of interlayer dielectric layer 180 may be positioned in stair region 200 and the laterally alternating sequence of insulating material strips 182 and sacrificial material strips 183 may be positioned within memory array region 100.

Referring to fig. 30, a second layer structure may be formed over the first layer structure (132,142,170,148,128). The second layer structure may comprise an additional alternating stack of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers may then be formed on a top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes alternating third and fourth pluralities of material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first layer insulating layer 132, and the fourth material may be the same as the second material of the first layer sacrificial material layer 142.

In one embodiment, the third material layer may be the second insulating layer 232 and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be removed selective to the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second layer of sacrificial material 242 may then be replaced with a conductive electrode, which may be used as a control gate electrode for a vertical NAND device, for example.

In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second layer alternating stack (232, 242) may include alternating pluralities of second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by Chemical Vapor Deposition (CVD). The fourth material of the second layer of sacrificial material 242 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be removed selective to the third material of the second insulating layer 232. The sacrificial material that may be used for the second layer of sacrificial material 242 may be any material that may be used for the first layer of sacrificial material 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

The thickness of the second insulating layer 232 and the second sacrificial material layer 242 may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and second sacrificial material layer 242 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although more repetitions may be used. In one embodiment, each second layer of sacrificial material 242 in the second alternating stack (232, 242) may have a uniform thickness that is substantially constant within each respective second layer of sacrificial material 242.

The second stepped surface in the second stepped region may be formed in the stair region 200 using the same set of processing steps as the processing steps used to form the first stepped surface in the first stepped region, with the pattern of the at least one mask layer being suitably adjusted. A second backward stepped dielectric material portion 265 may be formed over the second stepped surface in the stairwell 200.

A second insulating cap layer 270 may then be formed over the second alternating stack (232, 242). The second insulating cap 270 comprises a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating cap layer 270 may comprise silicon oxide. In one embodiment, the first and second layers of sacrificial material (142, 242) may comprise silicon nitride.

Optionally, drain select level isolation structures 72 may be formed through a subset of layers in an upper portion of the second layer alternating stack (232, 242). The second sacrificial material layer 242 cut by the drain select level isolation structures 72 corresponds to the level at which the drain select level conductive layer is subsequently formed. The drain select level isolation structure 72 comprises a dielectric material, such as silicon oxide. The drain select level isolation structures 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd 1. The combination of the second alternating stack (232, 242), the second backward stepped dielectric material portion 265, the second layer insulating cap 270 and the optional drain select level isolation structure 72 together constitute a second layer structure (232,242,265,270,72).

Referring to fig. 31A and 31B, various second layer openings (249,229) may be formed through the second layer structure (232,242,265,270,72). A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be lithographically patterned to form various openings therethrough. The pattern of openings may be the same as the pattern of the various first layer openings (149,129), which is the same as the sacrificial first layer opening fill portions (148,128). Thus, the photoresist layer may be patterned using a photolithographic mask for patterning the first layer openings (149,129).

The pattern of openings in the photoresist layer may be transferred through the second layer structure (232,242,265,270,72) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form various second layer openings (249,229). The various second layer openings (249,229) can include a second layer memory opening 249 and a second layer support opening 229.

The second layer memory openings 249 are formed directly on the top surface of a respective one of the sacrificial first layer memory opening fill portions 148. The second layer support openings 229 are formed directly on the top surface of a corresponding one of the sacrificial first layer support opening fill portions 128. In addition, each second layer support opening 229 may be formed through horizontal surfaces within the second stepped surfaces, including the interfacial surfaces between the second alternating stacks (232, 242) and the second rearwardly stepped dielectric material portions 265. The location of the steps S in the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) is shown in dashed lines in FIG. 31B.

The second anisotropic etching process may include an etching step in which the material of the second layer alternating stack (232, 242) is etched simultaneously with the material of the second backward stepped dielectric material portion 265. The chemistry of the etching steps may be alternated to optimize etching of the material in the second layer alternating stack (232, 242) while providing an average etch rate comparable to the material of the second backward stepped dielectric material portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF ₄ /O ₂ Ar etch). The sidewalls of the various second layer openings (249,229) can be substantially vertical or can be tapered. The bottom perimeter of each second layer opening (249,229) can be laterally offset and/or can be entirelyPositioned within the perimeter of the top surface of the underlying sacrificial first layer opening fill portion (148,128). The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 32, the sacrificial first layer fill material of the sacrificial first layer opening fill portion (148,128) may be removed using an etching process that etches the sacrificial first layer fill material selective to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating cap layers (170, 270), and the interlayer dielectric layer 180. The memory openings 49 (also referred to as inter-layer memory openings) are formed in each combination of the second layer memory openings 249 and the volumes from which the sacrificial first layer memory opening fill portions 148 are removed. Support openings 19 (also referred to as interlayer support openings 19) are formed in each combination of the second layer support openings 229 and the volume from which the sacrificial first layer support opening fill portions 128 are removed. Each of the memory openings 49 cuts through a longitudinal edge of a respective one of the strips of sacrificial material 183.

Fig. 33A-33D provide sequential cross-sectional views of the memory opening 49 during formation of the memory opening fill structure. The same structural change occurs in each of the memory opening 49 and the support opening 19.

Referring to fig. 33A, a memory opening 49 in the first exemplary device structure of fig. 8 is shown. The memory opening 49 extends through the first layer structure and the second layer structure.

Referring to fig. 33B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a continuous sacrificial spacer material layer 260L may be sequentially deposited in the memory opening 49. Blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks leakage of stored charge to the control gate electrode. In one embodiment, blocking dielectric layer 52 comprises aluminum oxide. Alternatively or in addition, blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling may be performed under suitable electrical bias conditions. Charge tunneling may be performed by hot carrier injection or by fowler-nordheim tunneling induced charge transfer, depending on the mode of operation of the unitary three-dimensional NAND string memory device to be formed. Tunnel dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, tunnel dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. In one embodiment, tunnel dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunnel dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used. The stack of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 forms memory film 50 that stores a memory bit.

A continuous layer 260L of sacrificial spacer material is deposited over the memory film 50. The continuous sacrificial spacer material layer 260L includes a material that is selectively removable with respect to the material of the memory film 50. For example, the continuous sacrificial spacer material layer 260L may include amorphous silicon, a silicon germanium alloy, or amorphous carbon. The continuous sacrificial spacer material layer 260L may be formed by a conformal deposition method such as Low Pressure Chemical Vapor Deposition (LPCVD). The thickness of the continuous sacrificial spacer material layer 260L may be in the range of 2nm to 10nm, although lesser and greater thicknesses may also be used. Memory cavity 49' is stored within each volume of memory opening 49 that is not filled with a deposited material layer (52,54,56,260L).

Referring to fig. 33C, in the event that the memory cavity 49' in each memory opening is not completely filled with the continuous sacrificial spacer material layer 260L, a dielectric core layer may be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method, such as Low Pressure Chemical Vapor Deposition (LPCVD), or by a self-planarizing deposition process, such as spin-on. The horizontal portion of the dielectric core layer overlying the second insulating cap 270 may be removed, for example, by recess etching. Optionally, the recess etch may continue until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

Referring to fig. 33D, a sacrificial fill material may be deposited in the cavity overlying dielectric core 62. The sacrificial fill material comprises a material different from the material of the continuous sacrificial spacer material layer 260L and the second insulating cap 270. For example, the sacrificial fill material may comprise a doped silicate glass, such as borosilicate glass. Portions of the sacrificial fill material, the continuous sacrificial spacer material layer 260L, the tunnel dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of the second insulating cap layer 270) may be removed by a planarization process, such as a Chemical Mechanical Planarization (CMP) process.

In the case of dielectric core 62 having a top surface below a horizontal plane including the top surface of second layer insulating cap layer 270, and if a sacrificial fill material is used, each remaining portion of the sacrificial fill material constitutes a drain level sacrificial post 91. Each remaining portion of the continuous sacrificial spacer material layer 260L constitutes a sacrificial conformal spacer 260. Tunnel dielectric layer 56 is surrounded by charge storage layer 54 and laterally surrounds sacrificial conformal spacers 260. Each set of adjacent blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 collectively comprise a memory film 50 that can store charge with macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the formation of the backside recess. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

Each combination of memory film 50, sacrificial conformal spacers 260, dielectric core 62, and drain region 63 within memory opening 49 constitutes an in-process memory opening fill structure 258. The source level sacrificial layer 104, the first layer structure (132,142,170,165), the second layer structure (232,242,270,265,72), the interlayer dielectric layer 180, and the in-process memory opening fill structure 258 together comprise a memory level assembly.

Referring to fig. 34, a first exemplary structure is shown after the memory opening fill structure 258 is formed. The support post structures 20 are formed in the support openings 19 at the same time as the memory opening fill structures 258 are formed in the process. Each support pillar structure 20 may have the same set of components as the in-process memory opening fill structure 258.

Referring to fig. 35A-35E, a first contact level dielectric layer 280 may be formed over the second layer structure (232,242,270,265,72). The first contact level dielectric layer 280 comprises a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100nm to 600nm, although lesser and greater thicknesses may also be used.

A photoresist layer may be applied over the first contact level dielectric layer 280 and may be lithographically patterned to form elongated openings extending along the first horizontal direction hd1 between clusters of in-process memory opening fill structures 258. The backside trench 79 may be formed by transferring a pattern in a photoresist layer (not shown) through the first contact level dielectric layer 280, the second layer structure (232,242,270,265,72), the laterally alternating sequence of insulating material strips 182 and sacrificial material strips 183 and the interlayer dielectric layer 180, and the first layer structure (132,142,170,165), and into the source level sacrificial layer 104. The laterally alternating sequence of first contact level dielectric layer 280, second layer structure (232,242,270,265,72), first layer structure (132,142,170,165), insulating material strips 182 and sacrificial material strips 183, and portions of interlayer dielectric layer 180 and source level sacrificial layer 104 underlying the openings in the photoresist layer may be removed to form backside trenches 79. In one embodiment, backside trenches 79 may be formed between clusters of in-process memory opening fill structures 258. Clusters of in-process memory opening fill structures 258 may be laterally spaced apart along the second horizontal direction hd2 by backside trenches 79.

Referring to fig. 36A to 36E, a first isotropic etching process may be performed in which a first isotropic etchant is provided into the backside trench 79. The first isotropic etchant etches material of the sacrificial material strips 183 selective to material of the insulating material strips 182 and the interlayer dielectric layer 180, the insulating layer (132, 232), the sacrificial material layer (142, 242), the insulating cap layer (170, 270), and the first and second back step dielectric material portions (165, 265). In one embodiment, if the sacrificial material strips 183 comprise amorphous carbon, the sacrificial material strips 183 may be removed by ashing. In one embodiment, if the sacrificial material strips 183 comprise organosilicate glass or borosilicate glass, a wet etch (which uses hydrofluoric acid) may be used. In one embodiment, if the strips of sacrificial material 183 comprise amorphous undoped silicon or silicon germanium alloy, a wet etch process may be performed to remove the strips of sacrificial material 183 along the longitudinal direction (i.e., the second horizontal direction hd 2) of each strip of sacrificial material 183, the wet etch process using hot trimethyl-2-hydroxyethyl ammonium hydroxide ("hot TMY") or tetramethyl ammonium hydroxide (TMAH). The void created by removing the strip of sacrificial material 183 is referred to herein as a laterally extending cavity 185. The strips of sacrificial material 183 may be selectively removed to the material of the memory film 50. Laterally extending cavities 185 are formed in the volume from which the strips 183 of sacrificial material are removed. In this case, the laterally extending cavity 185 may be laterally defined by the memory film 50 of the in-process memory opening fill structure 258.

Subsequently, at least one second isotropic etching process may be performed by providing at least one second isotropic etchant into the backside trench 79 and into the laterally extending cavity 185. At least one second isotropic etchant etches material portions of the blocking dielectric layer 52, the charge storage layer 54, the tunneling dielectric layer 56, and portions of the sacrificial conformal spacers 260 adjacent the laterally extending cavities 185. The at least one second isotropic etching process may be a sequence of isotropic etching processes. Pit cavities 49P are formed within each of the memory openings 49 in a volume adjacent a respective one of the laterally extending cavities 185. Each removed portion of memory film 50 and sacrificial conformal spacer 260 has a respective side aperture through which dimple cavity 49P extends. Each pocket cavity 49P abuts a respective one of the laterally extending cavities 185. Each laterally extending cavity 185 may abut at least one column of pocket cavities 49 arranged along the second horizontal direction hd 2.

Referring to fig. 37A-37E, a dielectric material such as undoped silicate glass or doped silicate glass may be conformally deposited in the pit cavity 49P, the laterally extending cavity 185, at the peripheral region of the backside trench 79, and over the first contact level dielectric layer 280. In one embodiment, the dielectric material may include undoped silicate glass or doped silicate glass (such as borosilicate glass). An isotropic etch-back process is performed to remove portions of the dielectric material from the peripheral regions of the backside trench 79 and from over the first contact level dielectric layer 280.

Each remaining portion of the dielectric material in the pit cavity 49P constitutes a dielectric plug portion. Each remaining portion of the dielectric material in the laterally extending cavity 185 constitutes a dielectric rail portion. Each successive combination of a dielectric rail portion and a plurality of dielectric plug portions is referred to herein as a dielectric strip 187. Dielectric strips 187 are formed in the laterally extending cavities 185 and in the pocket cavities 49, i.e., the volume from which portions of the memory film 50 and the sacrificial conformal spacers 260 are removed. Thus, each of the dielectric strips 187 includes a dielectric rail portion that fills the volume of one of the sacrificial material strips 183, and includes a dielectric plug portion that protrudes laterally from the dielectric rail portion and is positioned within a column of memory openings 49. Dielectric strip 187 is formed directly on dielectric core 62. The laterally alternating sequence of strips 182 of insulating material finds that the dielectric strips 187 are referred to herein as interlayer insulating assemblies (182,187).

Referring to fig. 38A, an etchant that selectively etches the material of the source-level sacrificial layer 104 for the first alternating stack (132, 142), the second alternating stack (232, 242), the inter-layer dielectric layer 180 and insulating material strip 182, the dielectric strip 187, the first and second insulating cap layers (170, 270), the first contact-level dielectric layer 280, and the sacrificial etch stop liner may be introduced into the backside trench in an isotropic etching process. For example, if source-level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, and the sacrificial etch stop liner comprises silicon oxide, a wet etch process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide ("thermal TMY") or tetramethyl ammonium hydroxide (TMAH) may be used to selectively remove source-level sacrificial layer 104 for the sacrificial etch stop liner. In the event that the surfaces of the lower source layer 112 and the upper source layer 118 are accidentally exposed to thermal TMY or TMAH during the wet etch process, boron atoms in the lower source layer 112 and the upper source layer 118 prevent accidental etching of the lower source layer 112 and/or the upper source layer 118. If source-level sacrificial layer 104 comprises organosilicate glass or borosilicate glass, a wet etch (which uses dilute hydrofluoric acid) may be used. Source cavity 109 is formed in the volume from which source-level sacrificial layer 104 is removed. Each of the in-process memory opening fill structures 258 is physically exposed to the source cavity 109.

Referring to fig. 38B, a sequence of isotropic etchants (such as wet etchants) may be applied to physically exposed portions of memory film 50 to sequentially etch the various component layers of memory film 50 from the outside to the inside and physically expose the cylindrical surfaces of sacrificial conformal spacers 260 at the level of source cavity 109. The sacrificial etch stop liner may be incidentally etched during the removal of the portion of the memory film 50 located at the level of the source cavity 109. The volume of the source cavity 109 may be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the sacrificial etch stop liner. The top surface of the substrate semiconductor layer 10 may be physically exposed to the source cavity 109. Source cavity 109 is formed by isotropically etching a bottom portion of each of source-level sacrificial layer 104 and memory film 50 selective to substrate semiconductor layer 10 and sacrificial conformal spacers 260.

Referring to fig. 39C, a doped semiconductor material having a second conductivity type may be deposited on the physically exposed semiconductor surface around the source cavity 109. The physically exposed semiconductor surfaces include the bottom portions of the outer sidewalls of the sacrificial conformal spacers 260 and the horizontal surfaces of the substrate semiconductor layer 10. In one embodiment, the catalyst may be prepared by selective exo-catalyst A process is followed to deposit a doped semiconductor material of a second conductivity type on the physically exposed semiconductor surface surrounding the source cavity 109. During the selective epitaxy process, semiconductor precursor gases, etchants, and dopant gases may be flowed simultaneously into a process chamber comprising the exemplary structure. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include a hydride of dopant atoms, such as phosphine, arsine, stibine, or diborane. In this case, the selective epitaxial process grows doped monocrystalline semiconductor material having the doping of the second conductivity type from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped monocrystalline semiconductor material forms a source contact layer 114 that may contact sidewalls of the sacrificial conformal spacers 260. The atomic concentration of the dopant of the second conductivity type in the deposited semiconductor material may be 1.0X105/cm ³ Up to 2.0X11021/cm ³ Such as 2.0X11020/cm ³ To 8.0X105/cm ³ 。

The initially formed source contact layer 114 may consist essentially of semiconductor atoms of the second conductivity type and dopant atoms. Optionally, one or more etch back processes may be used in combination with a plurality of selective or non-selective deposition processes to provide a seamless and/or void-free source contact layer 114. In one embodiment, the doped semiconductor material may comprise monocrystalline silicon. Thus, source-level sacrificial layer 104 may be replaced with source contact layer 114. Generally, source-level sacrificial layer 104 is replaced with a source contact layer 114 comprising a doped monocrystalline semiconductor material epitaxially aligned with a monocrystalline semiconductor material layer, such as substrate semiconductor layer 10.

Referring to fig. 38D, an oxidation process may be performed to convert the physically exposed surface portions of the source contact layer 114 into a semiconductor oxide liner 122.

Referring to fig. 39A, sacrificial material layers (142, 242) may be selectively removed for insulating layers (132, 232), interlayer dielectric layer 180, and laterally alternating sequences of insulating material strips 182 and 187, first and second insulating cap layers (170, 270), first contact level dielectric layer 280 and source contact layer 114, and semiconductor oxide liner 122. For example, an etchant that selectively etches the material of the sacrificial material layers (142, 242) may be introduced into the backside trench 79, for example using an isotropic etching process, with respect to the laterally alternating sequence of insulating layers (132, 232), interlayer dielectric layer 180, and insulating material strips 182 and 187, the first and second insulating cap layers (170, 270), the material of the back-step dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50. For example, the sacrificial material layer (142, 242) may comprise silicon nitride, the insulating layer (132, 232), the interlayer dielectric layer 180, and the laterally alternating sequence of insulating material strips 182 and dielectric strips 187, the first and second insulating cap layers (170, 270), the rearwardly stepped dielectric material portions (165, 265), and the outermost material of the memory film 50 may comprise a silicon oxide material.

The isotropic etching process may be a wet etching process using a wet etching solution, or may be a gas phase (dry) etching process in which an etchant is introduced into the backside trench 79 in a gas phase. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etch bath comprising phosphoric acid, the wet etching process etching silicon nitride selective to silicon oxide, silicon, and various other materials used in the art.

A backside recess (143,243) is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recesses (143,243) include a first backside recess 143 formed in the volume from which the first layer of sacrificial material 142 is removed and a second backside recess 243 formed in the volume from which the second layer of sacrificial material 242 is removed. Each of the backside recesses (143,243) can be a laterally extending cavity having a lateral dimension that is greater than a vertical extent of the laterally extending cavity. In other words, each of the backside recesses (143,243) can have a lateral dimension that is greater than a height of the respective backside recess (143,243). A plurality of backside recesses (143,243) can be formed in a volume of material from which the sacrificial material layers (142, 242) are removed. Each of the backside recesses (143,243) can extend substantially parallel to the top surface of the substrate semiconductor layer 10. The backside recess (143,243) can be vertically defined by a top surface of the underlying insulating layer (132, 232) and a bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143,243) can have a uniform height throughout.

Referring to fig. 39B, a backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses (143,243) and backside trenches 79 and over the first contact level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the backside blocking dielectric layer may comprise aluminum oxide. The backside blocking dielectric layer may be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer may be in the range of 1nm to 20nm, such as 2nm to 10nm, although lesser and greater thicknesses may also be used.

At least one conductive material may be deposited in the plurality of backside recesses (143,243), on the sidewalls of the backside trench 79, and over the first contact level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may comprise an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

A conductive layer (146,246) may be formed by depositing at least one conductive material in the backside recess (143,243). A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous layer of metal material (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact level dielectric layer 280. Each of the first and second conductive layers 146 and 246 may include a respective conductive metal nitride liner and a respective conductive filler material. Thus, the first and second layers of sacrificial material (142, 242) may be replaced with first and second conductive layers (146,246), respectively. Specifically, each first layer of sacrificial material 142 may be replaced with an optional portion of a backside blocking dielectric layer and first conductive layer 146, and each second layer of sacrificial material 242 may be replaced with an optional portion of a backside blocking dielectric layer and second conductive layer 246. A backside cavity is present within the portion of each backside trench 79 that is not filled with a continuous layer of metal material.

Residual conductive material may be removed from inside the backside trench 79. In particular, the deposited metal material of the continuous metal material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metallic material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metallic material in the second backside recess constitutes a second conductive layer 246. The sidewalls of the first and second conductive material layers 146 and 79 may be physically exposed to the respective backside trenches. The backside trench may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.

Each conductive layer (146,246) can be a conductive sheet including an opening therein. A first subset of the openings through each conductive layer (146,246) can be filled with an in-process memory opening fill structure 258. A second subset of the openings through each conductive layer (146,246) can be filled with support pillar structures 20. Due to the first and second stepped surfaces, each conductive layer (146,246) can have a smaller area than any underlying conductive layer (146,246). Due to the first and second stepped surfaces, each conductive layer (146,246) can have a larger area than any overlying conductive layer (146,246).

In some embodiments, drain select level isolation structures 72 may be provided at the topmost level of the second conductive layer 246. A subset of the second conductive layers 246 positioned at the level of the drain select level isolation structure 72 constitute a drain select gate electrode. A subset of the conductive layers (146,246) positioned under the drain select gate electrode can be used as a combination of control gates and word lines positioned at the same level.

Each of the memory films 50 includes a vertical stack of memory elements positioned at each level of a conductive layer (146,246). A subset of the conductive layers (146,246) can include word lines for the memory elements.

Referring to fig. 39C, 40A, and 40B, a layer of dielectric material may be conformally deposited in the backside trench 79 and over the first contact level dielectric layer 280 by a conformal deposition process. The layer of dielectric material may comprise, for example, silicon oxide. Each deposited portion of dielectric material in the backside trench 79 constitutes a backside trench fill structure 76, which may be a dielectric wall structure. A horizontal portion of the dielectric material above the top surface of the first contact level dielectric layer 280 may be removed or may be incorporated into the first contact level dielectric layer 280.

Referring to fig. 41A, 41B, and 42, a drain cavity 85 may be formed over each of the in-process memory opening fill structures 258. For example, a photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be patterned with a separate opening overlying the in-process memory opening fill structure 258. An anisotropic etch may be performed to transfer the pattern in the photoresist layer through the first contact level dielectric layer 280. The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 43A-43C, an etching process is performed that etches the material of the sacrificial conformal spacers 260 selective to the material of the memory film 50, the dielectric core 62, the first contact level dielectric layer 280, and the source contact layer 114. The etching process may be an isotropic etching process such as a wet etching process. In one embodiment, the sacrificial conformal spacer 260 can comprise undoped amorphous silicon or a silicon germanium alloy, and the etching process can comprise a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide ("thermal TMY") or tetramethyl ammonium hydroxide (TMAH). The drain level sacrificial post 91 (if present) may be removed.

Channel cavities 259 are formed that include the combined volume of sacrificial conformal spacers 260. Each channel cavity 259 may include a void that includes the volume of the removed sacrificial conformal spacers 260. An annular top surface of the monocrystalline semiconductor material of the source contact layer 114 may be physically exposed at the bottom of each channel cavity 259. Each channel cavity 259 laterally surrounds the dielectric core 62. Each vertically extending portion of the channel cavity 259 may have a uniform lateral width that may be in the range of 10nm to 120nm, such as 20nm to 80nm, although smaller and larger uniform lateral widths may also be used. The dielectric plug portions of the dielectric strips 187 provide structural support to the dielectric cores 62 by fixing the position of each dielectric core 62 relative to the dielectric strips 187 and insulating material strips 182 at the level of the interlayer dielectric layer 180 during and after formation of the channel cavity 159.

Referring to fig. 44, a selective epitaxial process may be performed to grow a doped single crystal semiconductor material having a first conductivity type in the channel cavity 259. For example, the first exemplary structure may be placed in a vacuum sealed selective epitaxial processing chamber and a combination of a semiconductor precursor gas (such as a precursor gas of silane, disilane, dichlorosilane, trichlorosilane, silicon tetrachloride, germanium, or a compound semiconductor material), a dopant gas comprising atoms of an electrical dopant of a first conductivity type (e.g., diborane for a p-type dopant, or phosphine, arsine, or stibine for an n-type dopant), and an etchant gas (such as hydrogen chloride) flowed into the selective epitaxial processing chamber while the first exemplary structure is maintained at an elevated temperature. The elevated temperature may be in the range of 500 degrees celsius to 900 degrees celsius. In-process epitaxial semiconductor channel 60P may be grown upward from the physically exposed semiconductor surface of source contact layer 114 during the selective epitaxial process. The selective epitaxial process grows monocrystalline semiconductor material up through the channel cavity 259 and around each of the dielectric plug portions of the dielectric strip 187. The epitaxial semiconductor channel 60P may fill the entire volume of the channel cavity 259 during processing. The dielectric plug portions of the dielectric strips 187 provide structural support to the dielectric cores 62 by fixing the position of each dielectric core 62 relative to the dielectric strips 187 and insulating material strips 182 at the level of the interlayer dielectric layer 180 during the selective epitaxy process.

The excess portion of monocrystalline semiconductor material grown above the horizontal plane including the top surface of the first contact level dielectric layer 280 may be removed by a planarization process, which may use chemical mechanical planarization. The epitaxial semiconductor channel 60P may be epitaxially aligned with a single crystal semiconductor material layer of the substrate 8 (such as the substrate semiconductor layer 10) through the intermediate single crystal material of the source contact layer 114 in each process.

Referring to fig. 45A through 45C, 46A and 46B, dopants of the second conductivity type may be implanted into an upper portion of the epitaxial semiconductor channel 60P in each process. The upper portion of each implant of epitaxial semiconductor channel 60P is converted into a doped drain region having a second conductivity type during the process. Each remaining lower portion of epitaxial semiconductor channel 60P has a doping of the first conductivity type during the process and constitutes an epitaxial semiconductor channel 60. Drain region 63 may comprise a single crystal doped semiconductor material. The dopant concentration in the drain region 63 may be 5.0x10 ¹⁹ /cm ³ Up to 2.0X10 ²¹ /cm ³ But smaller and larger dopant concentrations may be used.

Each successive combination of memory film 50 and epitaxial semiconductor channel 60 constitutes a memory stack structure 55 that includes a vertical stack of memory elements therein. The vertical stack of memory elements may include portions of a charge storage layer positioned at each level of the conductive layer (146,246). A set of all material portions that fill the memory opening 49 after the formation of the drain region 63 constitute the memory opening filling structure 58. Each memory opening fill structure 58 includes a memory film 50, an epitaxial semiconductor channel 60, a dielectric core 62, a drain region 63, and a dielectric plug portion of a dielectric stripe 187. The epitaxial semiconductor channel 60 is formed directly on and epitaxially aligned with the source contact layer 114.

Referring to fig. 47, the process steps of fig. 23 may be performed to form a first pass-through memory level via structure 488, contact via structures (86, 88), and metal line structures (96, 98).

With reference to all of the figures and in accordance with various embodiments of the present disclosure, there is provided a three-dimensional memory device comprising: the first layers of the first insulating layer 132 and the first conductive layer 146 are alternately stacked, the first layer being positioned above the substrate 8; an interlayer insulating component (182,187) positioned over the first layer alternating stack (132,146) and comprising a plurality of dielectric strips 187, wherein each of the plurality of dielectric strips 187 comprises a dielectric plug portion protruding laterally from a dielectric rail portion; the second layers of the second insulating layer 232 and the second conductive layer 246 are alternately stacked, the second layer being positioned above the interlayer insulating member (182,187); a memory opening 49 extending vertically through the first layer alternating stack (132,146), the interlayer insulating assembly (182,187), and the second layer alternating stack (232,246), wherein each of the memory openings 49 includes a side aperture through which a respective one of the dielectric plug portions extends inwardly; and a memory opening fill structure 58 positioned in a respective one of the memory openings 49 and including a memory film 50, a semiconductor channel, and a dielectric core 62 including a dielectric fill material and abutting a respective one of the dielectric plug portions.

In one implementation, each of the semiconductor channels has a respective annular horizontal cross-sectional shape at a level of the first layer alternating stack (132,146) and at a level of the second layer alternating stack (232,246), and a respective block arc shape at a level of the interlayer insulating component (182,187), i.e., between a first horizontal plane comprising a bottom surface of the interlayer insulating component (182,187) and a second horizontal plane comprising a top surface of the interlayer insulating component (182,187).

In one implementation, each of the memory films 50 has a respective annular horizontal cross-sectional shape at the level of the first layer alternating stack (132,146) and at the level of the second layer alternating stack (232,246), and a respective block arc shape at the level of the interlayer insulating component (182,187).

In one embodiment, each interface between the dielectric core 62 and the dielectric plug portions includes a convex vertical surface of a respective one of the dielectric cores 62 and a concave vertical surface of a respective one of the dielectric plug portions.

In one embodiment, the interlayer insulating assembly (182,187) comprises strips of insulating material 182 interwoven with a plurality of dielectric strips 187, wherein a laterally alternating sequence of the strips 182 of insulating material and the strips 187 of dielectric material alternating along a first horizontal direction hd1 is present between a first layer alternating stack (132,146) and a second layer alternating stack (232,246).

In one implementation, each of the plurality of strips of insulating material 182 contacts two columns of memory opening filling structures 58 extending along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd 1.

In one embodiment, a three-dimensional memory device includes: a back side groove 79 extending vertically through the first layer alternating stack (132,146), the interlayer insulating member (182,187), and the second layer alternating stack (232,246), extending laterally along the first horizontal direction hd1, and having a uniform width along the second horizontal direction hd2 perpendicular to the first horizontal direction hd 1; and a backside trench fill structure 76 positioned in the backside trench 79, wherein each strip within the laterally alternating sequence of insulating material strips 182 and dielectric strips 187 contacts a sidewall of the backside trench fill structure 76.

In one implementation, each of the plurality of dielectric strips 187 has two sets of straight sidewall sections, wherein each set of straight sidewall sections includes a plurality of straight sidewall sections positioned in a respective vertical plane perpendicular to the first horizontal direction hd 1.

In one embodiment, the three-dimensional memory device includes a single crystal semiconductor material layer positioned in or over the substrate 8, wherein the semiconductor channel includes an epitaxial semiconductor channel epitaxially aligned with the single crystal semiconductor material layer. The device further includes a drain region 63 comprising a doped epitaxial semiconductor material that contacts and is epitaxially aligned with an upper end of a respective one of the epitaxial semiconductor channels 60 and contacts a top surface of a respective one of the dielectric cores 62.

In one embodiment, a three-dimensional memory device includes: a source contact layer 114 comprising doped monocrystalline semiconductor material and contacting and epitaxially aligning the monocrystalline semiconductor material layer and the epitaxial semiconductor channel 60. In one implementation, the source contact layer 114 contacts and laterally surrounds each of the dielectric cores 62.

In one embodiment, each interface between source contact layer 114 and epitaxial semiconductor channel 60 includes an annular convex tapered surface of source contact layer 114 and an annular concave tapered surface of a respective one of epitaxial semiconductor channel 60.

In one embodiment, epitaxial semiconductor channel 60 comprises a material selected from monocrystalline silicon, monocrystalline silicon germanium alloy, or monocrystalline group III-V compound semiconductor material; and the plurality of dielectric strips 187 comprise a material selected from undoped silicate glass, doped silicate glass, or organosilicate glass.

In one embodiment, the second exemplary structure may include dielectric plugs 62G of the first exemplary structure in addition to dielectric plugs of dielectric strips 187 positioned in the interlayer insulating assembly to provide additional support to the semiconductor channel and dielectric core 62.

The dielectric plugs of the first and/or second exemplary structures provide support to the semiconductor channel and the dielectric core 62 to prevent them from collapsing during the fabrication steps (e.g., during formation of the backside recesses 43).

Various epitaxial monocrystalline semiconductor channels (e.g., monocrystalline silicon channels) of some embodiments of the present disclosure provide higher charge carrier mobility relative to polycrystalline semiconductor channels. In addition, the epitaxial semiconductor channel 60 of embodiments of the present disclosure is formed in a tubular configuration, and thus may be formed with a lateral thickness small enough to provide complete depletion of charge carriers within the epitaxial semiconductor channel 60 when the epitaxial semiconductor channel 60 is turned off. Thus, the epitaxial semiconductor channel 60 of embodiments of the present disclosure may provide high conduction current and low leakage current for a NAND string, thereby enhancing performance of a three-dimensional memory device including the NAND string. However, in alternative embodiments, the semiconductor channel may be polycrystalline, such as a polysilicon channel.

Referring to fig. 48A and 48B, a third exemplary structure according to a third embodiment of the present disclosure is shown. The third exemplary structure includes a substrate 908 having a higher substrate portion 910. The substrate 908 may be a semiconductor substrate, such as a commercially available monocrystalline silicon wafer. In this case, the upper substrate portion 910 may include a top portion of a silicon wafer, a doped well, and/or an epitaxial silicon layer comprising a single crystal semiconductor (e.g., silicon) material that is carbon-free or contains carbon. As used herein, a structure is "free of carbon" if the atomic concentration of carbon within the structure is below trace levels of atomic concentration (such as less than 0.1 ppm).

The lower semiconductor layer 212 may be formed on the upper substrate portion 910. In one embodiment, the lower semiconductor layer 212 may be formed by ion implantation or diffusion of a p-type dopant (e.g., boron) and optionally carbon into an upper portion of the upper substrate portion 910. Alternatively, a layer of monocrystalline semiconductor (e.g., silicon) material doped in situ with boron and optionally carbon may be deposited on the top surface of the upper substrate portion 910 to form the lower semiconductor layer 212. Preferably, the p-type dopant in the lower semiconductor layer 212 includes boron atoms. In this case, the lower semiconductor layer 212 may include a carbon and boron doped semiconductor material, which is referred to herein as a first boron doped semiconductor material. In one embodiment, the first boron-doped semiconductor material comprises a doped monocrystalline semiconductor material that is epitaxially aligned with the monocrystalline semiconductor material of the substrate 908 (i.e., the monocrystalline semiconductor material of the upper substrate portion 910).

In one embodiment, the first boron-doped semiconductor material may include an atomic concentration of 1.0X10 ¹⁸ /cm ³ Up to 2.0X10 ²¹ /cm ³ Boron atoms in the range of (2). In one embodiment, the first boron-doped semiconductor material of the lower semiconductor layer 212 may comprise single crystal silicon doped with boron atoms and carbon atoms. In one embodiment, the first boron-doped semiconductor material may include an atomic concentration of 1.0X10 ¹³ /cm ³ Up to 1.0X10 ¹⁹ /cm ³ Carbon atoms in the range of (2). The thickness of the lower semiconductor layer 212 may be in the range of 50nm to 400nm, such as 100nm to 300nm, although lesser and greater thicknesses may also be employed.

A lower etch stop dielectric liner 103 may be formed on the top surface of the lower semiconductor layer 212. The lower etch stop dielectric liner 103 comprises a dielectric material that can be used as an etch stop material during subsequent removal of the sacrificial material. For example, the lower etch stop dielectric liner 103 may comprise silicon oxide. The lower etch stop dielectric liner 103 may be formed by thermal oxidation or plasma oxidation of a surface portion of the lower semiconductor layer 212. The lower etch stop dielectric liner 103 may have a thickness in the range of 2nm to 10nm, but smaller and larger thicknesses may also be employed.

Sacrificial source level material may be deposited over the lower etch stop dielectric liner 103 to form a sacrificial source level material layer. The sacrificial source level material layer comprises a material that is selectively removable for the lower etch stop dielectric liner 103. For example, the sacrificial source level material layer may comprise undoped amorphous silicon, undoped polysilicon, amorphous carbon, organosilicate glass, or a polymeric material. In one embodiment, the sacrificial source-level material layer comprises undoped amorphous silicon or polysilicon. The sacrificial source level material layer may have a uniform thickness throughout, which may be in the range of 20nm to 300nm, such as 50nm to 150nm, although lesser and greater thicknesses may also be employed.

A higher etch stop dielectric liner 107 may be formed on the sacrificial source level material layer. The higher etch stop dielectric liner 107 comprises a dielectric material that is selective to an etching process that is subsequently used to remove the sacrificial source level material layer. In one embodiment, the higher etch stop dielectric liner 107 may comprise silicon oxide. The thickness of the higher etch stop dielectric liner 107 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be employed.

The upper semiconductor layer 218 may be formed over the upper etch stop dielectric liner 107 by depositing a polycrystalline or amorphous semiconductor material having p-type doping and including carbon atoms. In one embodiment, the p-type dopant in the higher semiconductor layer 218 may include boron atoms. In this case, the higher semiconductor layer 218 may comprise a boron doped semiconductor material, referred to herein as a second boron doped semiconductor material.

In one embodiment, the second boron-doped semiconductor material may include an atomic concentration of 1.0X10 ¹⁸ /cm ³ Up to 2.0X10 ²¹ /cm ³ Boron atoms in the range of (2). In one embodiment, the second boron doped semiconductor material of the higher semiconductor layer 218 may comprise polysilicon or amorphous silicon doped with boron atoms and carbon atoms. In one embodiment, the second boron-doped semiconductor material may include an atomic concentration of 1.0X10 ¹⁵ /cm ³ Up to 1.0X10 ¹⁹ /cm ³ Carbon atoms in the range of (2). The thickness of the higher semiconductor layer 218 may be in the range of 20nm to 400nm, such as 50nm to 200nm, although lesser and greater thicknesses may also be employed.

The stack of layers of the lower semiconductor layer 212, the lower etch stop dielectric liner 103, the sacrificial source level material layer, the higher etch stop dielectric liner 107, and the higher semiconductor layer 218 is referred to herein as an in-process source level material layer 110', which is subsequently modified to provide a source level material layer. The exemplary structure includes a memory array region 100 in which a memory device array will be formed later, a stair region 200 in which alternating stacked stair-step surfaces of insulating and conductive layers will be formed later, and a peripheral region 400 from which layers within the alternating stacks of insulating and conductive layers are removed. Optionally, the in-process source-level material layer 110' may be lithographically patterned to form openings in the peripheral region 400 and at least one optional opening within the memory array region 100. In this case, dielectric material may be deposited in the regions from which portions of the source-level material layer 110' are removed to provide dielectric isolation structures (not shown).

Generally, in-process source level material layer 110' includes lower semiconductor layer 212, optionally lower etch stop dielectric liner 103, sacrificial source level material layer, optionally higher etch stop dielectric liner 107, and higher semiconductor layer 218.

Referring to fig. 49, an alternating stack of first material layers and second material layers is then formed. Each first material layer may comprise a first material, and each second material layer may comprise a second material different from the first material. In the case where at least another alternating stack of material layers is subsequently formed over the alternating stack of first material layers and second material layers, the alternating stack is referred to herein as a first layer alternating stack. The first layer of the alternating stack of layers is referred to herein as the first layer of layers, and the layer of the alternating stack to be subsequently formed directly above the first layer of layers is referred to herein as the second layer of layers, and so on.

The first layer alternating stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced with a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure has been described using embodiments in which the sacrificial material layer is replaced with a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are expressly contemplated herein.

In one embodiment, the first and second material layers may be the first insulating layer 132 and the first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the source-level material layers 110' in the process. As used herein, "sacrificial material" refers to material that is removed during subsequent processing steps.

The first layer alternating stack (132, 142) may include a first insulating layer 132 composed of a first material, and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced with a conductive electrode, which may be used as a control gate electrode for a vertical NAND device, for example. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for a CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and first sacrificial material layer 142 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although more repetitions may be used. In one embodiment, each first sacrificial material layer 142 in the alternating first layer stack (132, 142) may have a substantially constant uniform thickness within each respective first sacrificial material layer 142.

A first insulating cap layer 170 is then formed over the first alternating stack (132, 142). The first insulating cap layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating cap layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating cap layer 170 may be in the range of 20nm to 300nm, but smaller and larger thicknesses may also be used.

Referring to fig. 50, the first insulating cap layer 170 and the first layer alternating stack (132, 142) may be patterned to form a first stepped surface in the stair-section 200. The stair region 200 may include respective first stepped regions in which a first stepped surface is formed and second stepped regions in which additional stepped surfaces are subsequently formed in a second layer structure (which is subsequently formed over the first layer structure) and/or an additional layer structure. The first stepped surface may be formed, for example, by forming a mask layer (not shown) having openings therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively expanding the etched region, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair positioned directly below the bottom surface of the etched cavity within the etched region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity overlying the first stepped surface is referred to herein as a first stepped cavity.

An interlayer dielectric layer 180 may optionally be deposited over the first layer structure (132,142,170,165). The interlayer dielectric layer 180 includes a dielectric material such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may include doped silicate glass having a greater etch rate than the material of the first insulating layer 132 (which may include undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

Referring to fig. 51A and 51B, various first layer openings (149,129) can be formed through the interlayer dielectric layer 180 and the first layer structure (132,142,170,165) and into the in-process source-level material layer 110'. The first layer opening (149,129) can extend vertically into an upper portion of the lower semiconductor layer 212 outside the region of the sacrificial recessed trench fill portion 104A. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be lithographically patterned to form various openings therethrough. The pattern of openings in the photoresist layer may be transferred through the interlayer dielectric layer 180 and the first layer structure (132,142,170,165) by a first anisotropic etching process and into the in-process source-level material layer 110' to simultaneously (i.e., during the first isotropic etching process) form various first layer openings (149,129). Various first layer openings (149,129) can include a first layer reservoir opening 149 and a first layer support opening 129. The position of the steps S in the first alternating stack (132, 142) is shown in dashed lines in fig. 51B.

The first layer support openings 129 are openings formed in the stairway area 200 and subsequently used to form the support column structure. A subset of the first layer support openings 129 formed through the first rearwardly stepped dielectric material portion 165 may be formed through a corresponding horizontal surface of the first stepped surface.

In one embodiment, the terminal portion of the first anisotropic etch process may etch through the source select level conductive layer, the source level insulating layer 117, the upper semiconductor layer 218, the upper etch stop dielectric liner 107, the sacrificial source level material layer, and the lower etch stop dielectric liner 103, and at least partially into the lower semiconductor layer 212. The terminal portion of the first anisotropic etching process may contain at least one etching chemistry for the various semiconductor materials of the source-level material layer 110' during etching. The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 52, a sacrificial first layer opening filling portion (148,128) may be formed in various first layer openings (149,129). For example, a sacrificial first layer fill material is deposited simultaneously in each of the first layer openings (149,129). The sacrificial first layer fill material includes a material that is subsequently removable selective to the material of the first insulating layer 132 and the first sacrificial material layer 142.

In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the materials of the first insulating layer 132, the first insulating cap layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may comprise borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times greater than the etch rate of dense TEOS oxide in 100:1 diluted hydrofluoric acid (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densification in an annealing process). In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1nm to 3 nm) may be used prior to depositing the sacrificial first layer fill material. The sacrificial first layer of filler material may be formed by non-conformal deposition or conformal deposition methods.

Referring to fig. 53, a second layer structure may be formed over the first layer structure (132,142,170,148). The second layer structure may comprise an additional alternating stack of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers may then be formed on a top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes alternating third and fourth pluralities of material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

In one embodiment, the third material layer may be the second insulating layer 232 and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be removed selective to the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as a control gate electrode for a vertical NAND device, for example.

In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second alternating stack (232, 242) may include alternating pluralities of second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by Chemical Vapor Deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or Atomic Layer Deposition (ALD).

The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be removed selective to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

The thickness of the second insulating layer 232 and the second sacrificial material layer 242 may be in the range of 20nm to 50nm, but smaller and larger thicknesses may be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and second sacrificial material layer 242 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although more repetitions may be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) may have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

A second insulating cap layer 270 may then be formed over the second alternating stack (232, 242). The second insulating cap 270 includes a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating cap layer 270 may comprise silicon oxide. In one embodiment, the first and second layers of sacrificial material (142, 242) may comprise silicon nitride.

Generally, at least one alternating stack of insulating layers (132, 232) and spacer material layers, such as sacrificial material layers (142, 242), may be formed over the source-level material layers 110' in the process, and at least one backward stepped dielectric material portion (165, 265) may be formed over a stair-section on the at least one alternating stack (132,142,232,242).

Optionally, drain select level isolation structures 72 may be formed through a subset of layers in an upper portion of the second layer alternating stack (232, 242). The second sacrificial material layer 242 cut by the drain select level isolation structures 72 corresponds to the level at which the drain select level conductive layer is subsequently formed. The drain select level isolation structure 72 comprises a dielectric material, such as silicon oxide. The drain select level isolation structures 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd 1. The combination of the second alternating stack (232, 242), the second backward stepped dielectric material portion 265, the second insulating cap 270 and the optional drain select level isolation structure 72 together constitute a second layer structure (232,242,265,270,72).

Referring to fig. 54A and 54B, various second layer openings (249,229) may be formed through the second layer structure (232,242,265,270,72). A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be lithographically patterned to form various openings therethrough. The pattern of openings may be the same as the pattern of the various first layer openings (149,129), which is the same as the sacrificial first layer opening fill portions (148,128). Thus, the photoresist layer may be patterned using a photolithographic mask for patterning the first layer openings (149,129).

The second layer memory openings 249 are formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening fill portions 148. The second layer support openings 229 are formed directly on the top surface of a corresponding one of the sacrificial first layer support opening fill portions 128. In addition, each second layer support opening 229 may be formed through horizontal surfaces within the second stepped surfaces, including the interfacial surfaces between the second alternating stacks (232, 242) and the second rearwardly stepped dielectric material portions 265. The location of the steps S in the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) is shown in dashed lines in FIG. 54B.

The second anisotropic etching process may include an etching step in which the material of the second layer alternating stack (232, 242) is etched simultaneously with the material of the second backward stepped dielectric material portion 265. The chemistry of the etching steps may be alternated to optimize etching of the material in the second layer alternating stack (232, 242) while providing an average etch rate comparable to the material of the second backward stepped dielectric material portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF ₄ /O ₂ Ar etch). The sidewalls of the various second layer openings (249,229) can be substantially vertical or can be tapered. The bottom perimeter of each second layer opening (249,229) can be laterally offset and/or can be positioned entirely within the perimeter of the top surface of the underlying sacrificial first layer opening fill portion (148,128). The photoresist layer may then be removed, for example, by ashing.

Referring to fig. 55, the sacrificial first layer fill material of the sacrificial first layer opening fill portion (148,128) may be removed using an etching process that etches the sacrificial first layer fill material selective to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating cap layers (170, 270), and the interlayer dielectric layer 180. The memory openings 49 (also referred to as inter-layer memory openings) are formed in each combination of the second layer memory openings 249 and the volumes from which the sacrificial first layer memory opening fill portions 148 are removed. Support openings 19 (also referred to as interlayer support openings 19) are formed in each combination of the second layer support openings 229 and the volume from which the sacrificial first layer support opening fill portions 128 are removed.

Fig. 56A-56D provide sequential cross-sectional views of the memory opening 49 during formation of the memory opening fill structure. The same structural change occurs in each of the memory opening 49 and the support opening 19.

Referring to fig. 56A, a memory opening 49 in the third exemplary device structure of fig. 55 is shown. The memory opening 49 extends through the first layer structure and the second layer structure.

Referring to fig. 56B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 360L may be sequentially deposited in the memory opening 49. Blocking dielectric layer 52 may comprise a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, blocking dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks leakage of stored charge to the control gate electrode. In one embodiment, blocking dielectric layer 52 comprises aluminum oxide. Alternatively or in addition, blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

The semiconductor channel material layer 360L comprises a p-type semiconductor material, such as at least one elemental semiconductor material, at least one group III-V compound semiconductor material, at least one group II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 360L may have uniform doping. In one embodiment, the semiconductor channel material layer 360L has a p-type doping, wherein the p-type dopant (such as boron atoms) is at 1.0X10 ¹² /cm ³ Up to 1.0X10 ¹⁸ /cm ³ Such as 1.0 x 10 ¹⁴ /cm ³ Up to 1.0X10 ¹⁷ /cm ³ Atomic concentrations within the range exist. In one embodiment, semiconductor channel material layer 360L comprises and/or consists essentially of boron doped amorphous silicon or boron doped polysilicon. The thickness of the semiconductor channel material layer 360L may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. A cavity 49' is formed in the volume of each reservoir opening 49 that is not filled with the deposited material layer (52,54,56,360L).

Referring to fig. 56C, in the event that the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 360L, a dielectric core layer may be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method, such as Low Pressure Chemical Vapor Deposition (LPCVD), or by a self-planarizing deposition process, such as spin-on. The horizontal portion of the dielectric core layer overlying the second insulating cap layer 270 may be removed, for example, by recess etching. The recess etch continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

Referring to fig. 56D, n-type doped semiconductor material may be deposited in the cavity overlying dielectric core 62. Portions of the deposited doped semiconductor material, semiconductor channel material layer 360L, tunnel dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of second insulating cap layer 270) may be removed by a planarization process, such as a Chemical Mechanical Planarization (CMP) process.

Each remaining portion of n-doped semiconductor material constitutes a drain region 63. The dopant concentration of the n-type dopant in the drain region 63 may be 5.0x10 ¹⁹ /cm ³ Up to 2.0X10 ²¹ /cm ³ But smaller and larger dopant concentrations may be used. The doped semiconductor material may be, for example, doped polysilicon.

Each remaining portion of the semiconductor channel material layer 360L constitutes a vertical semiconductor channel 360 through which current can flow when a vertical NAND device including the vertical semiconductor channel 360 is turned on. Tunnel dielectric layer 56 is surrounded by charge storage layer 54 and laterally surrounds vertical semiconductor channel 360. Each set of adjacent blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 collectively comprise a memory film 50 that can store charge with macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the formation of the backside recess. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

Each combination of memory film 50 and vertical semiconductor channel 360 (which is a vertical semiconductor channel) within memory opening 49 constitutes a memory stack structure 55. Memory stack structure 55 is a combination of vertical semiconductor channel 360, tunneling dielectric layer 56, a plurality of memory elements including portions of charge storage layer 54, and optional blocking dielectric layer 52. Each combination of memory stack structure 55, dielectric core 62, and drain region 63 within memory opening 49 constitutes a memory opening fill structure 58. In-process source level material layer 110', first layer structure (132,142,170,165), second layer structure (232,242,270,265,72), interlayer dielectric layer 180, and memory opening fill structure 58 collectively comprise a memory level assembly.

Referring to fig. 57, a third exemplary structure is shown after forming the memory opening filling structure 58. The support post structures 20 are formed in the support openings 19 at the same time as the memory opening fill structures 58 are formed. Each support pillar structure 20 may have the same set of components as the memory opening filling structure 58.

Referring to fig. 58A and 58B, a first contact level dielectric layer 280 may be formed over the second layer structure (232,242,270,265,72). The first contact level dielectric layer 280 comprises a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100nm to 600nm, although lesser and greater thicknesses may also be used.

A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be lithographically patterned to form discrete openings in the regions of the memory array region 100 where the memory opening fill structures 58 are not present. An anisotropic etch may be performed to form vertical interconnect area cavities 585 having substantially vertical sidewalls extending through the first contact level dielectric layer 280, and a second layer structure (232,242,270,265,72) and a first layer structure (132,142,170,165) may be formed below the openings in the photoresist layer. The top surface of the lower level metal interconnect structure 780 may be physically exposed at the bottom of each vertical interconnect area cavity 585. The photoresist layer may be removed, for example, by ashing.

Referring to fig. 59, a dielectric material such as silicon oxide may be deposited in the vertical interconnect area cavity 585 by a conformal deposition process (such as low pressure chemical vapor deposition) or a self-planarizing deposition process (such as spin-on). Excess portions of the deposited dielectric material may be removed from over the top surface of the first contact level dielectric layer 280 by a planarization process. The remaining portion of the dielectric material in the vertical interconnect area cavity 585 constitutes the interconnect area dielectric fill material portion 584.

Referring to fig. 60A and 60B, a photoresist layer may be applied over the first contact level dielectric layer 280 and may be lithographically patterned to form elongated openings extending along the first horizontal direction hd1 between clusters of memory opening filling structures 58. The backside trench 79 may be formed by transferring a pattern in a photoresist layer (not shown) through the first contact level dielectric layer 280, the second layer structure (232,242,270,265,72) and the first layer structure (132,142,170,165) and into the in-process source level material layer 110'. The first contact level dielectric layer 280, the second layer structure (232,242,270,265,72), the first layer structure (132,142,170,165), and portions of the in-process source level material layer 110' below the openings in the photoresist layer may be removed to form the backside trench 79. In one embodiment, backside trenches 79 may be formed between clusters of memory stack structures 55. The clusters of memory stack structures 55 may be laterally spaced apart along the second horizontal direction hd2 by backside trenches 79.

The higher semiconductor layer 218 may serve as an endpoint detection layer during the anisotropic etching process that forms the backside trench. In one embodiment, the anisotropic etching process may include an etching step that etches material of the alternating stacks (32, 42) selective to doped semiconductor material of the higher semiconductor layer 218. Subsequently, the upper semiconductor layer 218 may be etched by employing the upper etch stop dielectric liner 107 as an etch stop layer. The higher etch stop dielectric liner 107 may then be etched by employing an etch chemistry selective to the material of the sacrificial source level material layer. The backside trench 79 is formed in a region in which the sacrificial recessed trench fill portion 104A is present. The sacrificial recessed trench fill portion 104A provides protection against process variations in which the depth of the backside trench 79 exceeds a target depth. In particular, the additional thickness of the sacrificial source-level material layer provided by the sacrificial recessed trench fill portion 104A prevents the bottom portion of the backside trench 79 from extending into the lower semiconductor layer 212. Generally, each backside trench 79 may be formed through the alternating stack (32, 42) such that a bottom surface of each backside trench 79 is formed within a region of a recessed trench in the lower semiconductor layer 212. A bottom surface of each backside trench 79 may be formed between a top surface of the sacrificial source-level material layer and a recessed surface of the lower semiconductor layer 212.

Referring to fig. 61 and 62A, a backside trench spacer 74 may be formed on a sidewall of each backside trench 79. For example, a conformal spacer material layer may be deposited in the backside trench 79 and over the first contact level dielectric layer 280, and may be anisotropically etched to form the backside trench spacers 74. The backside trench spacers 74 comprise a material different from the material of the sacrificial source level material layer. For example, the backside trench spacers 74 may comprise silicon nitride.

Referring to fig. 62B, an etchant that selectively etches the material of the sacrificial source level material layer for the material of the first alternating stack (132, 142), the second alternating stack (232, 242), the first and second insulating cap layers (170, 270), the first contact level dielectric layer 280, the higher etch stop dielectric liner 107, and the lower etch stop dielectric liner 103 may be introduced into the backside trench in an isotropic etching process. For example, if the sacrificial source level material layer comprises undoped polysilicon, undoped amorphous silicon, or an undoped amorphous silicon germanium alloy, the backside trench spacers 74 comprise silicon nitride, and the upper and lower etch stop liners (107,103) comprise silicon oxide, a wet etch process using thermal trimethyl-2-hydroxyethylammonium hydroxide ("thermal TMY") or tetramethylammonium hydroxide (TMAH) may be used to remove the sacrificial source level material layer selective to the backside trench spacers 74 and the upper and lower etch stop liners (107,103). Source cavities 109 are formed in the volume from which the sacrificial source-level material layers are removed.

Wet etch chemistries such as thermal TMY and TMAH selectively etch undoped silicon compared to boron doped silicon materials such as the boron doped silicon material of the higher semiconductor layer 218 and/or the lower semiconductor layer 212. Thus, the use of selective wet etch chemistries such as thermal TMY and TMAH in the wet etch process to form the source cavity 109 provides a larger process window that resists variations in etch depth during the formation of the backside trench 79. In particular, in forming source cavity 109 and/or backside trench spacer 74, even if the sidewalls of higher semiconductor layer 218 are physically exposed or even if the surface of lower semiconductor layer 212 is physically exposed, the collateral etching of higher semiconductor layer 218 and/or lower semiconductor layer 212 is minimal and structural changes in the third exemplary structure caused by accidental physical exposure of the surfaces of higher semiconductor layer 218 and/or lower semiconductor layer 212 during the manufacturing steps do not result in device failure. Each of the memory opening fill structures 58 is physically exposed to the source cavity 109. Specifically, each of the memory opening fill structures 58 includes sidewalls and a bottom surface that are physically exposed to the source cavity 109.

Referring to fig. 62C, a sequence of isotropic etchants (such as wet etchants) may be applied to physically exposed portions of memory film 50 to sequentially etch the various component layers of memory film 50 from the outside to the inside and physically expose the cylindrical surfaces of vertical semiconductor channels 360 at the level of source cavity 109. The upper and lower etch stop liners (107,103) may be incidentally etched during the removal of the portion of the memory film 50 that is positioned at the level of the source cavity 109. The lower etch stop dielectric liner 103, the higher etch stop dielectric liner 107, and the portions of the memory film 50 physically exposed to the source cavity 109 are removed such that the sidewalls of the vertical semiconductor channels 360 are physically exposed. The volume of the source cavity 109 may be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower etch stop liners (107,103). The top surface of the lower semiconductor layer 212 and the bottom surface of the upper semiconductor layer 218 may be physically exposed to the source cavity 109. The source cavity 109 is extended by isotropically etching the sacrificial source-level material layer and the bottom portion of each memory film 50 selective to at least one source-level semiconductor layer, such as the lower semiconductor layer 212 and the upper semiconductor layer 218, and the vertical semiconductor channel 360.

Each remaining portion of the memory film 50 that remains under the source cavity 109 constitutes a dielectric cap structure 150. The dielectric cap structure 150 is embedded within the lower semiconductor layer 212 below the source cavity 109 and surrounds and contacts a respective one of the vertical semiconductor channels 360. In one embodiment, each of the memory films 50 includes a first layer stack including the charge storage layer 54 and the tunneling dielectric 56, and each of the dielectric cap structures 150 includes a second layer stack including a dielectric material layer 154 having the same thickness and the same material composition as the charge storage layer 54, and another dielectric material layer 156 having the same thickness and the same material composition as the tunneling dielectric 56. In one embodiment, the first layer stack may include a blocking dielectric 52, and the second layer stack may include a further dielectric layer 152 having the same thickness and the same material composition as the blocking dielectric 52.

Referring to fig. 62D, semiconductor material may be deposited on the physically exposed semiconductor surfaces around the source cavity 109. The physically exposed semiconductor surfaces include a bottom portion of the outer sidewalls of the vertical semiconductor channel 360 and a horizontal surface of at least one source-level semiconductor layer (such as a bottom surface of the higher semiconductor layer 218 and/or a top surface of the lower semiconductor layer 212). For example, the physically exposed semiconductor surfaces may include a bottom portion of the outer sidewalls of the vertical semiconductor channel 360, the physically exposed surface of the lower semiconductor layer 212, and the bottom surface of the upper semiconductor layer 218.

In one embodiment, semiconductor material may be deposited on the physically exposed semiconductor surfaces surrounding the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, the semiconductor precursor gas, the etchant, and optionally the dopant gas may be flowed simultaneously into the process chamber including the third exemplary structure. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include a hydride of p-type dopant atoms, such as diborane. In this case, the selective semiconductor deposition process grows p-type semiconductor material from the physically exposed semiconductor surfaces surrounding the source cavity 109. The deposited doped semiconductor material forms a source contact layer 214 that may contact the sidewalls of vertical semiconductor channel 360. The atomic concentration of the p-type dopant in the deposited semiconductor material may be 1.0X10 ¹⁴ /cm ³ Up to 2.0X10 ²¹ /cm ³ Such as 1.0X10 ¹⁸ /cm ³ To 5.0X10 ²⁰ /cm ³ 。

In one embodiment, the source contact layer 214 may be deposited as an intrinsic semiconductor material into which boron atoms and carbon atoms diffuse from the lower semiconductor layer 212 and from the upper semiconductor layer 218. In another embodiment, the source contact layer 214 may be deposited within an in-situ p-type doping such that boron atoms merge from the dopant gas into the source contact layer 214, and carbon atoms and additional boron atoms diffuse into the source contact layer 214 from the lower semiconductor layer 212 and from the upper semiconductor layer 218. In yet another embodiment, the source contact layer 214 may be within the in situ carbon doping and deposited by in situ p-type doping such that carbon atoms and boron atoms merge from the dopant gas into the source contact layer 214 and carbon atoms and additional boron atoms diffuse from the lower semiconductor layer 212 and from the upper semiconductor layer 218 into the source contact layer 214. Thus, the source contact layer 214 may include semiconductor atoms, in-situ doped and/or diffused boron atoms, and in-situ doped and/or diffused carbon.

Alternatively, the source contact layer 214 may be formed using at least one non-selectively doped semiconductor material deposition process instead of a selective semiconductor material deposition process. The material composition of the source contact layer 214 in this case may be the same as in the case of a selective semiconductor material deposition process. Optionally, one or more etch back processes may be used in combination with a plurality of selective or non-selective deposition processes to provide a seamless and/or void-free source contact layer 214. The source contact layer 214 is formed directly on the sidewalls of the vertical semiconductor channels 360 in the source cavity 109.

The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 214 in addition to covering the volume of the recessed trench in the lower semiconductor layer 212. The source contact layer 214 may contact a bottom portion of the outer sidewall of the backside trench spacer 74. In one embodiment, the source contact layer 214 may be formed by selectively depositing a p-type from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may comprise doped polysilicon.

Thus, the sacrificial source level material layer may be replaced by the source contact layer 214. The layer stack including the lower semiconductor layer 212, the source contact layer 214, and the upper semiconductor layer 218 constitutes the source-level material layer 110. In one embodiment, vertical semiconductor channel 360 comprises a p-type semiconductor material, and source contact layer 214 may be formed by conformally depositing a third p-type semiconductor material within source cavity 109. In this case, the atomic concentration of boron atoms in the source contact layer 214 may be less than the atomic concentration of boron atoms in the higher semiconductor layer 218 and/or the lower semiconductor layer 212 to reduce boron diffusion into the vertical semiconductor channel 360.

In one embodiment, each of the vertical semiconductor channels 360 includes a p-type semiconductor material having a lower concentration of boron atoms than the source contact layer 214. In one embodiment, the source contact layer 214 includes an epitaxial semiconductor material portion 214E that is epitaxially aligned with the monocrystalline semiconductor material of the substrate 908 by the doped monocrystalline semiconductor material of the lower semiconductor layer 212. The source contact layer 214 may also include a portion of polycrystalline semiconductor material formed by the growth of polycrystalline semiconductor material from the surfaces of the upper semiconductor layer 218 and the vertical semiconductor channel 360. During the growth of the source contact layer 214, carbon atoms may diffuse out into the source contact layer 214 from the lower semiconductor layer 212 and the upper semiconductor layer 218 and into the vertical semiconductor channel 360. Each of the vertical semiconductor channels 360 may have a bottom portion with a graded carbon dopant concentration that decreases with distance from the source contact layer 214. Generally, the sacrificial source level material layer is replaced with a source contact layer 214 comprising boron doped semiconductor material, and if desired, an anneal may be performed to diffuse boron into the material at the bottom of the backside trench 79 to form one or more dense boron doped polysilicon regions.

Referring to fig. 62E, an optional semiconductor oxide liner 122 may be formed at the bottom of each backside trench 79, for example, by thermal oxidation of the semiconductor material of the physically exposed surface portion of the source contact layer 214. Each semiconductor oxide liner 122 may have a thickness in the range of 3nm to 30nm, although lesser and greater thicknesses may also be employed. Alternatively, the semiconductor oxide liner 122 may be omitted if a dense boron doped polysilicon region is formed in a previous step.

Referring to fig. 63, an isotropic etching process may be used to remove the backside trench spacers 74 selective to the insulating layer (132, 232), the first and second insulating cap layers (170, 270), the first contact level dielectric layer 280, and the semiconductor oxide liner 122. For example, if the backside trench spacers 74 comprise silicon nitride, a wet etch process using hot phosphoric acid may be performed to remove the backside trench spacers 74. In one embodiment, the isotropic etch process to remove the backside trench spacers 74 may be combined with a subsequent isotropic etch process that etches the sacrificial material layer (142, 242) selective to the insulating layer (132, 232), the first and second insulating cap layers (170, 270), the first contact level dielectric layer 280, and the semiconductor oxide liner 122.

Referring to fig. 64, the sacrificial material layer (142, 242) may be selectively removed with respect to the insulating layer (132, 232), the first and second insulating cap layers (170, 270), the first contact level dielectric layer 280, and the source contact layer 214, the semiconductor oxide liner 122, and the annular dielectric semiconductor oxide spacers. For example, an etchant that selectively etches the material of the sacrificial material layer (142, 242) may be introduced into the backside trench 79, for example, using an isotropic etching process, relative to the material of the insulating layer (132, 232), the first and second insulating cap layers (170, 270), the back-step dielectric material portion (165, 265), and the outermost layer of the memory film 50. For example, the sacrificial material layer (142, 242) may comprise silicon nitride, and the material of the insulating layer (132, 232), the first and second insulating cap layers (170, 270), the portion of the rearwardly stepped dielectric material (165, 265), and the outermost layer of the memory film 50 may comprise a silicon oxide material.

The isotropic etching process may be a wet etching process using a wet etching solution, or may be a gas phase (dry) etching process in which an etchant is introduced into the backside trench 79 in a gas phase. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process may be a wet etching process in which the third exemplary structure is immersed in a wet etch bath comprising phosphoric acid, the wet etching process etching silicon nitride selectively to silicon oxide, silicon, and various other materials used in the art.

A backside recess (143,243) is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recess (143,243) includes a first backside recess 143 formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess 243 formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses (143,243) can be a laterally extending cavity having a lateral dimension that is greater than a vertical extent of the cavity. In other words, each of the backside recesses (143,243) can have a lateral dimension that is greater than a height of the respective backside recess (143,243). A plurality of backside recesses (143,243) can be formed in a volume of material from which the sacrificial material layers (142, 242) are removed. Each of the backside recesses (143,243) can extend substantially parallel to the top surface of the substrate semiconductor layer 9. The backside recess (143,243) can be vertically defined by a top surface of the underlying insulating layer (132, 232) and a bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143,243) can have a uniform height throughout.

Referring to fig. 65A and 65B, a backside blocking dielectric layer 44 may optionally be deposited in the backside recesses (143,243) and backside trenches 79 and over the first contact level dielectric layer 280. The backside blocking dielectric layer 44 comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the backside blocking dielectric layer 44 may comprise aluminum oxide. Backside blocking dielectric layer 44 may be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer 44 may be in the range of 1nm to 20nm, such as 2nm to 10nm, although lesser and greater thicknesses may also be used.

A conductive layer (146,246) may be formed by depositing at least one conductive material in the backside recess (143,243). A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous layer of metal material (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact level dielectric layer 280. Each of the first and second conductive layers 146 and 246 may include a respective conductive metal nitride liner and a respective conductive filler material. Thus, the first and second sacrificial material layers (142, 242) may be replaced with first and second conductive layers (146,246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of a backside blocking dielectric layer and first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of a backside blocking dielectric layer and second conductive layer 246. A backside cavity is present within the portion of each backside trench 79 that is not filled with a continuous layer of metal material.

Residual conductive material may be removed from inside the backside trench 79. In particular, the deposited metal material of the continuous metal material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280 and from within the backside trench 79, for example, by an anisotropic etching process and/or an isotropic etching process. Each remaining portion of the deposited metallic material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metallic material in the second backside recess constitutes a second conductive layer 246. The sidewalls of the first and second conductive material layers 146 and 79 may be physically exposed to the respective backside trenches.

Each conductive layer (146,246) can be a conductive sheet including an opening therein. A first subset of the openings through each conductive layer (146,246) can be filled with memory opening fill structures 58. A second subset of the openings through each conductive layer (146,246) can be filled with support pillar structures 20. Due to the first and second stepped surfaces, each conductive layer (146,246) can have a smaller area than any underlying conductive layer (146,246). Due to the first and second stepped surfaces, each conductive layer (146,246) can have a larger area than any overlying conductive layer (146,246).

In some embodiments, drain select level isolation structures 72 may be provided at the topmost level of the second conductive layer 246. A subset of the second conductive layers 246 positioned at the level of the drain select level isolation structure 72 constitute a drain select gate electrode. A subset of the conductive layers (146,246) positioned under the drain select gate electrode can be used as a combination of control gates and word lines positioned at the same level. The control gate electrode within each conductive layer (146,246) is a control gate electrode for a vertical memory device comprising a memory stack structure 55.

Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layer (146,246). A subset of the conductive layers (146,246) can include word lines for the memory elements. The semiconductor devices in the underlying peripheral device region 700 may include word line switching devices configured to control bias voltages to the corresponding word lines. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory hierarchy component includes at least one alternating stack (132,146,232,246) and a memory stack structure 55 extending vertically through the at least one alternating stack (132,146,232,246).

Referring to fig. 66A-66D, a layer of dielectric material may be conformally deposited in the backside trench 79 and over the first contact level dielectric layer 280 by a conformal deposition process. The layer of dielectric material may comprise, for example, silicon oxide. The thickness of the dielectric material may be in the range of 10nm to 50nm, but smaller and larger thicknesses may also be employed. An anisotropic etching process may be performed to remove horizontal portions of the dielectric material layer. A horizontal portion of the dielectric material layer may be removed from above the first contact level dielectric layer 280 and at the bottom of each backside trench 79. In addition, a central portion of the semiconductor oxide liner 122 may be removed from under each of the backside trenches 79 to physically expose a surface of the source contact layer 214. Each remaining portion of the dielectric material layer positioned at the peripheral portion of the backside trench 79 constitutes an insulating spacer 124.

At least one conductive material may be deposited in the unfilled volume of the backside trench 79. Excess portions of the at least one conductive material may be removed from over the top surface of the first contact level dielectric layer 280 by a planarization process. The planarization process may employ a recess etch process or a chemical mechanical planarization process. Each remaining portion of the at least one conductive material filling the backside trench 79 constitutes a backside contact via structure. Each backside contact via structure may be formed directly on the inner sidewall of the corresponding insulating spacer 124 and directly on the surface of the source contact layer 214.

Referring to fig. 67A and 67B, a second contact level dielectric layer 282 may be formed over the first contact level dielectric layer 280. The second contact level dielectric layer 282 comprises a dielectric material such as silicon oxide and may have a thickness in the range of 100nm to 600nm, although lesser and greater thicknesses may also be used.

A photoresist layer (not shown) may be applied over the second contact level dielectric layer 282 and may be lithographically patterned to form various contact via openings. For example, an opening for forming a drain contact via structure may be formed in the memory array region 100, and an opening for forming a stair region contact via structure may be formed in the stair region 200. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the second and first contact level dielectric layers (282,280) and underlying portions of dielectric material. The drain region 63 and the conductive layer (146,246) can function as an etch stop structure. A drain contact via cavity may be formed over each drain region 63 and a stair-step region contact via cavity may be formed over each conductive layer (146,246) at a stair-step surface under the first and second rearwardly-directed stair-step dielectric material portions (165, 265). The photoresist layer may then be removed, for example, by ashing.

A drain contact via structure 88 is formed in the drain contact via cavity and on a top surface of a respective one of the drain regions 63. A stair-region contact via structure 86 is formed in the stair-region contact via cavity and on a top surface of a respective one of the conductive layers (146,246). The stair-region contact via structures 86 may include drain select level contact via structures that contact a subset of the second conductive layer 246 that serves as a drain select level gate electrode. Furthermore, the stair-region contact via structures 86 may include word line contact via structures that contact the conductive layer (146,246) under the drain select level gate electrode and serve as word lines for the memory stack structure 55.

Referring to fig. 68, at least one additional dielectric layer may be formed over the contact level dielectric layer (280, 282), and additional metal interconnect structures (referred to herein as higher level metal interconnect structures) may be formed in the at least one additional dielectric layer. For example, the at least one additional dielectric layer may include a line level dielectric layer 290 formed over the contact level dielectric layer (280, 282). The higher level metal interconnect structure may include: a bit line 98 contacting a respective one of the drain contact via structures 88; and an interconnect line structure 96 that contacts and/or is electrically connected to at least one of the landing contact via structures 86.

With reference to all of the figures and in accordance with various embodiments of the present disclosure, there is provided a three-dimensional memory device comprising: a source-level material layer 110 positioned above the substrate 908 and comprising a lower semiconductor layer 212, a source contact layer 214, and an upper semiconductor layer 218, wherein the lower semiconductor layer 212 comprises a first boron-doped semiconductor material, the upper semiconductor layer 218 comprises a carbon-doped second boron-doped semiconductor material, and the source contact layer 214 comprises a boron-doped semiconductor material; an alternating stack of insulating layers (132, 232) and conductive layers (146,246), the alternating stack being positioned over the source-level material layer 110; and memory stack structures 55 extending vertically through the alternating stacks { (132,246), (232,246) }, higher semiconductor layers, and source contact layers, wherein each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel contacting the source contact layer.

In one embodiment, each of the first boron-doped semiconductor material and the second boron-doped semiconductor material comprises a silicon layer comprising a silicon having an atomic concentration of 1.0X10 ¹⁵ /cm ³ Up to 1.0X10 ¹⁹ /cm ³ Carbon atoms in the range of (2). In one embodiment, each of the first boron-doped semiconductor material and the second boron-doped semiconductor material comprises an atomic concentration of 1.0X10 ¹⁹ /cm ³ Up to 2.0X10 ²¹ /cm ³ Boron atoms in the range of (2). In one embodiment, the source contact layer 214 comprises a third boron doped semiconductor material comprising silicon comprising an atomic concentration of 1.0X10 ¹⁸ /cm ³ Up to 1.0X10 ²¹ /cm ³ Boron atoms in the range of (2).

In one embodiment, a three-dimensional memory device includes: backside trenches 79 extending vertically through the alternating stacks { (132,146), (232,246) }; and a backside contact via structure extending through the backside trench 79 and contacting the source contact layer 214. In one embodiment, the three-dimensional memory device includes insulating spacers 124 positioned in the backside trenches 79 and laterally surrounding the backside contact via structures and contacting sidewalls of layers within the alternating stacks { (132,146), (232,246) } and the surface of the source contact layer 214.

In one embodiment, each of the vertical semiconductor channels 360 includes a p-type semiconductor material having a smaller concentration of boron atoms than the source contact layer 214. In one implementation, each of the memory films 50 contacts a respective annular surface portion of the source contact layer 214. Each annular surface of the source contact layer 214 may be a convex annular surface.

In one implementation, each of the memory films 50 includes a charge storage layer 54 and a tunneling dielectric layer 56 that contacts a respective one of the vertical semiconductor channels 360. In one embodiment, the bottom end of each of the vertical semiconductor channels 360 is embedded within a respective dielectric layer stack that includes a layer of dielectric material 154 having the same composition and the same thickness as the charge storage layer 54, and another layer of dielectric material 156 having the same composition and the same thickness as the tunneling dielectric layer 56.

In one embodiment, the substrate 910 comprises a single crystal semiconductor material that is free of carbon; and the first boron-doped semiconductor material comprises a doped monocrystalline semiconductor material that is epitaxially aligned with the monocrystalline semiconductor material of the substrate 908. In one embodiment, the source contact layer 214 includes an epitaxial semiconductor material portion 214E that is epitaxially aligned with the monocrystalline semiconductor material of the substrate 908 by the doped monocrystalline semiconductor material of the lower semiconductor layer 212.

In one embodiment, each of the vertical semiconductor channels 360 has a bottom portion with a graded carbon dopant concentration that decreases with distance from the source contact layer 214.

In one embodiment, the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device, the conductive strips (146,246) comprise or are electrically connected to respective word lines of the monolithic three-dimensional NAND memory device, the substrate 908 comprises a silicon substrate, the monolithic three-dimensional NAND memory device comprises a monolithic three-dimensional NAND string array over the silicon substrate, and at least one memory cell in a first device level of the monolithic three-dimensional NAND string array is positioned over another memory cell in a second device level of the monolithic three-dimensional NAND string array. The silicon substrate may include an integrated circuit including driver circuitry for a memory device positioned thereon, the conductive stripe (146,246) including a plurality of control gate electrodes having a stripe shape extending substantially parallel to a top surface of the substrate 908, the plurality of control gate electrodes including at least a first control gate electrode positioned in a first device level and a second control gate electrode positioned in a second device level. The monolithic three dimensional NAND string array comprises a plurality of semiconductor channels 360, wherein at least one end of each of the plurality of semiconductor channels 360 extends substantially perpendicular to the top surface of the substrate 908, and one of the plurality of semiconductor channels comprising vertical semiconductor channels 360. The monolithic three dimensional NAND string array comprises a plurality of charge storage elements (including portions of memory film 50), each charge storage element positioned adjacent to a respective one of a plurality of semiconductor channels 360.

Embodiments of the present disclosure prevent unwanted boron diffusion into the vertical semiconductor channel 360 during a boosted read operation. In a boosted read operation, source contact layer 214 has a p-type doping with a higher boron concentration than vertical semiconductor channel 360. Negative threshold voltage settings may be employed for the source select electrode (i.e., the bottommost first conductive layer 146) and the drain select electrode (i.e., the topmost second conductive layer 246). Carbon atoms inhibit boron atoms from diffusing into vertical semiconductor channel 360, which improves the device threshold voltage and reduces undesirable channel leakage current in unselected blocks of memory stack structure 55. Boron doping in the source contact layer 214 allows holes to be implanted into the vertical semiconductor channel 360.

One of the advantages of the embodiments of the present disclosure is that the source contact layer 214 may be formed to be at least partially epitaxially aligned with the monocrystalline material in the substrate 908 to provide high charge carrier mobility. In addition, gate-induced drain leakage (GIDL) current need not be generated in devices of some embodiments of the present disclosure because the source contact layer 214 may generate a sufficient number of holes that may be implanted into the vertical semiconductor channel 360.

While specific embodiments have been mentioned in the foregoing, it will be understood that the claims are not so limited. Those of ordinary skill in the art will recognize that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the claims. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless explicitly stated otherwise, the word "comprising" or "comprises" contemplates all embodiments in which the word "consists essentially of …" or the word "consists of …" in lieu of the word "comprising" or "comprising". Embodiments using a particular structure and/or configuration are shown in this disclosure, it being understood that the claims may be practiced with any other compatible structure and/or configuration that is functionally equivalent, provided that such substitution is not explicitly prohibited or otherwise deemed to be impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising:

a first alternating stack of first insulating layers and first conductive layers, the first alternating stack positioned over a substrate;

a second alternating stack of second insulating layers and second conductive layers, the second alternating stack positioned above and spaced apart from the first alternating stack;

a memory opening extending vertically through the first alternating stack and the second alternating stack, wherein each of the memory openings includes one or more side apertures positioned between the first alternating stack and the second alternating stack; and

a memory opening fill structure positioned in a respective one of the memory openings and including a memory film, a semiconductor channel, and a dielectric core including a dielectric fill material,

wherein the dielectric core includes a dielectric post portion and one or more dielectric plug portions extending laterally from the dielectric post portion through one or more holes in the semiconductor channel and abutting respective side apertures.

2. The three-dimensional memory device of claim 1, wherein:

The one or more dielectric plug portions are connected to a dielectric strip of the dielectric fill material positioned outside the memory opening and between the first alternating stack and the second alternating stack; and is also provided with

The dielectric strips of the dielectric fill material include a plurality of dielectric strips extending laterally along a first horizontal direction and spaced apart along a second horizontal direction perpendicular to the first horizontal direction.

3. The three-dimensional memory device of claim 2, further comprising a support pillar structure extending vertically through at least a subset of layers within the first and second alternating stacks, including the dielectric fill material, and abutting a respective one of the plurality of dielectric strips.

4. The three-dimensional memory device of claim 3, wherein:

the first alternating stack includes a first stepped surface, wherein the first conductive layer has a lateral extent that decreases with vertical distance from the substrate;

the second alternating stack includes a second stepped surface, wherein the second conductive layer has a lateral extent that decreases with the vertical distance from the substrate; and is also provided with

A rearwardly stepped dielectric material portion overlies the first stepped surface and the second stepped surface, wherein the support post structure extends vertically through the rearwardly stepped dielectric material portion.

5. The three-dimensional memory device of claim 2, wherein each of the plurality of dielectric strips has two sets of straight sidewall sections, wherein each set of straight sidewall sections comprises a plurality of straight sidewall sections extending along the first horizontal direction positioned within a respective vertical plane.

6. The three-dimensional memory device of claim 2, further comprising a two-dimensional array of insulating material platelets, wherein a row of insulating material platelets is positioned between each adjacent pair of dielectric strips.

7. The three-dimensional memory device of claim 1, further comprising drain regions contacting upper ends of respective ones of the semiconductor channels and contacting top surfaces of respective ones of the dielectric pillar portions.

8. The three-dimensional memory device of claim 1, further comprising:

a layer of monocrystalline semiconductor material positioned in or over the substrate, wherein the semiconductor channel comprises an epitaxial semiconductor channel epitaxially aligned with the layer of monocrystalline semiconductor material; and is also provided with

An epitaxial pedestal channel portion contacting and epitaxially aligned with a respective one of the single crystal semiconductor material layer and the epitaxial semiconductor channel.

9. The three-dimensional memory device of claim 8, wherein each of the epitaxial pedestal channel portions contacts a bottom surface of a respective one of the dielectric pillar portions and a bottom portion of a cylindrical sidewall of the dielectric pillar portion.

10. The three-dimensional memory device of claim 8, wherein:

the epitaxial semiconductor channel comprises a material selected from monocrystalline silicon, monocrystalline silicon germanium alloy, or monocrystalline III-V compound semiconductor material; and is also provided with

The dielectric filler material is selected from undoped silicate glass, doped silicate glass or organosilicate glass.

11. The three-dimensional memory device of claim 1, wherein each of the semiconductor channels has a circular horizontal cross-sectional shape at a level of the first alternating stack and at a level of the second alternating stack, and a pair of block-arc horizontal cross-sectional shapes at a level of the dielectric plug portion.

12. The three-dimensional memory device of claim 1, wherein each of the side apertures in the memory opening has a rectangular shape with a same height as a vertical separation distance between the first alternating stack and the second alternating stack.

13. The three-dimensional memory device of claim 1, further comprising at least one additional alternating stack of additional insulating layers and additional conductive layers positioned above the second alternating stack, wherein each of the dielectric cores comprises an additional pair of dielectric plug portions extending laterally from a respective dielectric pillar portion above the at least one additional alternating stack.

14. A method of forming a three-dimensional memory device, the method comprising:

forming a first alternating stack of first insulating layers and first sacrificial material layers positioned over the monocrystalline semiconductor material layers;

forming a laterally alternating sequence of strips of insulating material and strips of sacrificial material over the first alternating stack;

forming a second alternating stack of second insulating layers and second sacrificial material layers over the laterally alternating sequence, wherein the first sacrificial material layers and the second sacrificial material layers are subsequently replaced with conductive layers;

forming memory openings extending through the first alternating stack, the laterally alternating sequence, and the second alternating stack;

forming a memory film and sacrificial conformal spacers within each memory opening;

Forming a network of cavities by removing the strips of sacrificial material and the sacrificial conformal spacers;

depositing a dielectric fill material in the network of cavities, wherein a dielectric core is formed in each memory opening and a dielectric stripe is formed in the volume of the sacrificial material stripe;

forming a channel cavity in each memory opening by selectively removing the sacrificial conformal spacers for the dielectric core and the memory film; and

an epitaxial semiconductor channel is formed within each of the channel cavities, the epitaxial semiconductor channel being epitaxially aligned with the single crystal semiconductor material layer.

15. The method according to claim 14, wherein:

each memory opening cuts through a respective one of the strips of sacrificial material;

and is also provided with

After removing the strip of sacrificial material, one or more apertures are formed in the sidewalls of each memory opening.

16. The method of claim 15, wherein each of the dielectric cores comprises dielectric post portions extending vertically through the first and second alternating stacks, and comprises one or more dielectric plug portions extending laterally from the dielectric post portions to respective side apertures to abut the dielectric strip of the dielectric fill material.

17. The method of claim 16, wherein the epitaxial semiconductor channel is formed in the channel cavity by a selective epitaxial process that grows monocrystalline semiconductor material up through the channel cavity and around each of the dielectric plug portions.

18. The method of claim 14, further comprising:

forming support openings through at least one layer of the first alternating stack, the laterally alternating sequence, and the second alternating stack, wherein each support opening cuts through a respective one of the strips of sacrificial material;

isotropically etching the strip of sacrificial material to form a laterally extending cavity; and

at least one isotropic etching process is used to isotropically etch portions of the memory film and portions of the sacrificial conformal spacers adjacent to the laterally extending cavities.

19. The method according to claim 18, wherein:

covering the memory openings with a sacrificial covering material, wherein memory cavities surrounded by sacrificial conformal spacers are present within each of the memory openings, and wherein the memory cavities are combined with the laterally extending cavities to form a network of the cavities after the at least one isotropic etching process;

Removing the sacrificial cover material; and is also provided with

The dielectric fill material is deposited in the laterally-extending cavity and in the memory cavity to form the dielectric core and the dielectric strip simultaneously.

20. The method of claim 16, further comprising forming drain regions on an upper end of a respective one of the epitaxial semiconductor channels and on a top surface of a respective one of the dielectric pillar portions.

21. A three-dimensional memory device, comprising:

a first layer of alternating stacks of first insulating layers and first conductive layers, the first layer of alternating stacks positioned over a substrate;

an interlayer insulating component positioned over the first layer alternating stack and comprising a plurality of dielectric strips, wherein each of the plurality of dielectric strips comprises a dielectric plug portion protruding laterally from a dielectric rail portion;

a second layer of alternating stacks of second insulating layers and second conductive layers, the second layer of alternating stacks positioned over the interlayer insulating assembly;

a memory opening extending vertically through the first layer alternating stack, the interlayer insulating component, and the second layer alternating stack, wherein each of the memory openings includes a side aperture through which a respective one of the dielectric plug portions extends inwardly; and

A memory opening fill structure positioned in a respective one of the memory openings and comprising a memory film, a semiconductor channel, and a dielectric core comprising a dielectric fill material and abutting the respective one of the dielectric plug portions.

22. The three-dimensional memory device of claim 21, wherein each of the semiconductor channels has a respective annular horizontal cross-sectional shape at a level of the first layer alternating stacks and at a level of the second layer alternating stacks, and a respective shape of a block arc at a level of the interlayer insulating component.

23. The three-dimensional memory device of claim 22, wherein each of the memory films has a respective annular horizontal cross-sectional shape at the level of the alternating stacks of first layers and at the level of the alternating stacks of second layers, and a respective shape of a block arc at the level of the interlayer insulating component.

24. The three-dimensional memory device of claim 21, wherein each interface between the dielectric cores and the dielectric plug portions comprises a convex vertical surface of a respective one of the dielectric cores and a concave vertical surface of a respective one of the dielectric plug portions.

25. The three-dimensional memory device of claim 21, wherein the interlayer insulating component comprises strips of insulating material interleaved with the plurality of dielectric strips, wherein a laterally alternating sequence of strips of insulating material and dielectric strips alternating along a first horizontal direction is present between the first layer alternating stack and the second layer alternating stack.

26. The three-dimensional memory device of claim 25, wherein each of the plurality of strips of insulating material contacts two columns of memory opening filling structures extending along a second horizontal direction perpendicular to the first horizontal direction.

27. The three-dimensional memory device of claim 25, further comprising:

a back side trench extending vertically through the first layer alternating stack, the interlayer insulating member, and the second layer alternating stack, extending laterally along the first horizontal direction, and having a uniform width along a second horizontal direction perpendicular to the first horizontal direction; and

a backside trench fill structure positioned in the backside trench, wherein each strip within the laterally alternating sequence of insulating material strips and dielectric strips contacts a sidewall of the backside trench fill structure.

28. The three-dimensional memory device of claim 25, wherein each of the plurality of dielectric strips has two sets of straight sidewall sections, wherein each set of straight sidewall sections comprises a plurality of straight sidewall sections positioned within a respective vertical plane perpendicular to the first horizontal direction.

29. The three-dimensional memory device of claim 21, further comprising:

a layer of monocrystalline semiconductor material positioned in or over the substrate, wherein the semiconductor channel comprises an epitaxial semiconductor channel epitaxially aligned with the layer of monocrystalline semiconductor material; and

a drain region comprising a doped epitaxial semiconductor material contacting an upper end of and epitaxially aligned with a respective one of the epitaxial semiconductor channels and contacting a top surface of a respective one of the dielectric cores.

30. The three-dimensional memory device of claim 29, further comprising a source contact layer comprising doped monocrystalline semiconductor material and contacting and epitaxially aligning the monocrystalline semiconductor material layer and the epitaxial semiconductor channel.

31. The three-dimensional memory device of claim 30, wherein the source contact layer contacts and laterally surrounds each of the dielectric cores.

32. The three-dimensional memory device of claim 30, wherein each interface between the source contact layer and the epitaxial semiconductor channel comprises an annular convex tapered surface of the source contact layer and an annular concave tapered surface of a respective one of the epitaxial semiconductor channels.

33. The three-dimensional memory device of claim 32, wherein:

The plurality of dielectric strips comprises a material selected from undoped silicate glass, doped silicate glass, or organosilicate glass.

34. A method of forming a three-dimensional memory device, the method comprising:

first insulating layers and first sacrificial material layers formed over the single crystal semiconductor material layers are alternately stacked;

forming a laterally alternating stack of strips of insulating material and strips of sacrificial material over the first layer alternating stack;

forming a second layer alternating stack of second insulating layers and second sacrificial material layers positioned above the laterally alternating stack, wherein the first sacrificial material layers and the second sacrificial material layers are subsequently replaced with conductive layers;

Forming a memory opening through the first layer alternating stack, the lateral alternating stack, and the second layer alternating stack; and

forming in-process memory opening fill structures in each memory opening, wherein the in-process memory opening fill structures include a memory film, sacrificial conformal spacers, and a dielectric core;

forming a laterally extending cavity by removing the strip of sacrificial material;

removing portions of the memory film and the sacrificial conformal spacers adjacent to the laterally extending cavities;

forming a dielectric strip in the laterally extending cavity and in the volume from which the memory film and the portions of the sacrificial conformal spacers are removed; and

the sacrificial conformal spacers are replaced with epitaxial semiconductor channels.

35. The method according to claim 34, wherein:

wherein each of the memory openings cuts through a longitudinal edge of a respective one of the strips of sacrificial material; and is also provided with

The dielectric strip is formed directly on the dielectric core.

36. The method of claim 34, wherein each of the dielectric strips comprises a dielectric rail portion filling a volume of one of the strips of sacrificial material, and comprises a dielectric plug portion protruding laterally from the dielectric rail portion and positioned within a column of memory openings.

37. The method of claim 34, further comprising:

after forming the in-process memory opening fill structure, forming backside trenches through the first layer alternating stack, the lateral alternating stack, and the second layer alternating stack; and

a first isotropic etchant is provided into the backside trench that etches material of the strip of sacrificial material selective to material of the strip of insulating material in a first isotropic etching process, wherein the laterally extending cavity is formed by the first isotropic etching process.

38. The method of claim 37, further comprising providing at least one second isotropic etchant that etches material of the memory film and the sacrificial conformal spacers through the backside trench and the laterally-extending cavities, wherein a pit cavity is formed within each of the memory openings in a volume adjacent to a respective one of the laterally-extending cavities, and wherein a dielectric plug portion of the dielectric strip is formed in the pit cavity.

39. The method of claim 34, further comprising:

Forming a channel cavity by selectively removing the sacrificial conformal spacers for the dielectric core and the memory film after forming the dielectric strips; and

the epitaxial semiconductor channel is formed in the channel cavity by a selective epitaxial process that grows monocrystalline semiconductor material up through the channel cavity.

40. The method of claim 34, further comprising:

forming a source level sacrificial layer over the single crystal semiconductor material layer, wherein the first layer is alternately stacked over the source level sacrificial layer; and

replacing the source level sacrificial layer with a source contact layer comprising a doped monocrystalline semiconductor material epitaxially aligned with the monocrystalline semiconductor material layer,

wherein the epitaxial semiconductor channel is formed directly on and epitaxially aligned with the source contact layer.

41. A three-dimensional memory device, comprising:

a source-level material layer positioned over the substrate and comprising a lower semiconductor layer, a source contact layer, and an upper semiconductor layer, wherein the lower semiconductor layer comprises a first boron-doped semiconductor material, the upper semiconductor layer comprises a carbon-doped second boron-doped semiconductor material, and the source contact layer comprises a boron-doped semiconductor material;

An alternating stack of insulating layers and conductive layers, the alternating stack positioned over the source-level material layer; and

a memory stack structure extending vertically through the alternating stacks, the higher semiconductor layers, and the source contact layers, wherein each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel contacting the source contact layer.

42. The three-dimensional memory device of claim 41, wherein each of the first boron-doped semiconductor material and the second boron-doped semiconductor material comprises a silicon layer comprising an atomic concentration at 1.0 x 10 ¹⁵ /cm ³ Up to 1.0X10 ¹⁹ /cm ³ Carbon atoms in the range of (2).

43. The three-dimensional memory device of claim 42, wherein each of the first boron-doped semiconductor material and the second boron-doped semiconductor material comprises an atomic concentration of 1.0 x 10 ¹⁸ /cm ³ Up to 2.0X10 ²¹ /cm ³ Boron atoms in the range of (2).

44The three-dimensional memory device of claim 42, wherein the source contact layer comprises a silicon layer comprising an atomic concentration of 1.0X10 ¹⁷ /cm ³ Up to 1.0X10 ²¹ /cm ³ Boron atoms in the range of (2).

45. The three-dimensional memory device of claim 41, further comprising:

backside trenches extending vertically through the alternating stack; and

a backside contact via structure extends through the backside trench and contacts the source contact layer.

46. The three-dimensional memory device of claim 45, further comprising an insulating spacer positioned in the backside trench and laterally surrounding the backside contact via structure and contacting sidewalls of layers within the alternating stack and a surface of the source contact layer.

47. The three-dimensional memory device of claim 41, wherein each of the vertical semiconductor channels comprises a p-type semiconductor material having a smaller concentration of boron atoms than the source contact layer.

48. The three-dimensional memory device of claim 47, wherein each of the memory films contacts a respective annular surface portion of the source contact layer.

49. The three-dimensional memory device of claim 47, wherein each of the memory films comprises a charge storage layer and a tunneling dielectric layer that contacts a respective one of the vertical semiconductor channels.

50. The three-dimensional memory device of claim 49, wherein a bottom end of each of the vertical semiconductor channels is embedded within a respective dielectric layer stack comprising a layer of dielectric material having the same composition and the same thickness as the charge storage layer, and another layer of dielectric material having the same composition and the same thickness as the tunneling dielectric layer.

51. The three-dimensional memory device of claim 41, wherein:

the substrate comprises a single crystal semiconductor material; and is also provided with

The first boron-doped semiconductor material comprises a doped monocrystalline semiconductor material epitaxially aligned with the monocrystalline semiconductor material of the substrate.

52. The three-dimensional memory device of claim 51, wherein the source contact layer comprises an epitaxial semiconductor material portion that is epitaxially aligned with the single crystal semiconductor material of the substrate by the doped single crystal semiconductor material of the lower semiconductor layer.

53. The three-dimensional memory device of claim 41, wherein each of the vertical semiconductor channels may have a bottom portion with a graded carbon dopant concentration that decreases with distance from the source contact layer.

54. A three-dimensional memory device, comprising:

a source-level material layer positioned over a substrate and comprising a lower semiconductor layer, a source contact layer, and an upper semiconductor layer, wherein the substrate comprises a single-crystalline semiconductor material, and the lower semiconductor layer comprises a first boron-doped semiconductor material comprising a doped single-crystalline semiconductor material that is epitaxially aligned with the single-crystalline semiconductor material of the substrate;

55. The three-dimensional memory device of claim 54, wherein:

the higher semiconductor layer comprises a second boron doped semiconductor material; and is also provided with

And the source contact layer comprises a boron doped semiconductor material.

56. The three-dimensional memory device of claim 55, wherein:

each of the first boron-doped semiconductor material and the second boron-doped semiconductor material includes a layer including a dopant having an atomic concentration of 1.0X10 ¹⁸ /cm ³ Up to 2.0X10 ²¹ /cm ³ Boron atoms and atomic concentration in the range of 1.0X10 ¹⁵ /cm ³ Up to 1.0X10 ¹⁹ /cm ³ Carbon atoms within the range of (2); and is also provided with

The source contact layer comprises a silicon layer having an atomic concentration of 1.0X10 ¹⁸ /cm ³ Up to 1.0X10 ²¹ /cm ³ Boron atoms in the range of (2).

57. A method of forming a semiconductor structure, the method comprising:

forming a lower semiconductor layer comprising a first boron doped semiconductor material over a substrate;

forming a sacrificial source level material layer over the lower semiconductor layer;

forming a higher semiconductor layer comprising a carbon doped second boron doped semiconductor material over the sacrificial source level material layer;

forming an alternating stack of insulating layers and spacer material layers over the higher semiconductor layer, wherein the spacer material layers are formed as conductive layers or are subsequently replaced by the conductive layers;

forming memory stack structures through the alternating stacks, the upper semiconductor layers, and source contact layers and into the lower semiconductor layers, wherein each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel contacting the source contact layer; and

The sacrificial source level material layer is replaced with a source contact layer comprising a boron doped semiconductor material.

58. The method of claim 57, wherein:

each of the first boron-doped semiconductor material and the second boron-doped semiconductor material includes a silicon layer including a silicon having an atomic concentration of 1.0X10 ¹⁵ /cm ³ Up to 1.0X10 ¹⁹ /cm ³ Carbon atoms and atomic concentration in the range of 1.0X10) ¹⁸ /cm ³ Up to 2.0X10 ²¹ /cm ³ Boron atoms in the range of (2); and is also provided with

The source contact layer comprises a silicon layer containing a silicon source having an atomic concentration of 1.0X10 ¹⁷ /cm ³ Up to 1.0X10 ²¹ /cm ³ Boron atoms in the range of (2).

59. The method of claim 57, further comprising:

forming backside trenches through the alternating stack to a top surface of the sacrificial source-level material layer; and

a backside contact via structure is formed in the backside trench and directly on the source contact layer.

60. The method of claim 57 wherein the substrate comprises a monocrystalline silicon wafer and the lower semiconductor layer comprises a monocrystalline silicon layer epitaxially grown on the monocrystalline silicon wafer.