CN113162612B

CN113162612B - All-digital self-excitation loop

Info

Publication number: CN113162612B
Application number: CN202110400875.0A
Authority: CN
Inventors: 付晓亮; 殷治国; 张天爵; 纪彬
Original assignee: China Institute of Atomic of Energy
Current assignee: China Institute of Atomic of Energy
Priority date: 2021-04-14
Filing date: 2021-04-14
Publication date: 2024-09-06
Anticipated expiration: 2041-04-14
Also published as: CN113162612A

Abstract

The invention discloses a full-digital self-excitation circuit, which comprises a high-frequency cavity, a transmitter at the input end of the high-frequency cavity, a comparator at the output end of the high-frequency cavity, and an FPGA (field programmable gate array) connected with the output end of the comparator and the input end of the transmitter so as to form a full-digital self-excitation loop; the FPGA comprises a DDS, a CPU and a phase-locked loop, wherein the DDS is used for keeping the frequency of the loop consistent with the resonant frequency of the cavity, the input end of the DDS is connected with the CPU and the phase-locked loop, and the output end of the DDS is connected with the transmitter; the CPU is used for controlling the amplitude and the phase of the DDS and controlling a phase-locked loop to select a clock source, and the phase-locked loop is used for providing a clock input signal for the DDS, and is characterized in that: the full-digital self-excitation circuit adopts the DDS as a signal source of the system, specifically adopts the output of the DDS as the clock input of the DDS, and the transmitter is an amplifier.

Description

All-digital self-excitation loop

Technical Field

The invention belongs to the technical field of accelerator high-frequency low-level systems, and particularly relates to an all-digital self-excitation loop.

Background

In cyclotron and superconducting linear accelerator systems, a high frequency cavity is used to accelerate moving particles. In order to feed high frequency power into the cavity and convert it into kinetic energy of particle motion, the signal frequency of the high frequency power source must be kept consistent with the resonant frequency of the cavity. There are two ways to achieve this: one is to use an external driving signal and fix the frequency of the driving signal, and change the resonant frequency of the cavity to be consistent with the frequency of the external driving signal, so as to generate resonance, and such a system is called as a driven system; the other is that an external driving signal is not used, and a loop formed by the cavity, the amplifier, the limiter and the phase shifter is used for generating positive feedback self-excited oscillation, so that the frequency clock of the loop is kept at the resonant frequency of the cavity, and the system is called a self-excited system.

Because the Q value of the high-frequency cavity is generally higher, the bandwidth is very narrow, and when the cavity is driven in a separate excitation mode, in order to avoid the overlarge reflected power born by the transmitter, the cavity must be driven by low power during starting, and the trimming capacitor of the cavity is moved to find the resonance frequency point. After the resonance frequency point is found, the separate excitation system can gradually increase the power, and the cavity tuning is maintained in real time in the power increasing process. In a normal-temperature high-frequency cavity, the starting process of the separate excitation system is common and can be repeated. However, in superconducting cavities, the lorentz forces can cause the cavity to deform and detune due to extremely high field strengths. The separate excitation system must be very slow in boosting the power to prevent the power reflection caused by the detuning due to the lorentz force. Compared with the other excitation system, the self-excitation system has the advantages that the high-power feed-in can be directly achieved without tuning the cavity, and when the resonant frequency of the cavity changes due to temperature and mechanical deformation, the resonant frequency of the cavity is automatically tracked, so that the cavity is always kept at the resonant frequency. This allows the self-excited system to automatically compensate for the Lorentz force induced detuning. Therefore, since the invention, self-excited systems have been widely used in the cavities of superconducting linear accelerators.

The self-excitation system applied to the accelerator field basically comprises: cavity, transmitter, limiter, phase shifter. Because of the great difficulty in implementing limiters in digital systems, free-running systems are often presented in analog or digital-to-analog hybrid circuits. In recent years, the Thomas Jefferson laboratory in the united states, the indian baba atomic research center and the university of dammstatt industry in germany have all implemented all-digital self-excitation systems in different ways for use on superconducting linear accelerators. From the application point of view, the first analog or digital-analog hybrid circuit has the problem 1: the sampled signal returned from the cavity is processed by a series of analog circuits, the output of which is provided with an IQ modulator to the transmitter, and the IQ modulator is analog, so that the analog circuits can generate temperature drift and nonlinear distortion; problem 2: the digital-analog hybrid system is very complex in construction, and each module needs to be debugged to form the expected effect. To overcome the problems with analog circuits, all-digital self-excited circuits, such as those of the Thomas Jefferson laboratory in the united states, which operate at amplitude and phase coordinates, have been studied internationally. Problem 1: the circuit comprises a plurality of CIC filters and FIC filters, and the structural algorithm is troublesome; problem 2: the loop requires an external source to provide a very accurate clock, and once the configuration is complete, the external clock signal must be fixed, as must the multiple between the sampled and sampled signals. The indian baba atomic research center developed another all-digital self-exciting circuit, which is another way to implement an all-digital self-exciting circuit: a series of operations are performed entirely in IQ coordinates, which has the disadvantage that: the structure is too complex and the effect is not good.

Common to the prior art self-excitation systems described above is: 1. the high-frequency signals are all required to be sampled and converted into IQ signals by an ADC (analog to digital converter), and then the IQ signals are subjected to subsequent processing; 2. a well-defined multiple relationship is required for the system sampling clock and the sampled signal. Due to the existence of the second limiting condition, the universality of the system is poor, and the complexity of the system is improved.

Disclosure of Invention

The invention provides a full-digital self-excited loop for solving the problems existing in the prior art, and the first aim is to solve the problems that high-frequency signals are all required to be converted into IQ signals by ADC sampling and then are subjected to subsequent processing, and because an IQ modulator is analog, the analog modulator can generate some unwanted results; the second purpose is to solve the problems that the system sampling clock and the sampled signal need clear multiple relation, the universality is poor and the system complexity is high.

The invention provides the following technical scheme for solving the technical problems:

the full-digital self-excitation circuit comprises a high-frequency cavity, a transmitter at the input end of the high-frequency cavity, a comparator at the output end of the high-frequency cavity, and an FPGA (field programmable gate array) connected with the output end of the comparator and the input end of the transmitter so as to form a full-digital self-excitation loop; the FPGA comprises a DDS, a CPU and a phase-locked loop, wherein the DDS is used for keeping the frequency of the loop consistent with the resonant frequency of the cavity, the input end of the DDS is connected with the CPU and the phase-locked loop, and the output end of the DDS is connected with the transmitter; the CPU is used for controlling the amplitude and the phase of the DDS and controlling a phase-locked loop to select a clock source, and the phase-locked loop is used for providing a clock input signal for the DDS, and is characterized in that: the full-digital self-excitation circuit adopts DDS as a signal source of the system, specifically adopts the output of the DDS as the clock input of the DDS, and the transmitter is an amplifier.

The output of the DDS is used as the clock input of the DDS, and specifically comprises the following steps: the output signal of the DDS forms a square wave clock signal after passing through a transmitter, a high-frequency cavity and a comparator, the square wave clock signal is input into a phase-locked loop of the FPGA to be multiplied, a frequency multiplication clock is obtained, and the frequency multiplication clock signal is input into the DDS in the FPGA.

The phase-locked loop in the FPGA receives two clock signal inputs, one of which is from the output of the DDS and the other of which is from the output of an external signal source, and the clock source of the phase-locked loop can be selected by a clock selection end, and the input of the clock selection end is from GPIO controlled by the CPU.

The CPU is used for controlling the amplitude and the phase of the DDS, and specifically comprises the following steps: the phase of the loop is changed by setting the phase bias of the DDS, which value is controlled by the CPU; the output signal amplitude of the DDS is changed by an amplitude word of the DDS, and the value is controlled by the CPU.

The DDS is used for keeping the frequency of the loop consistent with the resonant frequency of the cavity, and specifically comprises the following steps: after the system forms self-excitation oscillation, the frequency of the loop can be adjusted by adjusting the phase of the DDS, so that the frequency is consistent with the resonant frequency of the cavity, and the amplitude word of the DDS can be controlled by the CPU to rapidly increase the power, so that the loop can automatically track the resonant frequency of the cavity, and the cavity is kept to be tuned.

After the power is increased to the power required for operation, the tuning capacitance of the cavity is moved so that the resonant frequency of the cavity approaches the frequency of the external reference signal.

The CPU controls the phase-locked loop to select a clock source, and specifically comprises the following steps: the self-excitation to other excitation conversion can be realized by controlling the GPIO to switch the clock source of the phase-locked loop through the CPU, and then the system works as an other excitation mode.

Advantageous effects of the invention

1. The invention adopts the full-digital self-excitation circuit based on the cavity, the amplifier and the DDS, thereby solving the problems of temperature drift and nonlinear distortion of the traditional analog circuit and reducing the complexity of realizing the self-excitation loop of the digital circuit. The invention uses DDS to realize self-excited loop, does not need to realize limiter, has the system clock frequency irrelevant to the frequency of the processed signal, greatly improves the flexibility and application range of the system, and reduces the complexity of digital algorithm and the consumption of hardware devices. Compared with the prior system, the method reduces the difficulty of a digital algorithm, greatly saves hardware resources and improves the reliability of the system.

2. The invention breaks through the traditional thinking formula, applies the DDS core device which is considered to be only applied in the separate excitation loop to the self-excitation loop, has very simple implementation mode, and successfully tests in a laboratory, thereby obtaining unexpected effects.

3. The invention adopts the full digital circuit to realize the self-excitation loop, is not only suitable for superconducting cavities, but also can use normal-temperature cavities, reduces the complexity of the system and improves the reliability of the system.

4. The invention provides a novel all-digital self-excitation loop, in particular to an all-digital low-level system, which can integrate the self-excitation loop into the all-digital low-level system by adopting the design principle of the invention and can switch back and forth between two modes of self-excitation and other excitation.

Drawings

FIG. 1 is a block diagram of a system according to the present invention

Detailed Description

Principle of design of the invention

1. The invention overcomes the traditional prejudice and is quite unexpected. Neither the former analog mode nor the modern digital mode uses DDS in the loop, because the normal usage of DDS is in the separate loop, but not in the free-running loop, because the input clock of DDS is a fixed frequency, the output is fixed, and the input clock of the free-running loop is variable, the output is also variable. The present invention is highly unexpected: the core device, which is considered to be applicable only in the separate excitation loop, is applied to the free-running loop and the implementation is very simple, which is very unexpected. The industry has long developed a mental formula: the DDS clock is unchanged, and after the DDS clock is configured, for example, a 200-megaclock is given, and a 40-megasignal is output unchanged. No one has tried to use DDS for the free-running loop, and the invention has been tested successfully in the laboratory, can oscillate, and is very convenient.

2. The invention relates to a design principle of a self-excited loop. The self-excited loop is called a self-excited oscillation loop, namely, an external signal source is not needed, and only one amplifier can oscillate and maintain stability. When the self-excitation loop is applied to the field of accelerators, a large self-excitation loop is formed by connecting the self-excitation loop, the cavity and the amplifier, and the effect is that the self-excitation loop can oscillate without external driving and is maintained within the resonance frequency of the cavity, that is, the loop can naturally vibrate and the loop is maintained within the bandwidth. The advantages of the self-excited loop are apparent: the power supply is started up without external drive, the amplitude is increased, the power is also increased, and the frequency of the self-excited loop is changed along with the frequency change of the cavity. Corresponding to the free-running loop is a separate-running loop: the other excitation loop is not known to the cavity frequency, then the other excitation loop is driven by a fixed frequency, the fixed frequency is possibly mismatched with the cavity frequency, for example, 50 megameters of fixed frequency is used for driving 30 megameters of cavity frequency, the cavity frequency is changed from 30 megameters to 50 megameters if the positive power is over, and when the other excitation loop frequency is consistent with the cavity frequency, the power is fed into the high-frequency cavity, which is the design idea of the other excitation loop. The design idea of the separate excitation loop is to change the cavity to adapt to the driving signal, and the design idea of the self-excitation loop is to change the driving signal to adapt to the cavity.

Summarizing: DDS is well known for use in a separate excitation loop system, calculates a clock frequency to keep the clock frequency unchanged for output, applies separate excitation to a separate excitation loop, and is very simple to implement, and the free-running circuit of the present invention is very simple and can be easily switched from a free-running mode to a separate excitation mode as shown in fig. 1.

Based on the design principle, the invention designs an all-digital self-excitation circuit as shown in figure 1, which comprises a high-frequency cavity, a transmitter at the input end of the high-frequency cavity, a comparator at the output end of the high-frequency cavity, and an FPGA (field programmable gate array) connecting the output end of the comparator and the input end of the transmitter, thereby forming an all-digital self-excitation loop; the FPGA comprises a DDS, a CPU and a phase-locked loop, wherein the DDS is used for keeping the frequency of the loop consistent with the resonant frequency of the cavity, the input end of the DDS is connected with the CPU and the phase-locked loop, and the output end of the DDS is connected with the transmitter; the CPU is used for controlling the amplitude and the phase of the DDS and controlling a phase-locked loop to select a clock source, and the phase-locked loop is used for providing a clock input signal for the DDS, and is characterized in that: the full-digital self-excitation circuit adopts DDS as a signal source of the system, and specifically adopts the output of the DDS as the clock input of the DDS. The transmitter is an amplifier;

Examples

In an all-digital low level control system for an accelerator, the RF signal frequency is approximately 23MHz. The DDS is designed to output a 23MHz signal, and the input clock of the DDS is 184MHz. The cavity sampling signal is passed through attenuator to form signal with proper amplitude, and then inputted into comparator and fed into phase-locked loop in FPGA. The phase locked loop takes this signal as a clock source by default. After the system self-excited oscillation, the phase of the DDS is controlled and regulated by the CPU to change the loop frequency, and the change of the cavity feedback signal is observed on the oscilloscope. When the loop frequency is consistent with the cavity resonant frequency, the cavity feedback signal observed on the oscilloscope reaches a maximum value. At this time, the phase of the DDS is fixed, and the output signal amplitude of the DDS starts to increase. When the amplitude reaches the required value, the amplitude is stopped from being increased, the trimming capacitor is controlled to move through the trimming mechanism of the cavity, and the resonant frequency of the cavity is changed to be consistent with an external reference signal of 23MHz. At this time, the CPU can control the phase-locked loop to switch the clock source, and the external reference signal is selected as the clock source, so as to complete the switching from the free-running loop to the other-running loop.

It should be emphasized that the embodiments described herein are illustrative rather than limiting and that this invention encompasses embodiments not limited to the specific implementations.

Claims

1. The full-digital self-excitation circuit comprises a high-frequency cavity, a transmitter at the input end of the high-frequency cavity, a comparator at the output end of the high-frequency cavity, and an FPGA (field programmable gate array) connected with the output end of the comparator and the input end of the transmitter so as to form a full-digital self-excitation loop; the FPGA comprises a DDS, a CPU and a phase-locked loop, wherein the DDS is used for keeping the frequency of the loop consistent with the resonant frequency of the cavity, the input end of the DDS is connected with the CPU and the phase-locked loop, and the output end of the DDS is connected with the transmitter; the CPU is used for controlling the amplitude and the phase of the DDS and controlling a phase-locked loop to select a clock source, and the phase-locked loop is used for providing a clock input signal for the DDS, and is characterized in that: the full-digital self-excitation circuit adopts DDS as a signal source of the system, specifically adopts the output of the DDS as the clock input of the DDS, and the transmitter is an amplifier;

The output of the DDS is used as the clock input of the DDS, and specifically comprises the following steps: the output signal of the DDS forms a square wave clock signal after passing through a transmitter, a high-frequency cavity and a comparator, the square wave clock signal is input into a phase-locked loop of the FPGA to be multiplied, a frequency multiplication clock is obtained, and the frequency multiplication clock signal is input into the DDS in the FPGA;

The phase-locked loop in the FPGA receives two clock signal inputs, one of which is from the output of the DDS and the other of which is from the output of an external signal source, the clock source of the phase-locked loop is selected by a clock selection end, and the input of the clock selection end is from a GPIO controlled by the CPU.

2. An all-digital self-exciting circuit according to claim 1, wherein: the CPU is used for controlling the amplitude and the phase of the DDS, and specifically comprises the following steps: the phase of the loop is changed by setting the phase bias of the DDS, which value is controlled by the CPU; the output signal amplitude of the DDS is changed by an amplitude word of the DDS, which value is controlled by the CPU.

3. An all-digital self-exciting circuit according to claim 1, wherein: the DDS is used for keeping the frequency of the loop consistent with the resonant frequency of the cavity, and specifically comprises the following steps: after the system forms self-excitation oscillation, the phase of the DDS is regulated, the frequency of the loop is regulated to be consistent with the resonant frequency of the cavity, and the amplitude word of the DDS can be controlled by the CPU to rapidly increase the power, so that the loop can automatically track the resonant frequency of the cavity and keep the cavity tuned.

4. An all-digital self-exciting circuit according to claim 3, wherein: after the power is increased to the power required for operation, the tuning capacitance of the cavity is moved so that the resonant frequency of the cavity approaches the frequency of the external reference signal.

5. An all-digital self-exciting circuit according to claim 1, wherein: the CPU controls the phase-locked loop to select a clock source, and specifically comprises the following steps: the self-excitation to other excitation conversion can be realized by controlling the GPIO to switch the clock source of the phase-locked loop through the CPU, and then the system works as an other excitation mode.