CN113161284A - Method for manufacturing interconnection structure - Google Patents

Method for manufacturing interconnection structure Download PDF

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Publication number
CN113161284A
CN113161284A CN202010013805.5A CN202010013805A CN113161284A CN 113161284 A CN113161284 A CN 113161284A CN 202010013805 A CN202010013805 A CN 202010013805A CN 113161284 A CN113161284 A CN 113161284A
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China
Prior art keywords
layer
hard mask
opening
metal hard
dielectric layer
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CN202010013805.5A
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Chinese (zh)
Inventor
徐民翰
曹荣志
陈俊彰
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Taiji Telecom Nanjing Co ltd
TSMC Nanjing Co Ltd
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiji Telecom Nanjing Co ltd
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiji Telecom Nanjing Co ltd, Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiji Telecom Nanjing Co ltd
Priority to CN202010013805.5A priority Critical patent/CN113161284A/en
Priority to US16/801,706 priority patent/US11450557B2/en
Priority to TW109116978A priority patent/TWI729821B/en
Publication of CN113161284A publication Critical patent/CN113161284A/en
Priority to US17/816,051 priority patent/US12051617B2/en
Pending legal-status Critical Current

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
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Abstract

The present disclosure relates to a method for fabricating an interconnect structure. A method of fabricating a dual damascene interconnect comprising the operations of: depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of the base conductive layer; modifying sidewalls of the metal hard mask opening; and depositing a conductive material in the metal hard mask opening and the at least one interconnect opening.

Description

Method for manufacturing interconnection structure
Technical Field
The present disclosure relates to a method for fabricating an interconnect structure.
Background
Dual damascene interconnects (dual damascene interconnects) provide reliable interconnects between various layers of an integrated circuit. Voids in the interconnects may increase resistance and reduce the overall reliability of the integrated circuit, and may reduce the clock speed of the device.
Disclosure of Invention
According to an embodiment of the present disclosure, there is provided a method of manufacturing an interconnect structure, including: depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of a base conductive layer; modifying sidewalls of the metal hard mask opening by adding non-metal atoms to a metallic layer of the metal hard mask; and depositing a conductive material in the metal hard mask opening and the at least one interconnect opening.
According to another embodiment of the present disclosure, there is provided a method of manufacturing an interconnect structure, including: depositing a dielectric layer over the first copper interconnect structure; depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask; etching a first portion of an interconnect structure opening in the dielectric layer; etching a second portion of the interconnect structure opening in the dielectric layer; modifying sidewalls of the metal hard mask opening by heat treating the metal hard mask; and depositing a conductive material in the interconnect structure opening through the metal hard mask opening.
According to yet another embodiment of the present disclosure, there is provided a method of manufacturing an interconnect structure, including: depositing a dielectric layer over a substrate; depositing a hard mask layer over the dielectric layer; exposing a top surface of the dielectric layer through a hard mask layer opening; etching an interconnect opening in the dielectric layer; modifying sidewalls of the hard mask layer opening; and filling the interconnect opening with a conductive material through the hard mask layer opening having the modified sidewall.
Drawings
The disclosure is best understood from the following detailed description when read in connection with the accompanying drawing. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-1B are cross-sectional views of a semiconductor device during a fabrication process according to some embodiments.
Fig. 2 is a cross-sectional view of a semiconductor device having a sloped sidewall profile during a fabrication process according to some embodiments.
Fig. 3 is a cross-sectional view of a semiconductor device having copper interconnects during a fabrication process according to some embodiments.
Fig. 4 is a cross-sectional view of a semiconductor device having copper interconnects during a fabrication process according to some embodiments.
Figure 5 is a flow chart of a method of fabricating a copper interconnect according to some embodiments.
Fig. 6 is a cross-sectional view of multiple layers of an integrated circuit during a fabrication process according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In fabricating a semiconductor device or integrated circuit having a dual damascene interconnect, conductive material added to the dual damascene structure opening is added in at least two processes. After forming trench and via openings in one or more layers of dielectric material, a layer of seed material is deposited into the trench and via openings. A layer of seed material is also deposited on the underlying conductive material at the bottom of the dual damascene structure opening prior to adding the bulk conductive material to the dual damascene structure. In some cases, a seed material or seed layer is sputtered onto the sidewalls of the dual damascene structure and onto the exposed portions of the underlying conductive material. In some embodiments, the seed layer comprises pure copper or a copper alloy. A bulk conductive material is filled into the dual damascene structure opening by electroplating, which results in a filled dual damascene structure and a layer of conductive material on the top surface of the die where the dual damascene structure is formed. In some embodiments, the plated bulk conductive material is copper or a copper alloy. In some embodiments, the seed layer and the electroplated bulk conductive material are the same alloy. In some cases, the seed layer and the plated bulk conductive material are different materials to promote adhesion of the seed layer to a liner (liner) located on sidewalls of the dual damascene structure and/or to reduce voids in the plated bulk conductive material.
Because electroplating of conductive materials is sensitive to the diffusion rate of the material into the openings (e.g., dual damascene structures), during the electroplating process, obstacles or features that promote non-uniform seed layer deposition can affect the flow of dissolved ions of the conductive material into the dual damascene structures. The restriction of the ion access opening to the conductive material allows voids to form in the resulting interconnect structure while the resistance of the interconnect structure increases beyond the threshold interconnect structure resistance of the integrated circuit.
Reducing and/or eliminating voids in the interconnect structure results in an overall reduction in resistance of an integrated circuit including the interconnect structure. The lower resistance also contributes to a faster overall switching time of the transistors of the integrated circuit.
Fig. 1 is a cross-sectional view of a semiconductor device 100 during a fabrication process according to some embodiments. Fig. 5 is a flow chart of a method 500 of fabricating a copper interconnect according to some embodiments. The operation of method 500 is described below and throughout this description reference is made to elements of the dual damascene trench structure and copper interconnect structure of fig. 1-4 as representative of embodiments of the present disclosure.
Semiconductor device 100 includes a dual damascene structure 101 located over a base conductive layer 114. Etch stop layer 112 is located over base conductive layer 114, and dielectric layer 110 is over etch stop layer 112. In some embodiments, the base conductive layer 114 is a contact. In some embodiments, the base conductive layer 114 is a metal line. In some cases, base conductive layer 114 is a dual damascene-type interconnect located in a lower layer of an integrated circuit. The base conductive layer stack is thus formed by sputtering or electroplating to accommodate the profile of the filled opening and the integration scheme used in manufacturing the integrated circuit. In some embodiments, the base conductive layer is a contact located in a lower layer of the semiconductor device. In some embodiments, the base conductive layer is a metal line located on a lower layer of the semiconductor device. In some embodiments, the base conductive layer is a dual damascene structure located in different layers of the semiconductor device.
Etch stop layer 112 comprises one or more layers of dielectric material having a lower etch selectivity to the etch process (under the etch conditions that form the interconnect opening in the dielectric layer as compared to dielectric layer 110). In some cases, the etch stop layer is comprised of one or more layers of silicon nitride or silicon oxynitride deposited on the lower dielectric layer and directly below the dielectric layer 110.
The dielectric layer 110 is an inter-layer dielectric layer (ILD) deposited over the etch stop layer 112. The dielectric layer 110 is etched to form openings for forming interconnect structures therein. The interconnect structure includes a dual damascene interconnect structure having a via region and a bar (bar)/trench region. Dual damascene structure 101 has a trench opening in upper region 116C and two or more via openings in lower region 116D. According to some embodiments, the thickness of the upper region 116C and the thickness of the lower region 116D are approximately the same thickness. In some embodiments, the thickness of the upper region 116C and the lower region 116D are different thicknesses. In some embodiments, the thickness of the upper region 116C is less than the thickness of the lower region 116D.
Dielectric layer 110 comprises silicon dioxide, spin-on glass, borophospho spin-on glass (BPSG), fluorinated silicon dioxide glass (FSG), or an organic low-K dielectric material including, for example, silicon, oxygen, carbon, and hydrogen. Non-limiting examples of integrated circuits having organic low-k dielectric materials include low-k dielectric materials, e.g., BLACK
Figure BDA0002358100870000041
Porous silicon, and the like. The material used for the dielectric layer 110 depends on the spacing and width between adjacent lines (or trenches) in the dielectric layer. Silicon dioxide is one example of a dielectric material that is deposited on a Contact Etch Stop Layer (CESL) by Chemical Vapor Deposition (CVD). Chemical vapor deposition techniques include plasma enhanced chemical vapor deposition (PE-CVD), high pressure chemical vapor deposition (HP-CVD), and the like. BPSG, FSG, and various low K dielectric materials are deposited onto the contact etch stop layer by various methods, including depositing a liquid matrix, and then spinning the wafer to remove excess material, leaving a thin film of dielectric material on the substrate. Some examples of low-K dielectric materials are deposited onto a contact etch stop layer or other substrate by techniques similar to PE-CVD, where the dielectric material is the result of a chemical reaction that occurs in a plasma above the substrate where the deposition occurs.
In some embodiments, dielectric layer 110 is a single layer film deposited in one process. In some embodiments, dielectric layer 110 comprises a plurality of dielectric materials deposited over etch stop layer 112. Antireflective layer 106 of metal hard mask 108 is situated over dielectric layer 110. In some embodiments, antireflective layer 106 is directly against the top surface of dielectric layer 110. Dual damascene structure 101 includes two openings 116A and 116B, which openings 116A and 116B extend through metal hard mask 108, dielectric layer 110, and etch stop layer 112 to expose a top surface of base conductive layer 114.
The method 500 includes an operation 505 in which a metal hard mask (e.g., metal hard mask 108) is deposited over the dielectric layer 110. The metal hard mask 108 includes an antireflective layer 102, a metallic layer 104A (e.g., a metal nitride layer), and an antireflective layer 106. In some embodiments, the metal hardmask includes a single antireflective layer and a metallic layer, rather than two antireflective layers and metallic layers. When two anti-reflective layers are present in the metal hard mask, a first anti-reflective layer is located above the metallic layer and a second anti-reflective layer is located below the metallic layer. In dual damascene structure 101, antireflective layers 102 and 106, located above and below metallic layer 104A, are used to improve the lithography of the metallic layer. Improved lithographic techniques include increased uniformity in the width of the opening, improved flatness of the edges of the opening, and more vertical sidewalls of the opening. In some embodiments, a single antireflective layer is present over the metallic layer. In some embodiments, a single antireflective layer is present under the metallic layer. The antireflective layer adjusts the photolithography process to achieve a uniform line shape and profile of the sidewalls of the metallic layer or the underlying dielectric layer.
The number of antireflective layers included in the metal hard mask depends on the difficulty associated with forming an opening through the metal hard mask and in the underlying dielectric layer. For some combinations of dielectric layers and metal hard masks, a single antireflective layer located below the metallic layer is sufficient to maintain uniform sidewall profile and line shape of the opening. A second anti-reflective layer is included to improve the shape of the opening through the metallic layer and into the dielectric layer when the sidewalls of the opening through the nitride layer or in the dielectric layer have a lateral vibration or undulation.
According to some embodiments, the metallic layer 104A is a titanium nitride layer, although nitrides of other metals are also contemplated within the scope of the present disclosure. Other metals used to fabricate the nitride layer of the hardmask include, but are not limited to, titanium, zirconium, tantalum, niobium, vanadium, tungsten, chromium, cobalt, nickel, silicon, and zinc.
The metallic layer 104A has a thickness in the range of about 10nm to about 100 nm. The thickness of the metallic layer greater than 100nm increases the cost of manufacturing the integrated circuit without producing additional benefits in improving the line smoothness of the trenches or vias of the dual damascene structure. A metallic layer less than 10nm thick may not be able to withstand the etching process for a sufficient time to sufficiently reduce or prevent unintended line roughness of the trenches or vias of the dual damascene structure. Furthermore, metallic layers less than 10nm thick exhibit thickness variations that affect the etch time to penetrate the metallic hard mask layer without changing the depth of the etch into the underlying dielectric layer. As the metal hardmask etch process penetrates the metal hardmask and into the dielectric layer, the depth of the trench portion of the interconnect opening is not uniform across the die, causing interconnect structure resistance to deviate from the circuit specifications of the overall circuit.
Antireflective layer 102 is deposited over dielectric layer 110 or on top of metallic layer 104A to create a more uniform structure developed by photolithographic techniques. The antireflective layer reduces and/or eliminates wiggle curves, standing waves in the photoresist, and line width variations of the patterned lines. Antireflective layers (e.g., antireflective layers 102, 106) help create interconnects with electrical resistance and other electrical characteristics that meet the design specifications of the integrated circuit. Deviations in the electrical performance of interconnect structures from design specifications can adversely affect the integrated circuit. Such deviations include increased resistance, slower switching times, parasitic capacitance, and electromigration. The antireflective layers 102, 106 each have a thickness of about 10nm to about 100 nm. When the antireflective layer is thinner than about 10nm, the antireflective layer does not provide sufficient protection from the above-mentioned lithographic defects in the integrated circuit manufacturing process. When the antireflective layer is thicker than about 100nm, the antireflective layer does not provide additional benefits, but consumes more material and increases the complexity of manufacturing the integrated circuit. The increased complexity of manufacturing integrated circuits is associated with the processes of developing photoresist, removing antireflective layers, and cleaning residual particles from surfaces during the manufacturing process. In some embodiments, the antireflective layer is a BARC layer, a top-side ARC layer, or a DARC layer. In some cases, the antireflective layer is nitrogen-free.
The method 500 includes an operation 510 in which an opening is etched in a metal hard mask. The opening in the hard mask is formed by: the method includes depositing a layer of patterning material (e.g., photoresist) on a top surface of the metal hard mask, forming a pattern within the layer of patterning material (e.g., by photolithography, or e-beam lithography), and removing a portion of the pattern to expose a top layer of the metal hard mask. Etching the opening in the metal hard mask includes one or more plasma etching steps to remove a portion of the hard mask exposed within the opening overlying the patterned layer. The chemistry, pressure, and power settings of the plasma etch step used to remove portions of the metal hard mask are adjusted based on the material of the metal hard mask and the dimensions of the openings in the overlying patterned layer.
The method 500 also includes an operation 515 in which at least one interconnect opening is formed below the metal hard mask. According to some embodiments, the interconnect opening extends through two layers of the metal hard mask, the dielectric layer, and the CESL in the semiconductor film stack. The interconnect opening is formed in multiple steps. One step of the operation in which the interconnect opening is formed includes: at least one etching process for forming one or more openings in the metal hard mask layer (e.g., metal hard mask 108). In some embodiments, one step of the operation for forming the interconnect opening comprises: a trench is formed in an upper portion of the dielectric layer and then a via is formed extending through a lower portion of the dielectric layer. In some cases, the vias are formed first, followed by the trench portions of the interconnect openings. For purposes of this discussion, a description of the operations for forming the interconnect opening will include a trench-first scheme, as described below, although via-first schemes are also contemplated by the present disclosure. In some embodiments, one step of the operation for forming the interconnect opening further comprises: an opening is formed in the CESL underlying the dielectric layer to expose the conductive base layer.
In a trench first scheme for fabricating interconnect openings, the openings 116A, 116B in the metal hard mask 108 correspond to the profile of the trenches to be formed in the upper portion 116C of the dielectric layer 110. In dual damascene structure 101, upper portion 116C includes an opening in an upper portion of dielectric layer 110 and an opening in metal hard mask 108.
Once the trenches have been formed in the upper region 116C, any residual patterning material remaining on the top surface of the metal hard mask 108 is removed, and a second layer of patterning material is deposited on the top surface of the metal hard mask and within the trench openings in the upper region 116C. During the second patterning step, portions of the second patterning material are removed from the top surface of the metal hard mask 108 or from regions within the upper region 116C to form a second pattern on the die surface for etching vias. After forming the pattern in the second patterned material, a second etching process is performed to form a via in the lower region 116D. As shown in dual damascene structure 101, lower region 116D includes a lower portion of dielectric material 110 and etch stop layer 112. The second patterned material is removed from the die surface after the etching process used to form the vias in the lower region 116D.
Dual damascene structure 101 is an unfilled structure in which two openings 116A and 116B extend through metal hard mask 108 to expose some of base conductive layer 114. Openings 116A and 116B of dual damascene structure 101 have different diameters at locations above the substrate. Moving down from the top surface of the metal hard mask, openings 116A and 116B have a first width 118A at the level of antireflective layer 102, a second width 118B at the level of metallic layer 104A, a third width 118C at the interface of dielectric layer 110 and antireflective layer 106, a fourth width 118D at the bottom of trench region 116C of openings 116A and 116B, a fifth width 118E at the top of via region 116D of openings 116A and 116B, and a sixth width 118F at the bottom of via region 116D. Moving downward again, first width 118A is greater than second width 118B, second width 118B is greater than third width 118C, third width 118C is greater than fourth width 118D, fourth width 118D is greater than fifth width 118E, and fifth width 118E is greater than sixth width 118F.
Sidewalls 122A of antireflective layer 102 are not vertically aligned with sidewalls 122B of metallic layer 104A as shown by the different widths 118A and 118B of opening 116A. Thus, at the interface 120 between the anti-reflective layer 102 and the metallic layer 104A, a step or "kink" (kink) is provided such that the top surface 124 of the metallic layer is exposed within the opening of the dual damascene structure. The deposition of the seed layer of conductive material into the dual damascene structure opening proceeds more rapidly at the location of the step at the exposed top surface 124 while exposing the top surface 124 of the metallic layer 104A. Thus, during deposition of the seed layer, the seed layer grows non-uniformly. The locations where seed layer growth is fastest occur at the locations of exposed top surface 124 such that after seed layer deposition, the openings of the dual damascene structure have a smaller diameter than the lower portions of the dual damascene structure. In the present disclosure, method 500 describes a process for forming an interconnect structure without the non-uniform seed layer deposition described above.
According to some embodiments, method 500 includes an operation 520 in which a portion of a metal hard mask is modified to produce sloped sidewalls. In operation 520, the metal hard mask is modified by: the metal hard mask is processed to diffuse non-metal atoms into the metallic layer (or metal layer in some embodiments) in order to produce a material stack having different lattice constants at different locations in the material stack. As the lattice constant of a material changes, the dimensions of the material also change. In the present disclosure, the addition of non-metallic atoms to a metal layer or a metallic layer increases the lattice constant and corresponds to the metallic layer swelling or expanding upon incorporation of the non-metallic atoms.
Treating the metal hard mask includes an annealing process and/or a plasma process for heating the metal hard mask. The plasma process also includes generating ionized atoms over a surface of the semiconductor device during the process, the ionized atoms penetrating into one or more layers of the metal hard mask to change a composition and shape of the metal hard mask. As described above, the new layer or poisoned layer (poisoned layer) includes the composition of both the metallic layer and the anti-reflective layer, and has sloped sidewalls in place of the steps or exposed upper surface 124 of the metallic layer 104A. Poisoning a layer or material refers to modifying a layer by diffusion of atoms from an adjacent layer into the poisoned layer.
Fig. 1B is a cross-sectional view of the semiconductor device 150 during a fabrication process according to some embodiments. Elements of fig. 1B that correspond to elements of fig. 1A have the same reference numerals. Those of ordinary skill in the art will appreciate that the present disclosure is directed to other embodiments different from those illustrated herein and that the features described herein are for convenience in describing the scope of the present disclosure and methods of fabricating semiconductor devices.
Fig. 1B includes a metal hard mask 104B with a non-metal atom treated surface 104C. According to some embodiments, a metallic hard mask 104B is deposited over the dielectric layer 110 and then treated with non-metallic atoms to modify the interface between the metallic layer and the one or more antireflective layers such that a portion of the metallic hard mask 104B is converted into a metallic region 104C rich in non-metallic atoms. In some embodiments, the process of adding non-metal atoms to a layer including a metal hard mask is referred to as poisoning (poisoning) the layer. In some embodiments, the metal hard mask 104B is enriched with non-metal atoms by: the sidewalls 122B of the metal hard mask 104B are exposed to the plasma of dissociated non-metal atoms in the absence of oxygen, such that atoms generated in the plasma are accelerated toward the exposed surface of the metal hard mask and penetrate into the metal hard mask. In some embodiments, the non-metal atom is a nitrogen atom. In some embodiments, the non-metallic atom is a mixture of nitrogen and oxygen. For the following discussion, the non-metal atom discussed is nitrogen, although other atoms are envisioned in this disclosure.
The addition of nitrogen to the metal hard mask 104 changes the chemical composition of the metal hard mask layer and changes the lattice constant of the material. According to an embodiment, the lattice constant of a material determines the amount of strain in the material, as the material transitions between layers of other materials above and below the material having the modified lattice. In some embodiments, adding material to modify the lattice constant of the material may cause the material to expand or increase in size because after modification (e.g., adding nitrogen to the metal hard mask), the lattice constant is greater than before modification. In some embodiments, the addition of non-metallic atoms to a metal hard mask shrinks the lattice constant, causing the material to shrink. In some embodiments, the metal hard mask is "poisoned" by adding nitrogen from a nitrogen-rich plasma before antireflective layer 106 is opened to expose substrate 110. In some embodiments, the metal hard mask is "poisoned" by adding nitrogen from a nitrogen-rich plasma after antireflective layer 106 has been opened and substrate 110 is exposed to the plasma. Exposing the substrate 110 to the nitrogen-rich plasma modifies exposed portions of the substrate 110 in addition to the exposed sidewalls of the metallic hard mask layer 104B. Poisoning metallic hard mask layer 104B prior to opening antireflective layer 106 prevents modification of the chemical composition and physical structure of substrate 110, making the etch process more uniform and faster (as compared to the substrate being nitrogen rich) in forming the interconnect openings (see 116A and 116B).
The nitrogen-rich region 104C covers the entire exposed top and sidewalls of the metal hardmask material located in the opening 116A. The nitrogen-rich region 104D covers the exposed top and upper portions of the sidewalls of the metal hardmask material in the opening 116B. The extent of coverage of the nitrogen-rich regions on the sidewalls of the metal hard mask 104B varies with the plasma characteristics (e.g., ion acceleration characteristics) of the plasma used to generate the dissociated nitrogen atoms. As the etching plasma becomes more anisotropic, sidewall coverage increases.
Fig. 2 is a cross-sectional view of a semiconductor device 200 having a sloped sidewall profile during a fabrication process according to some embodiments. Elements of fig. 2 that are similar to elements of fig. 1 described above have the same reference numeral (increased by 100). The sidewalls of the metal hard mask are modified by: the antireflection layer and the metallic layer are heated to allow the compounds from the antireflection layer and the metallic layer to permeate each other. Thus, the anti-reflective layer 202 and the metallic layer 204, which are directly opposite each other in fig. 1, are separated from each other in fig. 2 by the poisoned layer 203. The anti-reflective layer 202 has approximately vertical sidewalls 221A. The metallic layer 204 has approximately vertical sidewalls 221C. The poisoned layer 203 has a non-vertical but inclined poisoned layer sidewall 221B bridging the space between the sidewall 221A and the sidewall 221C, the sidewall 221A and the sidewall 221C being laterally separated from each other. The slope of sidewall 221C is approximately the same as the slope of sidewall 221D of the trench region in dielectric 210. In some embodiments, the slope of sidewall 221C is different from the slope of sidewall 221D. Sidewall 221F is an upper portion of a sidewall of a via region of the interconnect structure openings 216A/216B, and sidewall 221G is a sidewall of a lower portion of the via region of the interconnect structure. The exposed surface 223 of the base connector layer 214 is located at the bottom of the interconnect structures 216A and 216B. Sidewall 221E is located between sidewalls 221D and 221F. In some embodiments, angle 225 is in the range of 10 degrees to 70 degrees, although other angles are also contemplated within the scope of the present disclosure. By theory and concept, interconnect structures having an angle 225 of less than 20 ° are prone to void formation in the metal fill to the interconnect structure. In some embodiments, for angle values less than 20 °, the seed layer deposition becomes sporadic or non-uniform in the lower portion of the interconnect structure (e.g., along the portion of sidewall 221F). In embodiments of the interconnect structure where angle 225 is less than 20 °, the metal fill to the interconnect structure tends to form voids because material accumulates unevenly at the corners between sidewalls 221E and 221F.
In some embodiments, modifying the metal hard mask sidewalls or poisoning the layers of the metal hard mask includes one or more steps related to annealing and/or processing the metal hard mask in a plasma. Where metal hard mask poisoning occurs by annealing, the annealing step includes one or more of Rapid Thermal Processing (RTP), pulsed laser annealing, or other rapid annealing processes that facilitate inter-layer diffusion of atoms without causing melting of one or more layers of the metal hard mask. Annealing or rapid thermal processing of the metal hard mask layer involves heating the metal hard mask to a temperature of 600 to 900 degrees celsius for a period of 60 seconds. In some embodiments, the elevated temperature from 600 ℃ to 700 ℃ is maintained for a period of time from 40 seconds to 60 seconds. In some embodiments, the elevated temperature from 700 ℃ to 800 ℃ is maintained for a period of time from 20 seconds to 40 seconds. In some embodiments, the elevated temperature from 800 ℃ to 900 ℃ is maintained for a period of 10 seconds to 20 seconds. In some embodiments, the elevated temperature from 900 ℃ to 1000 ℃ is maintained for a period of time from 1 second to 10 seconds. In some embodiments, to facilitate diffusion of atoms without melting the metallic hard mask layer, the thermal treatment is performed at a temperature above 1000 ℃, and an exposure time of less than one second is employed at the peak temperature. In some cases, the peak temperature of the laser annealing process reaches above 1300 ° and the exposure time is in the order of milliseconds or microseconds.
In some embodiments, modifying the metal hard mask sidewalls includes exposing the metal hard mask to a nitrogen-containing plasma after forming the interconnect opening. The nitrogen-containing plasma generates nitrogen ions in the plasma that contaminate the exposed antireflective layer coating or sidewalls and heats the metal hardmask to promote diffusion of the metal out of the metallic layer and into one or more antireflective layers present in the metal hardmask. Little or no etching occurs during the exposure of the metal hardmask to the nitrogen-containing plasma. Instead, nitrogen in the plasma is ionized and the nitrogen ions react with the exposed portions of the antireflective layer. The reflective layer (typically an organic layer) is susceptible to nitrogen absorption by the plasma or adjacent materials in the thin film stack.
Modifying the metal hard mask to form a poisoned layer in the metal hard mask includes forming the poisoned layer to have a thickness of about 0.1nm to about 10 nm. The poisoned layer less than 0.1nm does not have a sufficient vertical thickness to bridge the lateral gap between the anti-reflective layer and the sidewalls of the metallic layer in the metal hardmask. A poisoned layer with a thickness greater than 10nm increases the risk of melting the metal hard mask layer, making it more difficult to partially or completely remove the metal hard mask after depositing the conductive material into the interconnect opening. The poisoned layer (or poisoned metal layer) has a composition ratio of metal to non-metal atoms between 0.25:1 and 1: 1. At metal composition ratios less than 0.25:1, the sidewalls of the poisoned metal layer do not have a slope that avoids excessive collection of seed layer material. At metal composition ratios greater than 1:1, the sidewalls of the poisoned metal layer have slopes that avoid excessive collection of seed layer material, but the greater thickness of the poisoned metal layer does not promote a reduction in seed layer uniformity. A poisoned metal layer having a composition ratio of less than 0.25:1 may not sufficiently mix the metallic layer and the antireflective layer to achieve sloped sidewalls compatible with void-free bulk conductive material plating.
The metal compound in the metallic layer 104A has the chemical formula AxByWherein A is a metal and B is a non-metal atom. The metal compound (metallic layer) of the metal hard mask has a thickness of 1:1 to 1:3Composition ratio of metal to non-metal atoms (x: y). At a nitrogen composition ratio of the metallic layer of less than 1:1, there is insufficient nitrogen in the metallic layer to form a poisoned metallic layer exhibiting reduced seed layer material collection. At a nitrogen composition ratio of the metallic layer greater than 1:3, the metallic layer does not have sufficient metal to form a poisoned metallic layer with the antireflective layer. In some embodiments, the metal a is titanium (Ti) and the non-metal atom is nitrogen (N). In some embodiments, the metal atom a is titanium and the nonmetal is a mixture of nitrogen and oxygen (O), such that axByIs TixNyOz. In some embodiments, other combinations of metals and non-metals are used according to semiconductor manufacturing processes known to those skilled in the art.
The method 500 includes an operation 525 in which a conductive material is deposited into at least one opening in the dielectric layer. In the fabrication of dual damascene structures in integrated circuits, conductive material is deposited in several steps. One step of operation 525 is to sputter a seed layer of conductive material onto the top surface of the metal hard mask 308 and onto the sidewalls 221A-221G of the interconnect structure. Another step of operation 525 includes electroplating a conductive material into the interconnect opening (at least one opening in the dielectric layer). The seed layer (not shown) serves as one electrode for performing the electroplating process. Because the poisoned layer 203 has sloped sidewalls 221B, there is less likelihood of voids or pockets forming within the interconnect when electroplating of conductive material into the interconnect opening occurs, due to the absence of bonds (junctions) at levels of the interconnect opening corresponding to the level of the poisoned layer 203.
According to some embodiments, the seed layer (not shown) and the plated bulk conductive material are the same material. In some cases, the seed layer and the bulk plating conductive material are different materials. Conductive materials used to form dual damascene interconnect structures include copper and copper alloys. Copper alloys include copper mixed with aluminum, zinc, and other metals to promote uniform electrodeposition of material within the interconnect opening and to reduce the grain size of the plated conductive material. In some embodiments after operation 525, one or more layers on the dielectric layer are removed, such as by Chemical Mechanical Polishing (CMP), in order to prepare the integrated circuit for deposition of another dielectric material, such as a contact etch stop layer (for, e.g., dual damascene structures), or a dielectric layer in which the conductive lines are to be fabricated.
Fig. 3 is a cross-sectional view of a semiconductor device 300 having a copper interconnect structure 301, in accordance with some embodiments. Elements of fig. 3 that are similar to elements of fig. 2 above have the same reference numeral (increased by 100). In the interconnect structure 301, a conductive material covers the sides of the dual damascene structure opening and the top of the metal hard mask 308. Thus, interconnect structures 318A and 318B are electrically connected through planar conductive material 318C. Interconnect structures 318A and 316B have line regions 316C and via regions 316D. Region 316D of each interconnect structure is electrically connected to the base conductor 314.
Because the poisoned layer 303 has sloped sidewalls 321B, depositing a seed layer 326 (copper or copper alloy) of conductive material onto the sidewalls of the interconnect opening does not create pinch points at the top of the interconnect opening. By eliminating the formation of shrinkage at the top of the interconnect openings, interconnect structures 318A and 318B have no voids or recesses therein. In some embodiments, after etching through the dielectric material, a seed layer 326 is deposited into the interconnect openings (see elements 216A, 216B of fig. 2) to prevent oxidation of the exposed metal of the base conductor 314 (e.g., metal-filled vias or trenches in lower levels of the semiconductor device). By depositing the seed layer immediately after exposing the metal of the base conductor 314, the formation of metal oxides on the base conductor is reduced, which reduces the resistance at the interface at the bottom of the interconnect after metal filling occurs. In some embodiments, the seed layer covers the inner sidewalls of the anti-reflective layer 302, the poisoned layer 303, the metal hard mask 304, and the anti-reflective layer 306. In some embodiments, the poisoned layer 303 is an inner sidewall of the metal hard mask 304 (see element 104C of fig. 1B). In some embodiments, the poisoned layer is a top portion of the exposed metal hard mask 104 material (see element 104D of fig. 1B).
Fig. 4 is a cross-sectional view of a semiconductor device 400 having a copper interconnect structure 401, in accordance with some embodiments. The method 500 includes an operation 530, wherein the copper interconnects formed in the operation 530 are electrically isolated from each other. Electrical isolation of copper interconnect structures is achieved by a Chemical Mechanical Polishing (CMP) process performed on the top surface of the die or semiconductor wafer. Electrical isolation of copper interconnects is considered complete when there is significantly less material laterally placed between the interconnects (see interconnects 418A and 418B of fig. 4).
In fig. 4, elements similar to those previously described in fig. 1 share the same reference numeral (incremented by 300). Interconnects 418A and 418B extend through metal hardmask 408, dielectric material 410, etch stop layer 412 to make electrical connection with substrate conductive layer 414. The interconnect 418A has an upper portion 418A1, the upper portion 418A1 having a first width W1 at the top of the upper portion 418A 1. The first width corresponds to an uppermost portion of upper portion 418a1 that is at the same vertical distance from substrate 410 as compared to poisoned layer 403. The first width W1 is greater than the width of the remainder of the upper portion 418a 1. A stripe region 416C of dual damascene interconnect structures 418A and 418B is formed in the trench portion of the interconnect structure opening. The via regions 416D of the interconnect structures 418A and 418B extend through the lower region of the dielectric layer 410. The metal hard mask 408 shown in fig. 4 is optionally removed from the top surface of the dielectric layer 410, depending on the material of the metallic layer. In some embodiments, the metal hard mask 408 comprises a silicon nitride layer, and the metal hard mask remains after removing bulk conductive material (e.g., electroplated copper) from the top surface of the metal hard mask, thereby isolating the dual damascene interconnect structures from each other. The silicon nitride layer does not have a sufficiently high conductivity to allow current to flow between the interconnect structures. The metallic layer, comprising, for example, titanium nitride, has sufficient conductivity such that the metallic layer is removed to prevent leakage current between the interconnect structures. The metallic layer is removed from the top surface of dielectric layer 410 by, for example, Chemical Mechanical Polishing (CMP).
Fig. 6 is a cross-sectional view of various layers of an integrated circuit 600 during a fabrication process according to some embodiments. The present disclosure relates to integrated circuits formed by a method of smoothing sidewalls of an integrated circuit interconnect opening prior to filling the interconnect opening with metal to form an interconnect structure (e.g., a via in a dual damascene structure of a trench and a layer of the integrated circuit). The integrated circuit 600 has an interface 606 between the first layer 602 and the second layer 604. In some embodiments, the first layer is a metallic layer and the second layer is an antireflective layer. In some embodiments, the first layer is an antireflective layer and the second layer is a metallic layer. The metallic layer is a layer such as a metal nitride or metal oxynitride layer. In structure 601, the first and second layers are depicted before heat treatment to smooth the sidewalls. Structure 610 depicts a first layer 612 (compared to first layer 602) and a second layer 614 (compared to second layer 604) after the structure has undergone a thermal process. The thermal treatment of the structure 601 creates a "poisoned" layer at the location of the interface 601, where the materials from the first and second layers interdiffuse to form a third material or interface layer 616 with properties intermediate to those of the first and second layers 612, 614. The characteristics of the interface layer 616 that are intermediate to those of the first layer 612 and the second layer 614 are (1) chemical composition and (2) lattice constant. The chemical composition of the interface layer ranges from the composition of the first layer 612 at the top side of the interface layer to the chemical composition of the second layer 614 at the bottom side of the interface layer. The variation in chemical composition across the vertical thickness of the interface layer 616 causes the lattice constant of the interface film to vary across the vertical thickness of the interface. The intermediate layer smoothly transitions the sidewall profile from the first layer to the second layer by diffusing the materials of the two layers of film into each other to remove kinks associated with different opening diameters at different layers of the metal hardmask (e.g., metal/metallic layer, and one antireflective layer) in the interconnect layer openings (prior to metal deposition). In some embodiments, the first layer is a metallic layer (a metal layer, or a metal nitride layer) and the second layer is an antireflective layer. In some embodiments, the first layer is an antireflective layer and the second layer is a metallic layer. The heat treatment described in the method of the present disclosure serves to smooth kinks at the interface of the metallic layer and the antireflective layer, whether or not the antireflective layer of the metallic layer is on top of the film stack.
A method comprising the operations of: depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of the base conductive layer; modifying sidewalls of the metal hard mask opening; a conductive material is deposited in the metal hard mask opening and the at least one interconnect opening. In some embodiments, the method further comprises: portions of the conductive material on the top surface of the metal hard mask are removed. In some embodiments, the method further comprises: the metal hard mask is removed to electrically isolate the conductive material in each of the at least one interconnect opening. In some embodiments, depositing the metal hard mask further comprises: depositing a first anti-reflective layer over the dielectric layer; and depositing a metallic layer over the dielectric layer. In some embodiments, the method further comprises: a second antireflective layer is deposited over the dielectric layer such that the metallic layer is between the first antireflective layer and the second antireflective layer. In some embodiments, etching the at least one interconnect opening further comprises: etching at least one trench in the dielectric layer through the metal hard mask opening; depositing a layer of mask material over the metal hard mask and in the at least one trench; patterning the mask material to form an opening through the mask material in the at least one trench; at least one via is etched through the dielectric layer to expose the base conductive layer underlying the dielectric layer. In some embodiments, depositing the conductive material further comprises: a seed layer is deposited on the sidewalls of the metal hard mask, the trench sidewalls of the at least one trench, and the via sidewalls of the at least one via. In some embodiments, modifying the sidewalls of the metal hard mask opening further comprises: the metal hard mask is annealed to diffuse metal atoms of the metallic layer into the first anti-reflective layer, wherein the metallic layer is between the first anti-reflective layer and the dielectric layer. In some embodiments, modifying the sidewalls of the metal hard mask opening further comprises: the first antireflective layer and the metallic layer are exposed to a nitrogen-containing plasma.
Aspects of the present disclosure relate to a method of fabricating an interconnect structure, including: depositing a dielectric layer over the first copper interconnect structure; depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask; etching a first portion of an interconnect structure opening in a dielectric layer; etching a second portion of the interconnect structure opening in the dielectric layer; poisoning a layer of the metal hard mask located over the dielectric layer; a conductive material is deposited in the interconnect structure opening through the metal hard mask opening. In some embodiments, depositing the metal hard mask further comprises: a first antireflective layer is deposited on the metallic layer over the dielectric layer. In some embodiments, poisoning the layer of the metal hard mask further comprises: the metal hard mask is annealed to diffuse the metallic layer and the first anti-reflective layer into each other. In some embodiments, poisoning the layer of the metal hard mask further comprises: the layer of the metal hardmask is exposed to a nitrogen-containing plasma. In some embodiments, depositing the conductive material further comprises: a copper seed layer is sputtered on the sidewalls of the poisoned metal hard mask and the sidewalls of the interconnect structure opening that are located in the dielectric layer. In some embodiments, etching the second portion of the interconnect structure opening in the dielectric layer further comprises: depositing a mask layer over the metal hard mask and the first portion of the interconnect structure opening; patterning the mask layer such that the opening extends into a first portion of the interconnect structure; and etching a lower portion of the dielectric layer.
Aspects of the present disclosure relate to a device, comprising: a metal hard mask layer located above the dielectric layer; and an interconnect structure extending through the metal hardmask layer and the dielectric layer and electrically connected to the base conductive layer located below the dielectric layer; wherein the metal hard mask layer has a poisoned layer therein. In some embodiments of the device, the metal hard mask further comprises: a metallic layer against the poisoned layer. In some embodiments, the interconnect structure has a first diameter at a top layer of the metal hard mask, a second diameter at a metallic layer of the metal hard mask, and a third diameter at a poisoned layer of the metal hard mask, wherein the third diameter is less than the first diameter and greater than the second diameter. In some embodiments, the interconnect structure further comprises copper or a copper alloy. In some embodiments, the metallic layer further comprises titanium nitride.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Example 1. a method of fabricating an interconnect structure, comprising: depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer; etching at least one interconnect opening in the dielectric layer to expose a top surface of a base conductive layer; modifying sidewalls of the metal hard mask opening by adding non-metal atoms to a metallic layer of the metal hard mask; and depositing a conductive material in the metal hard mask opening and the at least one interconnect opening.
Example 2. the method of example 1, further comprising: removing portions of the conductive material on a top surface of the metal hard mask.
Example 3. the method of example 2, further comprising: the metal hard mask is removed.
Example 4. the method of example 1, wherein depositing the metal hard mask further comprises: depositing a first anti-reflective layer over the dielectric layer; and depositing the metallic layer over the dielectric layer.
Example 5. the method of example 4, wherein modifying the sidewalls of the metal hard mask opening further comprises: annealing the metal hard mask to diffuse metal atoms of the metallic layer into the first anti-reflective layer, wherein the metallic layer is between the first anti-reflective layer and the dielectric layer.
Example 6. the method of example 4, wherein modifying the sidewalls of the metal hard mask opening further comprises: exposing the first anti-reflective layer and the metallic layer to a nitrogen-containing plasma.
Example 7. the method of example 4, further comprising: depositing a second anti-reflective layer over the dielectric layer such that the metallic layer is between the first anti-reflective layer and the second anti-reflective layer.
Example 8 the method of example 1, wherein etching the at least one interconnect opening further comprises: etching at least one trench in the dielectric layer through the metal hard mask opening; depositing a layer of mask material over the metal hard mask and in the at least one trench; patterning the mask material to form an opening through the mask material in the at least one trench; and etching at least one via through the dielectric layer to expose the base conductive layer underlying the dielectric layer.
Example 9. the method of example 1, further comprising: changing a slope of the metal hard mask layer by poisoning the metal hard mask layer.
Example 10 a method of fabricating an interconnect structure, comprising: depositing a dielectric layer over the first copper interconnect structure; depositing a metal hard mask over the dielectric layer; etching a metal hard mask opening in the metal hard mask; etching a first portion of an interconnect structure opening in the dielectric layer; etching a second portion of the interconnect structure opening in the dielectric layer; modifying sidewalls of the metal hard mask opening by heat treating the metal hard mask; and depositing a conductive material in the interconnect structure opening through the metal hard mask opening.
Example 11 the method of example 10, wherein depositing the metal hard mask further comprises: a first antireflective layer is deposited over the dielectric layer, a metallic layer is deposited over the first antireflective layer, and a second antireflective layer is deposited over the metallic layer.
Example 12. the method of example 11, wherein heat treating the metal hard mask further comprises: annealing the metal hardmask to a temperature between 600 degrees Celsius and 1000 degrees Celsius for an annealing time in a range from 60 seconds to 1 second.
The method of example 10, wherein poisoning the layer of the metal hard mask further comprises: exposing the layer of the metal hardmask to a nitrogen-containing plasma.
Example 14. the method of example 10, wherein depositing the conductive material further comprises: a copper seed layer is sputtered on the sidewalls of the poisoned metal hard mask and the sidewalls of the interconnect structure opening that are located in the dielectric layer.
Example 5. the method of example 10, further comprising: the slope of the sidewalls of the metal hard mask layer is changed by a heat treatment.
Example 16. a method of fabricating an interconnect structure, comprising: depositing a dielectric layer over a substrate; depositing a hard mask layer over the dielectric layer; exposing a top surface of the dielectric layer through a hard mask layer opening; etching an interconnect opening in the dielectric layer; modifying sidewalls of the hard mask layer opening; and filling the interconnect opening with a conductive material through the hard mask layer opening having the modified sidewall.
The method of example 17. according to example 16, wherein depositing the hard mask layer further comprises: an antireflective layer is deposited over the dielectric layer, and a metallic layer is deposited over the dielectric layer.
Example 18 the method of example 17, wherein modifying sidewalls of the hardmask layer opening further comprises: interlayer diffusion of the anti-reflection layer and the metallic layer.
Example 19 the method of example 16, wherein modifying sidewalls of the hard mask layer opening further comprises: and annealing the hard mask layer.
Example 20. the method of example 18, wherein filling the interconnect opening further comprises: depositing a seed layer on dielectric layer sidewalls and the hard mask layer openings having modified sidewalls; and electroplating a conductive material over the seed layer.

Claims (10)

1. A method of fabricating an interconnect structure, comprising:
depositing a metal hard mask over the dielectric layer;
etching a metal hard mask opening in the metal hard mask to expose a top surface of the dielectric layer;
etching at least one interconnect opening in the dielectric layer to expose a top surface of a base conductive layer;
modifying sidewalls of the metal hard mask opening by adding non-metal atoms to a metallic layer of the metal hard mask; and
depositing a conductive material in the metal hard mask opening and the at least one interconnect opening.
2. The method of claim 1, further comprising: removing portions of the conductive material on a top surface of the metal hard mask.
3. The method of claim 2, further comprising: the metal hard mask is removed.
4. The method of claim 1, wherein depositing a metal hard mask further comprises:
depositing a first anti-reflective layer over the dielectric layer; and
depositing the metallic layer over the dielectric layer.
5. The method of claim 4, wherein modifying sidewalls of the metal hard mask opening further comprises: annealing the metal hard mask to diffuse metal atoms of the metallic layer into the first anti-reflective layer, wherein the metallic layer is between the first anti-reflective layer and the dielectric layer.
6. The method of claim 4, wherein modifying sidewalls of the metal hard mask opening further comprises: exposing the first anti-reflective layer and the metallic layer to a nitrogen-containing plasma.
7. The method of claim 4, further comprising: depositing a second anti-reflective layer over the dielectric layer such that the metallic layer is between the first anti-reflective layer and the second anti-reflective layer.
8. The method of claim 1, wherein etching the at least one interconnect opening further comprises:
etching at least one trench in the dielectric layer through the metal hard mask opening;
depositing a layer of mask material over the metal hard mask and in the at least one trench;
patterning the mask material to form an opening through the mask material in the at least one trench; and
at least one via is etched through the dielectric layer to expose the base conductive layer underlying the dielectric layer.
9. A method of fabricating an interconnect structure, comprising:
depositing a dielectric layer over the first copper interconnect structure;
depositing a metal hard mask over the dielectric layer;
etching a metal hard mask opening in the metal hard mask;
etching a first portion of an interconnect structure opening in the dielectric layer;
etching a second portion of the interconnect structure opening in the dielectric layer;
modifying sidewalls of the metal hard mask opening by heat treating the metal hard mask; and
depositing a conductive material in the interconnect structure opening through the metal hard mask opening.
10. A method of fabricating an interconnect structure, comprising:
depositing a dielectric layer over a substrate;
depositing a hard mask layer over the dielectric layer;
exposing a top surface of the dielectric layer through a hard mask layer opening;
etching an interconnect opening in the dielectric layer;
modifying sidewalls of the hard mask layer opening; and
filling the interconnect opening with a conductive material through the hard mask layer opening having a modified sidewall.
CN202010013805.5A 2020-01-07 2020-01-07 Method for manufacturing interconnection structure Pending CN113161284A (en)

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