CN113160735B - Level conversion chip and display device - Google Patents
Level conversion chip and display device Download PDFInfo
- Publication number
- CN113160735B CN113160735B CN202110400415.8A CN202110400415A CN113160735B CN 113160735 B CN113160735 B CN 113160735B CN 202110400415 A CN202110400415 A CN 202110400415A CN 113160735 B CN113160735 B CN 113160735B
- Authority
- CN
- China
- Prior art keywords
- clock
- output
- output channel
- low
- level signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 18
- 238000001514 detection method Methods 0.000 claims abstract description 46
- 238000010586 diagram Methods 0.000 description 11
- 230000000630 rising effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a level conversion chip and a display device; the level conversion chip controls the output low-frequency clock of the clock output channel by using a detection circuit in the clock output channel according to the level signal of the input low-frequency clock of the clock output channel and the level signal of the output low-frequency clock of the symmetrical clock output channel, so that the level signal of the output low-frequency clock of the clock output channel and the level signal of the output low-frequency clock of the symmetrical clock output channel are not both high at the same moment; the invention solves the technical problem that the time duration of a low-frequency clock high-level signal is too long when a high-frequency clock pulse signal is lost by a time sequence control chip, thereby avoiding equipment damage caused by large current and the like.
Description
Technical Field
The invention relates to the technical field of display, in particular to a level conversion chip and a display device.
Background
When the display panel of the current display device is driven by the GOA method (the gate driving circuit is built on the panel, and a separate gate driving chip is not needed), the display device must be configured with a level conversion chip.
In practical applications, the level shift chip generates a scanning signal (hereinafter referred to as a low-frequency clock) required by the display panel in a two-in and multiple-out manner, that is, 2M low-frequency clock signals are generated and output according to two input high-frequency clock signals, the 2M low-frequency clock signals are respectively input into a corresponding number of clock signal lines, and 2N GOA units are connected to the clock signal lines.
However, when the pulse signal of the high frequency clock is lost, the duration of the high level signal of some low frequency clocks is too long, and further, some GOA units generate large current, which results in the damage of the device.
Specifically, this technical problem will be described in detail by taking an example in which 2M is 4 (i.e., M is 2). As shown in fig. 1, the timing control chip 10 provides 2 high frequency clocks CK1 and CK2 to the level shift chip 20, CK2 lags behind CK1 by 1.5 periods T, the level shift chip 20 outputs 4 low frequency clocks CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4 according to the high frequency clocks CK1 and CK2, and inputs them to the display panel 30 through clock signal lines L1 to L4, respectively, the cascade-connected GOA units 31(N, etc. in fig. 1) in the display panel 30 are connected to the clock signal lines L1 to L4 step by step in the manner shown in fig. 1, and output gate scan signals g (N) based on the high level and the low level of the low frequency clocks, specifically, outputs the high level when the corresponding low frequency clock is the high level, and outputs the low level when the corresponding low frequency clock is the low level.
The principle that the level shift chip 20 outputs 4 low frequency clocks CLKOUT1, CLKOUT2, CLKOUT3 and CLKOUT4 according to the high frequency clocks CK1 and CK2 is shown in fig. 2, wherein a rising edge of the high frequency clock signal CK1 will sequentially trigger rising edges of the low frequency clocks CLKOUT1, CLKOUT2, CLKOUT3 and CLKOUT4, and a falling edge of the high frequency clock signal CK2 will sequentially trigger falling edges of the low frequency clocks CLKOUT1, CLKOUT2, CLKOUT3 and CLKOUT 4.
In the actual working process, the absence of part of pulse signals of the high-frequency clock signal CK can cause the high level duration of some CLKOUT to be overlong, so that the associated CLKOUT has high level coincidence; as shown in fig. 3, the high frequency clock CK2 misses one pulse signal, resulting in CLKOUT1 and CLKOUT3 being high simultaneously for a period t.
The current GOA unit can adopt the circuit diagram shown in fig. 4, the output G (N) of the GOA unit 31(N) is subject to the clock signals of the output G (N-2) of the GOA unit 31(N-2), the output G (N +2) of the GOA unit 31(N +2), and the connected clock signal line L3, since the GOA unit 31(N-2) and the GOA unit 31(N +2) are both connected to the clock signal line L1, the present application refers to the clock signal line L1 and the clock signal line L3 as symmetric clock signal lines, and the corresponding clock channels of the clock signal line L1 and the clock signal line L3 as symmetric clock channels.
As shown in fig. 3 and 4, CLKOUT1 and CLKOUT3 are both at a high level during the T period, CLKOUT1 controls the output of both the GOA unit 31(N-2) and the GOA unit 31(N +2) to be high through the clock signal line L1, so that the transistors T21 and T31 are turned on, and since CLKOUT3 is also at a high level at this time, that is, the CK signal of the GOA unit 31(N) is at a high level, which is equivalent to the CK directly short-circuiting to the ground (Vss signal in fig. 4), a large current may be generated, and the device chip may be damaged.
Therefore, the current level shift chip has a technical problem that the duration of a high-level signal of a low-frequency clock generated due to the loss of a high-frequency clock pulse signal is too long, and needs to be solved.
Disclosure of Invention
The invention provides a level conversion chip and a display device, which are used for solving the technical problem that the high-level signal duration of a low-frequency clock is too long due to the loss of a high-frequency clock pulse signal in a current time sequence control chip.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a level conversion chip, which is applied to a display panel and comprises:
at least two clock input channels for inputting a high frequency clock;
2M clock output channels for respectively outputting 1 low-frequency clock;
the chip body is used for respectively inputting corresponding low-frequency clocks to the 2M clock output channels according to the high-frequency clocks;
at least a detection circuit is arranged in an m1 th clock output channel, and the detection circuit is used for controlling the output low-frequency clock of the m1 th clock output channel according to the level signal of the input low-frequency clock of the m1 th clock output channel and the level signal of the output low-frequency clock of the m2 th clock output channel, so that the level signal of the output low-frequency clock of the m1 th clock output channel and the level signal of the output low-frequency clock of the m2 th clock output channel are not both high at the same moment; the M1 and M2 belong to 1-2M, and the M1 clock output channel and the M2 clock output channel are symmetric clock channels with each other.
In the level shift chip of the present invention, the detection circuit is configured to control the level signal of the low frequency clock output from the m 1-th clock output channel not to be high when the level signal of the low frequency clock input from the m 1-th clock output channel is high and the level signal of the low frequency clock output from the m 2-th clock output channel is high.
In the level shift chip of the present invention, the detection circuit is configured to control the level signal of the low frequency clock output from the m 1-th clock output channel to be low when the level signal of the low frequency clock input from the m 1-th clock output channel is high and the level signal of the low frequency clock output from the m 2-th clock output channel is high.
In the level shift chip of the present invention, the detection circuit is configured to control the output terminal of the m 1-th clock output channel to stop outputting the clock when the level signal of the input low frequency clock of the m 1-th clock output channel is high and the level signal of the output low frequency clock of the m 2-th clock output channel is high.
In the level shift chip of the present invention, the detection circuit is configured to control the output terminal of the m 1-th clock output channel to output an error signal when the level signal of the input low frequency clock of the m 1-th clock output channel is high and the level signal of the output low frequency clock of the m 2-th clock output channel is high.
In the level shift chip of the present invention, the detection circuit is further configured to control the output terminal of the m1 th clock output channel to stop outputting the error signal when the reset signal is detected.
In the level shift chip of the present invention, the detection circuits are disposed in all the clock output channels.
In the level shift chip of the present invention, the detection circuit includes an inverter and a first multiplier; wherein:
the input end of the inverter is electrically connected with the output end of the m2 clock output channel, and the output end of the inverter is electrically connected with the first input end of the first multiplier;
the second input end of the first multiplier is electrically connected with the input end of the m1 clock output channel, and the output end of the first multiplier is electrically connected with the output end of the m1 clock output channel.
In the level shift chip of the present invention, the detection circuit further includes a second multiplier; wherein:
the first input end of the second multiplier is electrically connected with the input end of the m1 clock output channel, the second input end of the second multiplier is electrically connected with the output end of the m2 clock output channel, and the output end of the second multiplier is electrically connected with the output end of the m1 clock output channel.
Meanwhile, the invention provides a display device which comprises the level conversion chip.
Has the advantages that: the invention provides a level conversion chip and a display device, wherein the level conversion chip controls an output low-frequency clock of a clock output channel by a detection circuit in the clock output channel according to a level signal of an input low-frequency clock of the clock output channel and a level signal of an output low-frequency clock of a symmetrical clock output channel by utilizing the detection circuit, so that the level signal of the output low-frequency clock of the clock output channel and the level signal of the output low-frequency clock of the symmetrical clock output channel are not both high at the same moment; the technical problem that the high-level signal duration of a low-frequency clock is too long when a high-frequency clock pulse signal is lost by a time sequence control chip is solved, and equipment damage caused by large current and the like is avoided.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a display device;
FIG. 2 is a timing diagram of the operation of the current level shift chip when the high frequency clock is normal;
FIG. 3 is a timing diagram illustrating the operation of the current level shift chip when the high frequency clock is abnormal;
FIG. 4 is a schematic circuit diagram of a GOA unit;
fig. 5 is a circuit diagram of a level shift chip according to an embodiment of the invention;
FIG. 6 is a circuit diagram of a detection circuit according to an embodiment of the present invention;
fig. 7 to 9 are timing diagrams of three operations of the level shift chip according to the embodiment of the present invention after performing the abnormal correction;
fig. 10 is another circuit diagram of a level shift chip according to an embodiment of the invention;
FIG. 11 is a schematic view of another structure of the display device;
FIG. 12 is another schematic circuit diagram of a GOA unit;
fig. 13 is a schematic circuit diagram of a level shift chip according to another embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The embodiment of the invention can solve the technical problem that the current level conversion chip has large current caused by loss of high-frequency clock signal pulse signals.
As shown in fig. 5, an embodiment of the present invention provides a level shift chip, where the level shift chip 20 includes:
at least two clock input channels 201 for inputting a high frequency clock CK;
2M clock output channels 202 (including the clock output channel 202-1 to the clock output channel 202-2M in fig. 5) for respectively outputting 1 low frequency clock CLKOUT (CLKOUT 1-L to CLKOUT2M-L output from the output terminal b-1 to the output terminal b-2M in fig. 5); the ith clock output channel and the M + i clock output channel are symmetric clock channels, M is a positive integer greater than 1, and i belongs to 1-M; each clock output channel 202 includes an input terminal a (i.e., input terminal a-1 through input terminal a-2M in fig. 5) and an output terminal b (i.e., output terminal b-1 through output terminal b-2M in fig. 5);
the chip body 203 is configured to input corresponding low-frequency clocks to the 2M clock output channels through input ends a (i.e., input ends a-1 to a-2M in fig. 5) according to the high-frequency clocks; the clock signal control method is specifically used for sequentially triggering rising edges of low-frequency clocks CLKOUT1-F, CLKOUTi-F, CLKOUTN-F, CLKOUT2M-F and the like to be output based on rising edges of a high-frequency clock signal CK1, and sequentially triggering falling edges of low-frequency clocks CLKOUT1-F, CLKOUTi-F, CLKOUTN-F, CLKOUT2M-F and the like to be output based on falling edges of a high-frequency clock signal CK 2;
wherein, at least the M1 th clock output channel (i.e. any one of 1 to 2M in FIG. 5, M is greater than or equal to 2) is provided with a detection circuit 204, the detection circuit 204 is used for controlling the output low frequency clock of the M1 th clock output channel according to the level signal of the input low frequency clock of the M1 th clock output channel (the level signals of CLKOUT1-F to CLKOUT2M-F input to the input ends a-1 to a-2M in FIG. 5) and the level signal of the output low frequency clock of the M2 th clock output channel (the level signals of CLKOUT1-L to CLKOUT2M-L output from the output ends b-1 to b-2M in FIG. 5), so that the level signal of the output low frequency clock of the m1 th clock output channel and the level signal of the output low frequency clock of the m2 th clock output channel are not both high at the same time.
In FIG. 5, the same numbers indicate electrical connections, such as the input b-M +1 of the circuit 204 in the clock channel 202-1 and the output b-M +1 of the circuit 204 in the clock channel 202-M +1, which are similar to each other.
In the embodiment of the present application, the manner of adjusting the low-frequency clock signal may control the output of one or two channels of the symmetric clock channels, for example, the symmetric clock channels 202-i and 202-M + i may only control the output of the clock channel 202-i, may only control the output of the clock channel 202-M + i, and may also simultaneously control the outputs of the clock channels 202-i and 202-M + i, which is described below by taking only the output of the clock channel 202-i as an example, and the rest is similar to the above and is not repeated.
Wherein the M1 and M2 belong to 1-2M, and the M1 clock output channel and the M2 clock output channel are symmetric clock channels; for example, in the GOA layout circuit shown in fig. 1 and 5, when M1 is i, M2 is M + i, and when M1 is M + i, M2 is i, i belonging to 1 to M; of course, in other GOA layout circuits, other symmetrical schemes are possible, and only the specific analysis of the GOA circuit shown in fig. 4 is needed.
In one embodiment, the detection circuit may be disposed only in a clock output channel where a large current is likely to occur, for example, only in a clock output channel corresponding to the clock signal line L3 in fig. 1, so as to reduce chip manufacturing cost.
In an embodiment, the detection circuits are arranged in all the clock output channels, so that the detection control can be performed on the clocks output by all the clock output channels, the large current caused by the loss of the pulse signals of the high-frequency clock in any scene can be avoided, and the effect is better.
In the level shift chip provided in this embodiment, the detection circuit 204 is arranged in the clock output channel 202, and the detection circuit 204 is utilized to control the output low-frequency clock of the clock output channel according to the level signal of the input low-frequency clock of the clock output channel and the level signal of the output low-frequency clock of the symmetric clock output channel, so that the level signal of the output low-frequency clock of the clock output channel and the level signal of the output low-frequency clock of the symmetric clock output channel are not both high at the same time; the technical problem that the high-level signal duration of a low-frequency clock is too long when a high-frequency clock pulse signal is lost by a time sequence control chip is solved, and equipment damage caused by large current and the like is avoided.
In one embodiment, the detection circuit is configured to control the level signal of the output low frequency clock of the m 1-th clock output channel not to be high when the level signal of the input low frequency clock of the m 1-th clock output channel is high and the level signal of the output low frequency clock of the m 2-th clock output channel is high. The level signal is not high, and various implementations are possible, for example, the following modes, such as the mode that the level signal is low, an error signal, and no electric signal is output, and the like, as long as the modes can realize that the output clocks of the symmetric clock channels are not all high at the same time.
In one embodiment, the detection circuit is configured to control the level signal of the output low frequency clock of the m 1-th clock output channel to be low when the level signal of the input low frequency clock of the m 1-th clock output channel is high and the level signal of the output low frequency clock of the m 2-th clock output channel is high.
For example, as shown in fig. 7, when M is 2, the pulse signal at the same position as the high frequency clock in fig. 3 is missing, and the output low frequency clock of the 3 rd clock output channel is forcibly adjusted to the low level (i.e., VSS) during the t period; at this time, in the circuit shown in fig. 4, the gate voltages of the transistors T11, T31, and T41 are low, the transistors T11, T31, and T41 are off, the CLKOUT1 is disconnected from Vss, and no large current is generated, the transistor T21 is turned on based on the voltage of the capacitor C, the output g (N) of the GOA cell 31(N) is at a high potential corresponding to the CLKOUT1, the corresponding pixel circuit is turned on, and the display device operates normally.
In the level shift chip of the present invention, the detection circuit is configured to control the output terminal of the m 1-th clock output channel to stop outputting the clock until the next clock cycle (i.e., the period T of the low frequency clock) when the level signal of the input low frequency clock of the m 1-th clock output channel is high and the level signal of the output low frequency clock of the m 2-th clock output channel is high.
For example, as shown in fig. 8, when M is 2, the pulse signal at the same position as the high frequency clock in fig. 3 is missing, and the 3 rd clock output channel stops outputting the low frequency clock in the t period; at this time, in the circuit shown in fig. 4, the gates of the transistors T11, T31, and T41 are not charged, the transistors T11, T31, and T41 are turned off, the CLKOUT1 is disconnected from Vss, and no large current is generated, the transistor T21 is turned on based on the voltage of the capacitor C, the output g (N) of the GOA cell 31(N) is at a high potential corresponding to the CLKOUT1, the corresponding pixel circuit is turned on, and the display device operates normally.
In the level shift chip of the present invention, the detection circuit is configured to control the output terminal of the m 1-th clock output channel to output an error signal until a next clock cycle (i.e., a period T of the low frequency clock) when the level signal of the input low frequency clock of the m 1-th clock output channel is high and the level signal of the output low frequency clock of the m 2-th clock output channel is high.
For example, as shown in fig. 9, when M is 2, the pulse signal at the same position as the high frequency clock in fig. 3 is missing, and during the period t, the 3 rd clock output channel outputs an error signal (generally, a voltage of 0V or less); at this time, in the circuit shown in fig. 4, the gates of the transistors T11, T31, and T41 are smaller than 0, the transistors T11, T31, and T41 are turned off, the CLKOUT1 is disconnected from Vss, and no large current is generated, the transistor T21 is turned on based on the voltage of the capacitor C, the output g (N) of the GOA cell 31(N) is at a high potential corresponding to the CLKOUT1, the corresponding pixel circuit is turned on, and the display device operates normally.
In the level shift chip of the present invention, the detection circuit is further configured to control the output terminal of the m1 th clock output channel to stop outputting the error signal when the reset signal is detected. For example, the reset signal may be periodically generated by the chip body, and the detection circuit controls the output terminal of the m1 th clock output channel to stop outputting the error signal and normally output the low frequency clock when detecting the reset signal.
In one embodiment, the detection circuit is disposed in all clock output channels.
As shown in fig. 6, in one embodiment, for the ith clock output channel, the symmetric clock output channel is the clock output channel M + i, and the detection circuit 204 in the ith clock output channel includes an inverter 61 and a first multiplier 62; wherein:
the input end of the inverter 61 is electrically connected to the output end b-M + i of the M + i-th clock output channel, and the output end of the inverter 61 is electrically connected to the first input end of the first multiplier 62;
the second input terminal of the first multiplier 62 is electrically connected to the input terminals a-i of the ith clock output channel, and the output terminal of the first multiplier 62 is electrically connected to the output terminals b-i of the ith clock output channel.
In one embodiment, as shown in fig. 6, the detection circuit 204 further includes a second multiplier 63; wherein:
the first input end of the second multiplier 63 is electrically connected to the input end a-i of the ith clock output channel, the second input end is electrically connected to the output end b-M + i of the M + i clock output channel, and the output end is electrically connected to the output end b-i of the ith clock output channel.
The operation of the circuit of fig. 6 will now be explained:
when the high-frequency clock CK has no pulse missing, the waveform generated by the chip body is as shown in FIG. 2, the high and low levels of the low-frequency clock CLKI-F and the low-frequency clock CLKI + i-F are opposite, the detection result of the detection circuit 204 is that the low-frequency clock output by the symmetric clock channel is not high at the same time, the output potential of the output end b-i of the ith clock output channel is not controlled, the waveforms of the low-frequency clock CLKI-F and the low-frequency clock CLKI-L are the same, and the waveforms of the low-frequency clock CLKI + i-F and the low-frequency clock CLKI + i-L are the same;
when the high-frequency clock CK has a pulse missing, the waveform generated by the chip body is as shown in fig. 3, the low-frequency clock CLKOUTi-F and the low-frequency clock CLKOUTM + i-F are both high in the time period t, the detection result of the detection circuit 204 is that the low-frequency clock output by the symmetric clock channel is simultaneously high, the output potential of the output terminal b-i (for example, CLKOUT3 in fig. 7) of the ith clock output channel is controlled, the waveforms of the low-frequency clock CLKOUTi-F and the low-frequency clock CLKOUTi-L are different, and the waveforms of the low-frequency clock CLKOUTM + i-F and the low-frequency clock out M + i-L are the same.
Meanwhile, the present application also provides a display device, which includes a timing control chip 10, a level conversion chip 20 and a display panel 30, wherein the level conversion chip 20 is the chip shown in fig. 5 to 9.
When 2M is equal to 4, the structure of the display device is as shown in fig. 1, the connection manner of the GOA unit is as shown in fig. 1, and the circuit of the GOA unit is as shown in fig. 4; at this time, the specific structure of the level shift chip 20 is shown in FIG. 10, i.e., the clock channel 202-1 and the clock channel 202-3 are symmetrical, and the clock channel 202-2 and the clock channel 202-4 are symmetrical.
When 2M is equal to 8, the structure of the display device is as shown in fig. 11, the connection manner of the GOA unit is as shown in fig. 11, and the circuit of the GOA unit is as shown in fig. 12; at this time, the specific structure of the level shift chip 20 is shown in FIG. 13, i.e., the clock channel 202-1 and the clock channel 202-5 are symmetrical, the clock channel 202-2 and the clock channel 202-6 are symmetrical, the clock channel 202-3 and the clock channel 202-7 are symmetrical, and the clock channel 202-4 and the clock channel 202-8 are symmetrical.
According to the above embodiment:
the embodiment of the invention provides a level conversion chip and a display device, wherein the level conversion chip controls an output low-frequency clock of a clock output channel by a detection circuit in the clock output channel according to a level signal of an input low-frequency clock of the clock output channel and a level signal of an output low-frequency clock of a symmetrical clock output channel by utilizing the detection circuit, so that the level signal of the output low-frequency clock of the clock output channel and the level signal of the output low-frequency clock of the symmetrical clock output channel are not all high at the same moment; the technical problem that the high-level signal duration of a low-frequency clock is too long when a high-frequency clock pulse signal is lost by a time sequence control chip is solved, and equipment damage caused by large current and the like is avoided.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A level conversion chip applied to a display panel includes:
at least two clock input channels for inputting a high frequency clock;
2M clock output channels for respectively outputting 1 low-frequency clock;
the chip body is used for respectively inputting corresponding low-frequency clocks to the 2M clock output channels according to the high-frequency clocks;
at least a detection circuit is arranged in an m1 th clock output channel, and the detection circuit is used for controlling the output low-frequency clock of the m1 th clock output channel according to the level signal of the input low-frequency clock of the m1 th clock output channel and the level signal of the output low-frequency clock of the m2 th clock output channel, so that the level signal of the output low-frequency clock of the m1 th clock output channel and the level signal of the output low-frequency clock of the m2 th clock output channel are not both high at the same moment; the M1 and M2 belong to 1-2M, and the M1 clock output channel and the M2 clock output channel are symmetric clock channels with each other.
2. The chip of claim 1, wherein the detection circuit is configured to control the level signal of the output low frequency clock of the m1 clock output channel not to be high when the level signal of the input low frequency clock of the m1 clock output channel is high and the level signal of the output low frequency clock of the m2 clock output channel is high.
3. The chip of claim 2, wherein the detection circuit is configured to control the level signal of the output low frequency clock of the m1 clock output channel to be low when the level signal of the input low frequency clock of the m1 clock output channel is high and the level signal of the output low frequency clock of the m2 clock output channel is high.
4. The chip of claim 2, wherein the detection circuit is configured to control the output terminal of the m1 clock output channel to stop outputting the clock when the level signal of the input low frequency clock of the m1 clock output channel is high and the level signal of the output low frequency clock of the m2 clock output channel is high.
5. The chip of claim 1, wherein the detection circuit is configured to control the output terminal of the m1 clock output channel to output an error signal when the level signal of the input low frequency clock of the m1 clock output channel is high and the level signal of the output low frequency clock of the m2 clock output channel is high.
6. The chip of claim 5, wherein the detection circuit is further configured to control the output terminal of the m1 th clock output channel to stop outputting the error signal when the reset signal is detected.
7. The level shift chip of claim 1, wherein the detection circuit is disposed in all clock output channels.
8. The level shift chip according to any one of claims 1 to 7, wherein the detection circuit comprises an inverter and a first multiplier; wherein:
the input end of the inverter is electrically connected with the output end of the m2 clock output channel, and the output end of the inverter is electrically connected with the first input end of the first multiplier;
the second input end of the first multiplier is electrically connected with the input end of the m1 clock output channel, and the output end of the first multiplier is electrically connected with the output end of the m1 clock output channel.
9. The level shifting chip of claim 8, wherein the detection circuit further comprises a second multiplier; wherein:
the first input end of the second multiplier is electrically connected with the input end of the m1 clock output channel, the second input end of the second multiplier is electrically connected with the output end of the m2 clock output channel, and the output end of the second multiplier is electrically connected with the output end of the m1 clock output channel.
10. A display device comprising the level conversion chip according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110400415.8A CN113160735B (en) | 2021-04-14 | 2021-04-14 | Level conversion chip and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110400415.8A CN113160735B (en) | 2021-04-14 | 2021-04-14 | Level conversion chip and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113160735A CN113160735A (en) | 2021-07-23 |
| CN113160735B true CN113160735B (en) | 2022-04-08 |
Family
ID=76890359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110400415.8A Active CN113160735B (en) | 2021-04-14 | 2021-04-14 | Level conversion chip and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113160735B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099435A (en) * | 2015-08-27 | 2015-11-25 | 深圳市华星光电技术有限公司 | Level shift IC and level switching method thereof |
| CN105788543A (en) * | 2014-09-17 | 2016-07-20 | 乐金显示有限公司 | Display device |
| CN105913822A (en) * | 2016-06-23 | 2016-08-31 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) signal judging circuit and judging method, gate driving circuit and display device |
| CN107612539A (en) * | 2017-09-30 | 2018-01-19 | 深圳市华星光电技术有限公司 | A kind of abnormal processing method of the clock input signal of level translation device |
| CN110969971A (en) * | 2019-12-06 | 2020-04-07 | Tcl华星光电技术有限公司 | Display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102338945B1 (en) * | 2017-09-14 | 2021-12-13 | 엘지디스플레이 주식회사 | A display device having a level shifer |
| US10878931B2 (en) * | 2018-09-13 | 2020-12-29 | Chongqing Hkc Optoelectronics Technology Co., Ltd. | Gate driver circuit, level shifter, and display apparatus |
| US10783817B2 (en) * | 2018-09-21 | 2020-09-22 | Chongqing Hkc Optoelectronics Technology Co., Ltd. | Driving circuit, level shifter chip, and display device |
-
2021
- 2021-04-14 CN CN202110400415.8A patent/CN113160735B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105788543A (en) * | 2014-09-17 | 2016-07-20 | 乐金显示有限公司 | Display device |
| CN105099435A (en) * | 2015-08-27 | 2015-11-25 | 深圳市华星光电技术有限公司 | Level shift IC and level switching method thereof |
| CN105913822A (en) * | 2016-06-23 | 2016-08-31 | 京东方科技集团股份有限公司 | GOA (Gate Driver on Array) signal judging circuit and judging method, gate driving circuit and display device |
| CN107612539A (en) * | 2017-09-30 | 2018-01-19 | 深圳市华星光电技术有限公司 | A kind of abnormal processing method of the clock input signal of level translation device |
| CN110969971A (en) * | 2019-12-06 | 2020-04-07 | Tcl华星光电技术有限公司 | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113160735A (en) | 2021-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109064964B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US5410583A (en) | Shift register useful as a select line scanner for a liquid crystal display | |
| CN108806584B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US9818339B2 (en) | Shift register unit and method of driving the same, gate scanning circuit | |
| US9793005B2 (en) | Shift register unit, gate drive circuit, and display device | |
| CN106847156B (en) | Gate drive circuit and display device | |
| CN108877636B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US20160328045A1 (en) | Shift register, driving method, gate driving circuit and display device | |
| US20170123539A1 (en) | Gate drive circuit, cascade gate drive circuit and method for driving cascade gate drive circuit | |
| CN105304011A (en) | Shift register unit and driving method thereof, grid drive circuit and display device | |
| US11156882B2 (en) | Circuit substrate, display device and driving method | |
| CN105528985A (en) | Shift register unit, driving method and display device | |
| CN105047120B (en) | A kind of gate driving circuit and its driving method, display device | |
| CN111081180B (en) | Array substrate, detection method thereof and display device | |
| CN104575411A (en) | Liquid crystal display and bidirectional shift temporary storage device thereof | |
| US20210256889A1 (en) | Array substrate and testing method thereof | |
| US10522065B2 (en) | Transmitting electrode scan driving unit, driving circuit, driving method and array substrate | |
| CN104809973A (en) | Shifting register adaptable to negative threshold voltage and units thereof | |
| CN105355186A (en) | Drive circuit, touch display panel, driving method of touch display panel and touch display device | |
| CN112071250B (en) | GOA circuit | |
| CN110503913B (en) | Scanning circuit, display panel and driving method of display panel | |
| CN103021321A (en) | Shift register and liquid crystal display device | |
| CN110322847A (en) | Gate driving circuit, display device and driving method | |
| US9766744B2 (en) | Touch display panel, and driving method and driving circuit for the same | |
| CN106601207A (en) | Control circuit, source control circuit, driving method, and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Level conversion chip and display device Effective date of registration: 20231204 Granted publication date: 20220408 Pledgee: China Construction Bank Co.,Ltd. Shenzhen Branch Pledgor: TCL China Star Optoelectronics Technology Co.,Ltd. Registration number: Y2023980069233 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |