CN113158607B - SystemVerilog overlay set generation method and device - Google Patents

Abstract

The application relates to a method and a device for generating a SystemVerilog coverage set, wherein the method comprises the following steps: writing the collected related information of the function test points in the Excel document based on preset rules; and generating an overlay set based on the Excel document by using a preset script. By adopting the technical scheme, the verification worker only needs to quantize the function points in the Excel file through a more friendly input interface, and then the script (Perl) automatically generates the coverage set based on the file so as to improve the efficiency. The problems of large workload and low efficiency caused by manual writing of the coverage set are avoided.

Description

SystemVerilog overlay set generation method and device

Technical Field

The application relates to the technical field related to integrated circuit code layer verification, in particular to a method and a device for generating a SystemVerilog overlay set.

Background

The scale of the random integrated circuit is larger and larger, the functional verification test of the Verilog RTL code layer is larger and larger, the random verification method based on the SystemVerilog grammar is also popularized in a large scale, and the completeness of the functional verification under the random verification method is ensured by the coverage set. During execution of the project, if the complex module verifies, there is a large number of writes corresponding to the functional overlays, and manually writing the overlays is labor intensive and inefficient.

Disclosure of Invention

In view of the above, a method and a device for generating a SystemVerilog overlay set are provided to solve the problems in the background art.

The application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a method for generating a SystemVerilog coverage set, including:

writing the collected related information of the function test points in the Excel document based on preset rules;

and generating the coverage set based on the Excel document by using a preset script.

Optionally, the related information of the function test point includes: coverage points/combinations one or more of coverage point names, variable names to collect, collection names to combine, conditions of collection, and information used to generate bins.

Optionally, the information for generating the bin is information that the bin can be generated after the script is processed according to a preset rule.

Optionally, the rule of the custom bin-column writing of the Excel corresponding to the coverage point in the preset rule includes:

when there are a plurality of care values or value ranges, append is directly separated by 'separation';

several ranges or values are intended as a bin to be covered, included in { }, the contents of which are separated by |;

defining keyword segmentation; indicating that the latter range requires the creation of a bin to be covered independently;

defining a key single-hot effective code; the 'single-hot effective code' set representing the following multi-bit variables is subjected to coverage collection by independently generating bins;

defining wildcards to implement certain bit values that are only concerned about a certain variable;

defining a write method of the jump bin to realize a sequence which is concerned about the change of a certain variable value so as to identify that a certain function is covered;

defining an write method of which the whole bit coverage and the care value are 1;

defining an write method of which the whole bit coverage and the care value are 0;

optionally, the preset rule includes: and pre-writing keywords with guiding function in the Excel document so that related personnel can download the related information into the Excel document under the guidance of the keywords with guiding function.

Optionally, the generating the overlay set based on the Excel document by using a preset script includes:

step one: searching keywords in the Excel document based on the format and the keywords agreed in the preset rule;

step two: matching the searched keywords, and executing the corresponding processing mode in the preset rule;

and continuously repeating the first step and the second step until traversing the Excel document.

Optionally, one or more tables are included in the same Excel document; information written in each page table for generating an overlay set;

and generating an overlay set based on each page of table when generating the overlay set based on the Excel document by using a preset script.

In a second aspect, the present application provides a system verilog coverage set generating device, including:

the writing module is used for writing the collected related information of the function test points in the Excel document based on preset rules;

and the generation module is used for generating an overlay set based on the Excel document by using a preset script.

In a third aspect, the present application provides a system verilog coverage set generating device, including:

a processor, and a memory coupled to the processor;

the memory is used for storing a computer program, and the computer program is at least used for executing the SystemVerilog coverage set generation method according to the first aspect of the application;

the processor is configured to invoke and execute the computer program in the memory.

In a fourth aspect, the present application provides a storage medium storing a computer program, where the computer program when executed by a processor implements each step in the SystemVerilog overlay set generating method according to the first aspect of the present application.

By adopting the technical scheme, the verification worker only needs to quantize the function points in the Excel file through a more friendly input interface, and then the script (Perl) automatically generates the coverage set (SystemVerilog Covergroup) based on the file so as to improve the efficiency. The problems of large workload and low efficiency caused by manual writing of the coverage set are avoided.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a SystemVerilog overlay set generation method provided by an embodiment of the application;

FIG. 2 is a flowchart of a SystemVerilog overlay set generation method provided by an embodiment of the present application;

fig. 3 is a schematic structural diagram of a system verilog coverage set generating device according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a system verilog overlay set generating device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail below. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, based on the examples herein, which are within the scope of the application as defined by the claims, will be within the scope of the application as defined by the claims.

Firstly, the application scene of the embodiment of the application is explained, the scale of the random integrated circuit is larger and larger, the functional verification test of the Verilog RTL code layer is larger and larger, the random verification method based on the SystemVerilog grammar is also promoted in a large scale, and the completeness of the functional verification under the random verification method is ensured by the coverage set. During execution of the project, if the complex module verifies, there is a large number of writes corresponding to the functional overlays, and manually writing the overlays is labor intensive and inefficient. Furthermore, the SystemVerilog provides an overlay method, the function overlay condition is represented in a reverse direction through the collection rate of the bin, and the actual application level does not use too complex overlay grammar, and the basic overlay/cross point can represent the function point. As described above when writing SystemVerilog Covergroup (overlay set), the grammar is relatively single and regularly circulated.

Examples

Fig. 1 is a flowchart of a method for generating a SystemVerilog overlay set according to an embodiment of the present application, where the method may be executed by a SystemVerilog overlay set generating device according to an embodiment of the present application. Referring to fig. 1, the method may specifically include the steps of:

s101, writing the collected related information of the function test points in an Excel document based on preset rules;

it should be noted that, in the scheme provided by the application, the verification worker needs to quantize the function points in the Excel document with a more friendly input interface, namely: and related information of the function test points. Of course, in the process of writing the related information of the function test point, a preset rule needs to be followed. Because grammar is single and regular and circulating when writing the overlay set, the verification engineer can compare function test points which need to be collected through friendly interfaces based on certain common conventions, then the overlay set is automatically generated by the script based on the files, the verification engineer only needs to integrate the generated files in the verification environment and collect coverage rate, the work efficiency of the verification engineer is improved, and meanwhile leakage detection coverage caused by human factors is reduced.

Specifically, as mentioned in the background, in practical application, the basic coverage point/cross point is used to represent the functional point without using too complex coverage set syntax. Therefore, the application mainly aims at the fact that under the normal usage of the coverage grammar format, a mapping relation is contracted, a verification engineer fills in an input file (Excel) according to the contracted format, a SystemVerilog Covergroup (coverage) document is automatically generated by a script, and the contracted format is roughly described first: the following example, a simple coverage, contains coverage/cross points:

covergroup CovPort；

cover_kind:coverpointpkt.kind{

bins b0＝{0}；

bins b1＝{[1:3]}；

bins b2＝{[8:$]}；

option.weight＝3；

}

cover_port:coverpointpkt.port{

bins b0＝{[0:1]}；

bins b1＝{[8:10]}；

option.weight＝2；

}

cross_kind_port:cross cover_kind,cover_port；

endgroup

as can be seen from the above example, the SystemVerilog Covergroup (overlay set) syntax is relatively fixed, consisting of the following format: a coverage point/cross point name; 2. variable names to collect (Cover), or collection (Cover) names to combine (cross); 3. conditions of collection (Cover); 4. collecting bin enumeration of (Cover), or bin enumeration of combinations (cross);

note that here: the meaning of collection (Cover) is coverage or the like, the writing in the general literature is Cover, and the meaning of combination (cross) is cross coverage or the like. The writing method in the general literature is cross.

The names, variables and conditions are not specially processed, and the input and direct output in the Excel file can be directly input and written into the coverage set file; the collection (Cover) name or the designated bin of the combination (cross) required to be directly transferred out is not specially processed; script processing mainly processes the collected (Cover) bin, and under a contract, how to convert as few Excel inputs as possible into the bin to be represented;

specifically, keywords with guiding function are written in the Excel document in advance, so that related personnel can download the related information into the Excel document under the guidance of the keywords with guiding function. For example: the application is in the agreed Excel format as follows

Wherein:

CoverPoint: keywords representing relevant information of coverage points corresponding to the rear;

cross point: a keyword representing related information corresponding to cross point (combined coverage point) at the back;

CvpName: coverPoint name;

crsnap: cross Point (composite coverage Point) name;

SmpVariable: the coverage point corresponds to the variable name of sample;

CrsCvps: cross point (combined coverage point) corresponds to the coverage point name of the combination (cross);

VrbW: variable bit width, coverage point (coverage point) coverage corresponds to variable bit width;

UserDefBins: the coverage points list the coverage Bins of interest, and the coverage points list only needed or rejected combined Bins;

weight: user-defined Weight information of Bins corresponding to coverage points or cross points;

iff: the condition of the coverage point (Cover) variable;

comment: related annotation information;

TopTestPlan, project name, do no special treatment;

chapter: coverage rate of multiple coverage sets is collected in a general verification environment, so the script supports multiple Excel databases, each database corresponds to one coverage set, and names filled in after the chapters are used for generating coverage set names and file names;

PktHd: in the verification environment, variables of the common collection coverage set come from other components and are formed by packaging of class (group), and in order to reduce the number of the handle of the package class (group) before the variables when the variables are written into Excel, the variables are uniformly added by the script generation time.

S102, generating an overlay set based on the Excel document by using a preset script.

The specific step S102 includes:

step one: searching keywords in the Excel document based on the format and the keywords agreed in the preset rule;

step two: matching the searched keywords, and executing the corresponding processing mode in the preset rule;

and continuously repeating the first step and the second step until traversing the Excel document.

For better explanation in S102, a process of generating an overlay set based on the Excel document using a preset script is as follows: the process of analyzing the configuration file and generating the code of the code generation tool is further described: the script is developed in a Linux environment, and the script Perl needs to be additionally used in a Spreadsheet:: parseExcel module, which is mainly used for reading Excel.

The general process flow of a table is as follows in fig. 2:

s201, acquiring a sheet_name and generating a Covergroup file Cvgrp_ $sheet_name.sv;

s202, acquiring the effective line number and the column number of the current datasheet;

s203, from the beginning, traversing all effective rows and reading out the first column cell value (keyword) to judge;

s204, matching the CoverPoint keywords;

s2041, reading a column 2 cell to obtain the CoverPoint name $CvpName; reading a column 3 cell to obtain the Cover variable name $SvVariable; reading a column 4 cell to obtain a variable bit Width $width; reading a 5 th column cell to obtain user bin information $bins; reading a column 6 cell to obtain a user-defined cover Weight $weight; reading a column 7 cell to obtain Cover condition information $iff; reading the 8 th column cell to obtain Cover annotation information $Comment;

s2042, if the $Comment is not null, writing annotation information in the file;

s2043 if the $ Iff condition is not null;

s2044, $Iff conditional processing (particularly requiring processing of multiple combinational logic relationships and third party VIP handle)

S205, chapter: xxx matching file overtroup cvgrp_xxx write;

s206, annotating (#) keywords to remove# and writing the annotation content in the file;

s207, pktHd: xxx matching obtains a variable handle and assigns a global variable $pkthd;

s208, matching cross point keywords;

s2081, reading a column 2 cell to obtain the name of Cross Point $ CrsName; reading column 3 cell acquisition combinations (cross) coverage $crsvcnms; reading a 5 th column cell to obtain user bin information $bins; reading column 6 cells to obtain a user defined combination (cross) Weight $weight; reading column 7 cell acquisition combination (cross) condition information $iff; reading column 8 cell fetch combination (cross) annotation information $Comment;

s2082, if the user is self-defined, or only concerned with cross bin, enumerating and combining; apart, the script only needs to write the user-defined bin information into the file.

In particular, in the practical use of SystemVerilog Function Covergroup (function coverage rate) grammar, several basic grammars can meet project requirements, and the formats of the basic grammars are relatively uniform. Therefore, in the script implementation process, how the field content of the UserDefBins can Cover the basic grammar is mainly considered, and several common grammar forms are contracted in a specific format in the UserDefBins, and the Bins corresponding to coverage points to be collected (coverage) can be generated according to the contract in the script implementation process.

Further, in steps S201 to S208, S2081, and S2082, there is a program vocabulary including letters, and in other parts of the present application, the program vocabulary including letters is compared with chinese.

The coverage point corresponds to the 'UserDefBins' support as follows:

note that in the following description, a sentence used in a specific application is used, so that a word partially composed of letters exists in the description. These words do not affect the reading and understanding of the entire document.

1. Common bin:

cover_kind:coverpointkind{

bins b0＝{0}；

bins b1＝{[1:3]}；

option.weight＝2；

}

as described above, the above example, the value of kind (care value) is 0, and the value is in the range of 1 to 3, the value of 0 corresponds to one bin (name b 0), the value range of 1 to 3 corresponds to one bin (name b 1), and the value corresponds to two cases of the overtpoint care variable kind, one is 0, and the other is in the range of 1 to 3.

This column written 0,1:3 in Excel for CoverPointUserDefBins, with' spacing representing two different bins;

note: when there are a plurality of interest values or value ranges, it is sufficient to add the interest values directly with 'separation'.

2. Combining into a bin:

cover_kind:coverpointkind{

bins b0＝{0}；

bins b1＝{[1:3],[7:10]}；

option.weight＝2；

}

as described above, the above example concerns a value of 0 and a value in the range of 1 to 3 or 7 to 10, the value of 0 corresponds to one bin (name b 0), the value range of 1 to 3 or 7 to 10 corresponds to one bin (name b 1), and the above example corresponds to two cases where the above embodiment concerns a variable of kined, one is a value of 0 and the other is a value in the range of 1 to 3 or 7 to 10.

This is 0 in Excel for CoverPoint UserDefBins (bin) column notation, { [1:3] | [7:10] }, different values are separated by '|' in the combination; i.e. several ranges or values are intended to be included as a coverage, with the inner content being separated by |.

Continuous range each value is a bin alone:

cover_kind:coverpoint kind{

bins low[]＝{[0:7]}；

}

as an example, systemVerilog overlay grammar supports continuous range value generation of a single bin, requires adding [ ] to the name of the bin, identifies whether the normal range bin or the range of the single bin is to be generated for script implementation, defines a key Split, and indicates that the subsequent range requires the generation of an independent bin with the key Split, which corresponds to the UserDefbins column writing as Split (0:7)

Toggle key bit:

if toggle is desired to be 1 for all bits of the 8-bit address bus alone, then the overlay set syntax format is approximately as follows:

cover_kind:coverpoint addr{

bins bin_0＝{8’h1}；

bins bin_1＝{8’h2}；

bins bin_2＝{8’h4}；

bins bin_3＝{8’h8}；

bins bin_4＝{8’h10}；

bins bin_5＝{8’h20}；

bins bin_6＝{8’h40}；

bins bin_7＝{8’h80}；

}

if the above form is desired for more bit variables, the enumeration workload increases with increasing bit width, so the script defines the key one_hot, which corresponds to UserDefBins column write as one_hot (8) as in the above example.

5. Wild card bin:

when only some bit values of a certain variable are concerned, the SystemVerilog overlay set grammar has defined wild card bins, as follows:

cover_kind:coverpoint kind{

wildcardbins b0＝4’b 0；

wildcardbins b1＝4’b 1；

}

in the above example, where two Bins overlap by 0 and 1, respectively, the other bit values are not of interest, bin is preceded by a wildcard.

Script implementation, example above, corresponds to UserDefBins column one write method of 4'b 0,4' b1

Namely, the holdcard Bins to be collected (Cover) are enumerated, and Bins are separated.

6. Hopping bin:

in some scenarios, it may be possible to compare sequences of value changes of a certain variable of interest to identify that a certain function has been collected (Cover), and the SystemVerilog overlay grammar supports this value change as a write to collection (Cover), as examples:

cover_kind:coverpoint kind{

bins b0＝(0＝>1＝>2)；

}

that is, only if the value of kine changes in sequence as shown in 012 at 3 samples, this coverage can be switched to by toggle.

This sequence of change in the interest value corresponds to a case in which the UserDefBins column write method is 0= > 1= >2

Toggle all bits and a concern value of 1:

some scenarios may concern that all bits of a variable have appeared 1, such as a 4bit wide variable, and concern that all bits have appeared 1, then the SystemVerilog overlay set writing method is as follows:

cover_kind:coverpointkind{

wildcardbins b0＝4’b 1；

wildcardbins b1＝4’b 1？；

wildcardbins b2＝4’b1 ；

wildcardbins b3＝4’b1 ；

}

in the above scenario, if the variable bit width increases, the enumeration increases, and the keyword one_hold_holdcard_1 (value) is defined in all scripts, and the above example corresponds to the case of UserDefBins, and the column of writing is one_hold_holdcard_1 (4).

Toggle all bits and the interest value is 0:

when item-7 says that the care value is 0, the key is also defined to achieve.

On_hold_wildcard_0 (value), such as one_hold_wildcard_0 (3), then 3'b0, 3' b?0? Three bins 3' b 0.

9.Null Bins

When a certain variable corresponds to UserDefBins and corresponds to CoverPoint and is not filled, the corresponding CoverPoint direct collection (Cover) variable in the coverage set is generated, bins are not enumerated, and thus, the edges generate Bins based on the maximum number of Bins of the automax.

Reference is made in detail to the syntax and is not described in detail here.

Note: coverPointuserdefine bin are separated by a 'distance'; cross Pointusedefined bin (ignorebin) to'; ' spaced apart;

cross Point is not particularly treated, i.e., if the user only needs or needs to ignore certain combinations of Bins after cross, it is listed (in multiple; spaced) directly in the SystemVerilog grammar format within the corresponding UserDefbins of cross Point.

The following examples:

cover_kind:coverpoint kind{

bins b0＝{0}；

bins b1＝{1}；

option.weight＝2；

}

cover_port:coverpointport{

bins b0＝{0}；

bins b1＝{1}；

option.weight＝2；

}

cross_kind_port:cross cover_kind,cover_port{

ignore_binsbin0＝binsof(cover_kind)intersect{0}&&binsof(cover_port)intersect{0}；

ignore_binsbin1＝binsof(cover_kind)intersect{1}&&binsof(cover_port)intersect{1}；

}

in the above example, the combination (cross) would combine the cover_ind and the cover_port, but the two combinations would be ignore, as follows:

kind＝0，port＝0 ignore

kind＝0，port＝1

kind＝1，port＝0

kind＝1，port＝1 ignore

the example above, cross Point, corresponds to the UserDefBins write method in Excel as follows:

ignore_bins

bin0＝binsof(cover_kind)intersect{0}&&binsof(cover_port)intersect{0}；ignore_bins

bin1＝binsof(cover_kind)intersect{1}&&binsof(cover_port)intersect{1}；

according to the convention, the script development only needs simple Excel read access, and the convention is used for processing with basic regular expression to generate a coverage group;

specifically, refer to the following table:

excel file test.xls, which contains two pages of datasheet, test_0 and test_1 respectively;

the specific contents of test_0 are shown in the following table:

/>

note that, due to the size of the paper, a line division occurs in the same cell in the table. In actual writing, there are substantially no lines of text within the same cell.

The Excel file test.xls written according to the input format contains two pages of datasheet, namely test_0 and test_1, wherein the contents of the test_1 and the test_0 are consistent, and the Excel file test.xls is only used for generating a plurality of coverage group functions by script processing of a plurality of pages.

Commands are processed via script:

perl Cvgrp_gen.pl InFile＝./test.xls OutDir＝Output

wherein: the cvgrp_gen.pl is a script implemented according to the above idea, an Excel file to be processed by the script is input after the parameter InFile, and the parameter OutDir places a coverage group document generated by the script processing under the path.

After script processing, the Cvgrp_test_0.sv and the Cvgrp_test_1.sv are generated, and the Cvgrp_test_0.sv is taken as an example, and the generation format is as follows:

/>

/>

fig. 3 is a schematic structural diagram of a system verilog overlay set generating device according to another embodiment of the present application, where the device is adapted to execute a system verilog overlay set generating method provided by the embodiment of the present application. As shown in fig. 3, the apparatus may specifically include:

a writing module 31, configured to write, based on preset information about the collected function test points in the Excel document according to preset rules;

and the generating module 32 is used for generating an overlay set based on the Excel document by using a preset script.

The storage medium is characterized in that the storage medium stores a computer program, and when the computer program is executed by a processor, each step of the SystemVerilog coverage set generating method provided by the application is realized.

The embodiment of the application also provides a system verilog coverage set generating device, please refer to fig. 4, fig. 4 is a schematic structural diagram of the system verilog coverage set generating device, as shown in fig. 4, the intelligent customer service device includes: a processor 41 and a memory 42 connected to the processor 41; the memory 42 is used for storing a computer program at least for executing the SystemVerilog overlay set generation method in the embodiment of the present application; the processor 41 is arranged to invoke and execute the computer program in the memory.

The embodiment of the application also provides a storage medium which stores a computer program, and when the computer program is executed by a processor, the steps of the SystemVerilog coverage set generation method in the embodiment of the application are realized.

It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.

It should be noted that in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "plurality" means at least two.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.

The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims (9)

1. An Excel-based SystemVerilog Covergroup generation method is characterized by comprising the following steps:

writing the collected related information of the function test points in the Excel document based on preset rules;

generating a coverage group for performing functional test based on the Excel document by using a preset script;

wherein, excel corresponds to CoverPoint UserDefBins column writing rules in the preset rules, which comprise:

when there are a plurality of care values or value ranges, append is directly separated by 'separation';

several ranges or values are intended to be included as a cover bin, with the contents separated by |;

defining a key Split to indicate that the latter range requires the generation of an independent bin;

defining a key one_hot to indicate that a plurality of bit variables are to be covered;

defining wildcards to implement certain bit values that are only concerned about a certain variable;

defining a writing method of jump bin to realize a sequence which is concerned about the change of a certain variable value so as to identify that a certain function is covered;

defining a writing method of which the key is all bits and the care value is 1;

write method defining all bits of Toggle and concern value of 0.

2. The method of claim 1, wherein the information about the functional test point comprises: one or more of a Cover point/Cross point name, a variable name to Cover, a Cover name to Cross, a Cover condition, and information for generating a bin.

3. The method of claim 2, wherein the information for generating the bin is information that can generate the bin after processing a preset script according to a preset rule.

4. The method of claim 1, wherein the preset rule comprises: and pre-writing keywords with guiding function in the Excel document so that related personnel can download the related information into the Excel document under the guidance of the keywords with guiding function.

5. The method of claim 1, wherein the generating a coverage group based on the Excel document using a preset script comprises:

step one: searching keywords in the Excel document based on the format and the keywords agreed in the preset rule;

step two: matching the searched keywords, and executing the corresponding processing mode in the preset rule;

and continuously repeating the first step and the second step until traversing the Excel document.

6. The method of claim 1, wherein one or more pages of datasheet are included in the same Excel document; information for generating a copy of the Covergroup is written in each page of datasheet;

when generating a coverage based on the Excel document by using a preset script, generating a coverage based on each page of datasheet.

7. An Excel-based SystemVerilog Covergroup generation device, comprising:

the writing module is used for writing the collected related information of the function test points in the Excel document based on preset rules;

the generation module is used for generating a coverage for performing functional test based on the Excel document by using a preset script;

wherein, excel corresponds to CoverPoint UserDefBins column writing rules in the preset rules, which comprise:

when there are a plurality of care values or value ranges, append is directly separated by 'separation';

several ranges or values are intended to be included as a cover bin, with the contents separated by |;

defining a key Split to indicate that the latter range requires the generation of an independent bin;

defining a key one_hot to indicate that a plurality of bit variables are to be covered;

defining wildcards to implement certain bit values that are only concerned about a certain variable;

defining a writing method of jump bin to realize a sequence which is concerned about the change of a certain variable value so as to identify that a certain function is covered;

defining a writing method of which the key is all bits and the care value is 1;

write method defining all bits of Toggle and concern value of 0.

8. An Excel-based SystemVerilog Covergroup generation device, comprising:

a processor, and a memory coupled to the processor;

the memory is used for storing a computer program at least for executing the Excel-based SystemVerilog Covergroup generation method of any one of claims 1-6;

the processor is configured to invoke and execute the computer program in the memory.

9. A storage medium storing a computer program which, when executed by a processor, performs the steps of the Excel-based SystemVerilog Covergroup generation method of any one of claims 1-6.