CN113158600A - Method for quickly simulating ultra-large-scale via array based on moment method - Google Patents
Method for quickly simulating ultra-large-scale via array based on moment method Download PDFInfo
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- CN113158600A CN113158600A CN202110297707.3A CN202110297707A CN113158600A CN 113158600 A CN113158600 A CN 113158600A CN 202110297707 A CN202110297707 A CN 202110297707A CN 113158600 A CN113158600 A CN 113158600A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004088 simulation Methods 0.000 claims abstract description 48
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- 239000011159 matrix material Substances 0.000 claims description 22
- 238000004422 calculation algorithm Methods 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 6
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- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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Abstract
The invention belongs to the field of electromagnetic simulation, and provides a method for quickly simulating a super-large-scale via array based on a moment method, which comprises the following steps: step S1: generating an electromagnetic equivalence merging via model; in step S1, the merging of the via holes is used to maintain the electrical characteristics before and after the merging of the via hole arrays and the connection relationship with the physical layout; step S2: according to step S1, a moment method broadband simulation is performed. Based on the existing moment method electromagnetic simulation engine, a million-level via hole rapid combination technology is developed, the layout connection relation is ensured to be unchanged, the current flowing path is unchanged, the electrical characteristics of the combined via holes are brought into the electromagnetic simulation engine, and the electromagnetic simulation precision from direct current to terahertz is realized.
Description
Technical Field
The invention belongs to the field of electromagnetic simulation, and particularly relates to a method for quickly simulating a super-large-scale via array based on a moment method.
Background
In a high-speed high-frequency integrated circuit, particularly on the premise that a super-large scale through hole array is used for chip layout interconnection, the method is of great importance in analyzing the coupling among various high-speed high-frequency signals in a whole page mode. At present, under the condition that a million-level via array is encountered in a traditional EDA electromagnetic simulation algorithm, two methods are commonly used for processing, wherein the first method is to simplify the processing of the via array as an ideal via, and the second method is to divide the via array according to the shape of the via, wherein the former method cannot meet the precision requirement, and the latter method is too large in scale, so that the simulation cannot be performed under the existing computing resources.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a method for quickly simulating a super-large-scale via array based on a moment method, which solves the problem that the simulation precision and the simulation scale cannot be considered in a compatible manner, and can provide smaller memory consumption and shorter simulation time on the premise of ensuring the simulation precision.
The invention provides a moment method-based ultra-large scale via array rapid simulation method, which comprises the following steps:
step S1: generating an electromagnetic equivalence merging via model;
in step S1, the merging of the via holes is used to maintain the electrical characteristics before and after the merging of the via hole arrays and the connection relationship with the physical layout;
step S2: according to step S1, a moment method broadband simulation is performed.
In one embodiment of the present invention, the step S1 further includes the following sub-steps:
step S11: collecting via hole information, analyzing a layout file exported by electromagnetic simulation software, recording the physical position and size information of each layer of via holes, and setting a via hole merging interval threshold L;
step S12: marking the electrical characteristic, namely marking the equivalent RLC values of all the via holes by inquiring the information of the simulation process file according to the dimension information of the via holes in the step S11;
step S13: the via arrays are merged to maintain the connection relationship of the original layout.
In a technical solution of the present invention, in the step S13, the through holes are expanded in the XY direction by L, all the through hole arrays are merged into a plurality of polygonal through holes by using a geometric merging algorithm, and the merged polygonal through holes intersect with the upper and lower layers of metal.
In a technical solution of the present invention, the step S2 is further configured to obtain a standard format S parameter for fast analyzing the high-speed and high-frequency imposition chip crosstalk and coupling information.
In one embodiment of the present invention, the step S2 further includes the following sub-steps:
step S21: RLC filling matrix, fill the polygonal via hole with electromagnetic information into Y parameter matrix, and determine matrix position and direction according to the position of basis function;
step S22: and (6) solving the matrix.
In a technical solution of the present invention, in the step S22, the RLC padding matrix content in the step S21 is combined with the original matrix of the moment method to obtain a Y matrix, and the solved S parameter is obtained by utilizing the electromagnetic simulation influence of the existing moment method.
The invention has the beneficial effects that:
(1) the invention develops a million-level via hole rapid combination technology based on the existing moment method electromagnetic simulation engine, ensures that the connection relation of a layout is unchanged and the path through which current flows is unchanged, and brings the electrical characteristics of the combined via holes into the electromagnetic simulation engine to realize the electromagnetic simulation precision from direct current to terahertz.
(2) The invention can not only realize the coupling crosstalk analysis of the high-speed high-frequency full-page chip, but also ensure the precision to meet the design requirements of a high-speed analog circuit, a radio frequency circuit and a millimeter wave circuit.
(3) The invention provides an electromagnetic equivalent merging model generation algorithm, which can solve the problem of overlarge solving scale caused by a million-level via hole array in high-speed high-frequency chip simulation on the premise of not losing electromagnetic simulation precision, thereby realizing on-chip full-wave integrated simulation and quickly evaluating the field coupling effect between via holes and wiring.
Drawings
FIG. 1 is a schematic overall flow chart of the present invention.
Detailed Description
In order to facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings, in which several embodiments of the invention are shown, but which may be embodied in many different forms and are not limited to the embodiments described herein, but rather are provided for the purpose of providing a more thorough disclosure of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention; as used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the method for rapidly simulating the ultra-large scale via array based on the moment method provided by the invention solves the problem that the simulation precision and the simulation scale cannot be considered compatibly, and can provide smaller memory consumption and shorter simulation time on the premise of ensuring the simulation precision.
The working principle of the invention is as follows:
the first step is as follows: preparing an electromagnetic simulation model, and exporting a layout file from a chip design tool, wherein the layout file comprises layout information of metal and via hole layers;
the second step is that: preparing a simulation process file, importing a mainstream process file, and converting the mainstream process file into a required format;
the third step: generating an electromagnetic equivalence combination via hole model;
the fourth step: electromagnetic equivalence is combined with moment method broadband simulation of a via hole model.
The simulation method of the invention comprises the following steps:
step S1: generating an electromagnetic equivalence merging via model;
in step S1, the merging of the via holes is used to maintain the electrical characteristics before and after the merging of the via hole arrays and the connection relationship with the physical layout; the merging principle must ensure that the electrical characteristics of the via array are unchanged and the physical layout connection relationship is not affected, otherwise the electromagnetic simulation result is affected. The former can cause the simulation precision to be influenced, and the electromagnetic coupling effect cannot be considered; the latter completely changes the on-off relationship, thereby obtaining an error simulation result.
Step S2: according to step S1, a moment method broadband simulation is performed.
Specifically, step S1 includes the following sub-steps:
step S11: collecting via hole information, analyzing a layout file exported by electromagnetic simulation software, recording the physical position and size information of each layer of via holes, and setting a via hole merging interval threshold L;
step S12: marking the electrical characteristic, namely marking the equivalent RLC values of all the via holes by inquiring the information of the simulation process file according to the dimension information of the via holes in the step S11;
step S13: the via arrays are merged to maintain the connection relationship of the original layout.
Further, in step S13, the via holes are expanded in the XY direction by L, all the via hole arrays are merged into a plurality of polygonal via holes by using a geometric merging algorithm, and the merged polygonal via holes intersect with the upper and lower layers of metal.
Preferably, step S2 obtains standard format S parameters for fast analysis of high-speed and high-frequency imposition chip crosstalk and coupling information.
Specifically, step S2 includes the following sub-steps:
step S21: RLC filling matrix, fill the polygonal via hole with electromagnetic information into Y parameter matrix, and determine matrix position and direction according to the position of basis function; assuming that the sign of via _ i is sign _ i, the resistance is Ri, the inductance is Li, and the capacitance is Ci, then all basis functions that pass via _ i fill the matrix with the value Yi ═ (Ri + j × w Li +1/(j × w × Ci)) × sign _ i;
step S22: and (6) solving the matrix.
Further, in step S22, the RLC padding matrix content in step S21 is combined with the original matrix of the moment method to obtain a Y matrix, and the solved S parameter is obtained by utilizing the electromagnetic simulation influence of the existing moment method.
The invention develops a million-level via hole rapid combination technology based on the existing moment method electromagnetic simulation engine, ensures that the connection relation of a layout is unchanged and the path through which current flows is unchanged, and brings the electrical characteristics of the combined via holes into the electromagnetic simulation engine to realize the electromagnetic simulation precision from direct current to terahertz. The method can not only realize the coupling crosstalk analysis of the high-speed high-frequency full-page chip, but also ensure that the precision meets the design requirements of a high-speed analog circuit, a radio frequency circuit and a millimeter wave circuit. The invention provides an electromagnetic equivalent merging model generation algorithm, which can solve the problem of overlarge solving scale caused by a million-level via hole array in high-speed high-frequency chip simulation on the premise of not losing electromagnetic simulation precision, thereby realizing on-chip full-wave integrated simulation and quickly evaluating the field coupling effect between via holes and wiring.
The above-mentioned embodiments only express a certain implementation mode of the present invention, and the description thereof is specific and detailed, but not construed as limiting the scope of the present invention; it should be noted that, for those skilled in the art, without departing from the concept of the present invention, several variations and modifications can be made, which are within the protection scope of the present invention; therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (6)
1. A method for quickly simulating a super-large-scale via array based on a moment method is characterized by comprising the following steps:
step S1: generating an electromagnetic equivalence merging via model;
in step S1, the merging of the via holes is used to maintain the electrical characteristics before and after the merging of the via hole arrays and the connection relationship with the physical layout;
step S2: according to step S1, a moment method broadband simulation is performed.
2. The method for very large scale via array fast simulation based on the moment method of claim 1, wherein the step S1 comprises the following sub-steps:
step S11: collecting via hole information, analyzing a layout file exported by electromagnetic simulation software, recording the physical position and size information of each layer of via holes, and setting a via hole merging interval threshold L;
step S12: marking the electrical characteristic, namely marking the equivalent RLC values of all the via holes by inquiring the information of the simulation process file according to the dimension information of the via holes in the step S11;
step S13: the via arrays are merged to maintain the connection relationship of the original layout.
3. The method for fast simulation of a very large scale via array based on the moment method of claim 2, wherein in step S13, all the vias are extended by L in XY direction, and all the via arrays are merged into a plurality of polygonal vias by using a geometric merging algorithm, and the merged polygonal vias intersect with the upper and lower layer metals.
4. The method for fast simulating the ultra-large scale via hole array based on the moment method as claimed in claim 3, wherein the step S2 obtains S parameters in a standard format for fast analyzing the crosstalk and coupling information of the high-speed and high-frequency full-page chip.
5. The method for very large scale via array fast simulation based on the moment method of claim 4, wherein the step S2 comprises the following sub-steps:
step S21: RLC filling matrix, fill the polygonal via hole with electromagnetic information into Y parameter matrix, and determine matrix position and direction according to the position of basis function;
step S22: and (6) solving the matrix.
6. The method for very large scale via array rapid simulation based on moment method of claim 5, wherein in step S22, the RLC filling matrix content in step S21 is combined with the original matrix of moment method to obtain Y matrix, and the solving S parameter is obtained by utilizing the electromagnetic simulation influence of existing moment method.
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|---|---|---|---|---|
| US20110161905A1 (en) * | 2009-12-31 | 2011-06-30 | Lorentz Solution, Inc. | Layout Electromagnetic Extraction For High-Frequency Design And Verification |
| US20160314231A1 (en) * | 2015-04-24 | 2016-10-27 | Leung W. TSANG | Full wave modeling and simulations of the waveguide behavior of printed circuit boards using a broadband green's function technique |
| CN106650014A (en) * | 2016-11-21 | 2017-05-10 | 北京航天微电科技有限公司 | Method for designing microwave integrated LC filter model |
| US20190102499A1 (en) * | 2017-09-29 | 2019-04-04 | Texas Instruments Incorporated | Simulation and analysis of circuit designs |
| CN110188463A (en) * | 2019-05-29 | 2019-08-30 | 苏州芯禾电子科技有限公司 | A kind of sawtooth smoothing method of arrays of vias |
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- 2021-03-19 CN CN202110297707.3A patent/CN113158600B/en active Active
Patent Citations (5)
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| US20110161905A1 (en) * | 2009-12-31 | 2011-06-30 | Lorentz Solution, Inc. | Layout Electromagnetic Extraction For High-Frequency Design And Verification |
| US20160314231A1 (en) * | 2015-04-24 | 2016-10-27 | Leung W. TSANG | Full wave modeling and simulations of the waveguide behavior of printed circuit boards using a broadband green's function technique |
| CN106650014A (en) * | 2016-11-21 | 2017-05-10 | 北京航天微电科技有限公司 | Method for designing microwave integrated LC filter model |
| US20190102499A1 (en) * | 2017-09-29 | 2019-04-04 | Texas Instruments Incorporated | Simulation and analysis of circuit designs |
| CN110188463A (en) * | 2019-05-29 | 2019-08-30 | 苏州芯禾电子科技有限公司 | A kind of sawtooth smoothing method of arrays of vias |
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