CN113157510A - Method and device for testing transaction ordering rule of expansion bus of high-speed serial computer - Google Patents
Method and device for testing transaction ordering rule of expansion bus of high-speed serial computer Download PDFInfo
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Abstract
The invention provides a method for testing transaction sequencing rules of an expansion bus of a high-speed serial computer, which is applied to a main device of a PCIE bus of the expansion bus of the high-speed serial computer; the method comprises the following steps: sending a first type data packet to slave equipment of a PCIE bus so that the slave equipment stops updating flow control after responding to the first type data packet; sending a first type data packet to the slave device to exhaust a 5 flow control unit corresponding to the first type data packet in flow control; sending a first type data packet to the slave device to cause the first type data packet to be stored in a cache; and sending a second type of data packet to the slave device, so that the slave device starts to update the flow control in response to the second type of data packet, and sending the first type of data packet in the cache to the slave device. The invention can construct a scene needing to sort the PCIE transactions and verify the sorting rule of the PCIE.
Description
Technical Field
The invention relates to the technical field of processors, in particular to a method and a device for testing transaction sequencing rules of an expansion bus of a high-speed serial computer.
Background
The PCIE bus of the high-speed serial computer expansion bus is a widely applied computer bus and has the characteristics of point-to-point, high bandwidth, reliable transmission and the like. In the transmission process of the PCIE bus, in order to avoid congestion of transmission, a processing manner of ordering the transactions is generally adopted, for example, the transactions are ordered by using a D4 ordering rule.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art: because the transaction ordering is a processing mode adopted under the special condition that congestion may occur, in the stage of testing and verifying the chip, in the conventional data transmission process of the PCIe controller and the slave device, it is difficult to accurately construct a data transmission scenario of a certain transaction ordering rule, and thus, each PCIe transaction ordering rule cannot be verified accurately and efficiently.
Disclosure of Invention
The method and the device for testing the transaction sequencing rule of the expansion bus of the high-speed serial computer can construct a scene needing to sequence PCIE transactions and verify the sequencing rule of the PCIE.
In a first aspect, the invention provides a method for testing a sequencing rule of an expansion bus of a high-speed serial computer, which is applied to a main device of a PCIE bus of the expansion bus of the high-speed serial computer; the method comprises the following steps:
sending a first type data packet to slave equipment of a PCIE bus so that the slave equipment stops updating flow control after responding to the first type data packet;
sending a first type data packet to the slave device to exhaust a flow control unit corresponding to the first type data packet in the flow control;
sending a first type of packet to the slave device to cause the first type of packet to be stored in a pending transaction buffer;
and sending a second type of data packet to the slave device, so that the slave device starts to update the flow control in response to the second type of data packet, and the first type of data packet in the suspended transaction buffer is sent to the slave device.
Optionally, sending the first type data packet to the slave device to exhaust the flow control unit corresponding to the first type data packet in the flow control includes:
and receiving a third type data packet sent by the slave device, and sending a first type data packet to the slave device in response to the third type data packet so as to exhaust a flow control unit corresponding to the first type data packet in the flow control.
Optionally, sending the first type data packet to the slave device to exhaust the flow control unit corresponding to the first type data packet in the flow control includes:
and after waiting for the first preset time, sending a first type data packet to the slave equipment to exhaust a flow control unit corresponding to the first type data packet in the flow control.
Optionally, sending the second type of data packet to the slave device comprises:
and receiving a first type data packet sent by the slave equipment, and sending a second type data packet to the slave equipment in response to the first type data packet.
Optionally, before sending the second type of data packet to the slave device, the method includes:
and newly building a process and sending a vendor-defined Data Link Layer Packet (DLLP) to the slave equipment to trigger the slave equipment to send a first type packet.
Optionally, the first type data packet is sent to the slave device, so that after the flow control unit corresponding to the first type data packet in the flow control is exhausted, the slave device is further configured to send the first type data packet after waiting for a second predetermined time.
Optionally, the slave device includes a programmable PCIE device or a field programmable gate array FPGA.
In a second aspect, the present invention provides a device for testing an ordering rule of an expansion bus of a high-speed serial computer, which is applied to a host device of a PCIE bus of the expansion bus of the high-speed serial computer; the method comprises the following steps:
the flow control stopping module is used for sending a first type data packet to slave equipment of the PCIE bus so as to stop updating the flow control after the slave equipment responds to the first type data packet;
the flow control exhaustion module is used for sending the first type data packet to the slave device so as to exhaust flow control units corresponding to the first type data packet in the flow control;
a first sending module, configured to send a first type of packet to the slave device, so that the first type of packet is stored in a pending transaction buffer;
and a second sending module, configured to send a second type of packet to the slave device, so that the slave device starts to update the flow control in response to the second type of packet, and send the first type of packet in the pending transaction buffer to the slave device.
Optionally, the flow control exhaustion module is specifically configured to:
receiving a third type data packet sent by the slave device, and sending a first type data packet to the slave device in response to the third type data packet to exhaust a flow control unit corresponding to the first type data packet in the flow control; alternatively, the first and second electrodes may be,
and after waiting for the first preset time, sending a first type data packet to the slave equipment to exhaust a flow control unit corresponding to the first type data packet in the flow control.
Optionally, the second sending module is specifically configured to receive the first type of data packet sent by the slave device, and send a second type of data packet to the slave device in response to the first type of data packet, so that the slave device starts to update the flow control in response to the second type of data packet, and sends the first type of data packet in the pending transaction buffer to the slave device.
In the technical scheme provided by the invention, the congestion is formed when the primary equipment of the PCIE bus sends the first type data packet by closing and exhausting the flow control, and a processing environment which needs to sequence the PCIE transaction is created, so that whether the sequencing rule of the PCIE transaction can be correctly executed can be verified.
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FIG. 1 is a flow chart of a method for testing a high-speed serial computer expansion bus sequencing rule according to an embodiment of the present invention;
FIG. 2 is an interactive flowchart of a method for testing a high-speed serial computer expansion bus sequencing rule according to another embodiment of the present invention;
FIG. 3 is an interactive flowchart of a method for testing a high-speed serial computer expansion bus sequencing rule according to another embodiment of the present invention;
FIG. 4 is a timing diagram corresponding to FIG. 3;
FIG. 5 is a schematic diagram of an apparatus for testing a high-speed serial computer expansion bus sequencing rule according to another embodiment of the present invention;
FIG. 6 is a system diagram of an application environment of a high-speed serial computer extended bus sequencing rule testing device according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a method for testing the sequencing rule of an expansion bus of a high-speed serial computer, which is applied to a main device of a PCIE bus of the expansion bus of the high-speed serial computer as shown in figure 1; the method comprises the following steps:
step 101, sending a first type data packet to a slave device of a PCIE bus, so that the slave device stops updating a flow control after responding to the first type data packet; in some embodiments, the packet types generally include three types as follows: a non-forwarding request data packet NPH, a forwarding request data packet PH and a completion feedback data packet CPL; the correspondence between the types of the three data packets and the specific data processing procedure is as follows:
however, it should be understood by those skilled in the art that, after receiving an NPH type packet, a PCIE controller or a PCIE slave device is triggered to transmit a CPL type packet. For the above and the following descriptions, the first type packet and the second type packet refer to two types of packets that need to be sequenced in the process of processing PCIE transaction, for example, the d4 sequencing rule indicates that the CPL type packet should be able to pass through the NPH type packet, at this time, the first type packet may be the NPH type packet, and the second type packet may be the CPL type packet.
102, sending a first type data packet to the slave device to exhaust a flow control unit corresponding to the first type data packet in the flow control; in some embodiments, after the NPH flow control update is stopped, there are still a part of flow control units that are not used yet, and therefore, in order to block the first type data packet in the subsequent verification process, in this step, after the flow control update is stopped, the first type data packet is continuously sent, so that the flow control unit corresponding to the first type data packet is exhausted, and thus the sending of the first type data packet is blocked.
Step 103, sending a first type data packet to the slave device so that the first type data packet is stored in a suspended transaction buffer; in some embodiments, since the flow control unit corresponding to the first type packet is exhausted in step 102, at this time, the first type packet cannot be sent, and the first type packet that cannot be sent successfully will be stored in the pending transaction buffer of the PCIE controller.
And 104, sending a second type of data packet to the slave device, so that the slave device starts to update the flow control in response to the second type of data packet, and sending the first type of data packet in the pending transaction buffer to the slave device. In some embodiments, the second type of packet is a packet type specified in the ordering rule that can be ordered with the first type of packet according to a predetermined rule, for example, still explained with the rule of d4 in step 101, the CPL type of packet is required to be transmitted beyond the NPH type of packet in the rule of d4, and therefore, the CPL type of packet may be used as the second type of packet, and the NPH type of packet is used as the first type of packet, and at step 103, the first type of packet is transmitted first, and the second type of packet is transmitted later, at which time, it is verified that the second type of packet can be transmitted beyond the first type of packet, it is only necessary to determine whether the second type of packet to be transmitted later can be successfully transmitted, when the second type of packet can be transmitted successfully, it is determined that the ordering rule can be executed successfully, and when the second type of packet cannot be transmitted successfully, it may be determined that the sort rule cannot be successfully executed.
In the technical scheme provided by the invention, the congestion is formed when the primary equipment of the PCIE bus sends the first type data packet by closing and exhausting the flow control, and a processing environment which needs to sequence the PCIE transaction is created, so that whether the sequencing rule of the PCIE transaction can be correctly executed can be verified.
As an optional implementation manner, sending the first type data packet to the slave device to exhaust the flow control unit corresponding to the first type data packet in the flow control includes:
and receiving a third type data packet sent by the slave device, and sending a first type data packet to the slave device in response to the third type data packet so as to exhaust a flow control unit corresponding to the first type data packet in the flow control. In some embodiments, the third type of packet sent from the device is used to trigger the PCIE controller to send the first type of packet. The PCIE controller is configured to send a third type data packet after the slave device closes the flow control update in this step, and send the first type data packet after receiving the third type data packet, so as to accurately consume the flow control unit corresponding to the first type data packet.
As an optional implementation manner, sending the first type data packet to the slave device to exhaust the flow control unit corresponding to the first type data packet in the flow control includes:
and after waiting for the first preset time, sending a first type data packet to the slave equipment to exhaust a flow control unit corresponding to the first type data packet in the flow control. In some embodiments, since the slave device needs a certain operation time when the flow control update is turned off, enough waiting time needs to be reserved to ensure that the slave device turns off the flow control, and then the first type data packet is sent. The embodiment reduces the interaction process, and only needs the PCIE controller to wait before sending the first type data packet.
As an optional implementation, the sending the second type of data packet to the slave device includes:
and receiving a first type data packet sent by the slave equipment, and sending a second type data packet to the slave equipment in response to the first type data packet. In some embodiments, the first type of packet sent by the slave device is a condition for triggering the PCIE controller to send the second type of packet, for example, as described in the foregoing d4 sorting rule, since the second type of CPL type of packet is a packet fed back after receiving the NPH type of packet, that is, the first type of packet, needs to be sent from the slave device to the PCIE controller, and after the PCIE controller receives the NPH type of packet, the CPL type of packet, that is, the second type of packet, is fed back to the slave device.
As an optional implementation manner, before sending the second type of data packet to the slave device, the method includes:
and newly building a process and sending a manufacturer definition DLLP to the slave equipment so as to trigger the slave equipment to send a first type data packet. In some embodiments, since the PCIE controller has exhausted the flow control unit corresponding to the first type packet, the first type packet sent by the PCIE controller is cached and cannot be sent to the slave device, that is, the slave device cannot determine when to send the first type packet to trigger the PCIE controller, in this embodiment, after the PCIE controller sends the first type packet and the first type packet is cached, the PCIE controller sends the vendor definition DLLP to the slave device, so that the slave device obtains the state change of the PICE controller.
As an optional implementation manner, after the first type data packet is sent to the slave device to exhaust the flow control unit corresponding to the first type data packet in the flow control, the slave device is further configured to send the first type data packet after waiting for a second predetermined time. In this embodiment, after the PCIE controller exhausts the flow control unit corresponding to the first type of packet, the slave device waits for the second predetermined time, where the waiting time corresponds to a time for the PCIE controller to send the first type of packet and perform buffering, and therefore, the waiting time needs to ensure that the PCIE controller can complete sending and buffering the first type of packet. The mode reduces the interaction between the PCIE controller and the slave equipment and simplifies the interaction process.
As an optional implementation, the slave device includes a programmable PCIE device or a field programmable gate array FPGA.
As follows, a PCIE controller is used as a master device of a PCIE bus, a programmable PCIE device and a field programmable gate array FPGA are used as slave devices of the PCIE bus, and the above method is described in detail with a specific interaction process.
As shown in fig. 2, a PCIE controller is used as a master device of a PCIE bus, a programmable PCIE device is used as a slave device of the PCIE bus, and an interaction process between the two devices is taken as an example to explain:
in step 201, the PCIE controller sends a first type data packet, for example, sends a memory read request.
In step 202, the programmable PCIe device stops updating the NPH flow control after responding to the first type data packet sent by the test program.
In step 203, after the programmable PCIe device stops updating the setting of the NPH flow control to take effect, the programmable PCIe device sends a third type data packet, for example, a memory write request, to the PCIe controller, so as to trigger the PCIe controller to send the first type data packet to exhaust the flow control unit corresponding to the first type data packet.
In step 204, after receiving a third type data packet, such as a memory write request, sent by the PCIE device, the PCIE controller sends a first type data packet, such as a memory read request, to exhaust a flow control unit corresponding to the first type data packet.
In step 205, the PCIE controller sends a first type packet, for example, a configuration write request. Since the sending of the first-type packet in step 204 depletes the corresponding flow control unit, there will be no corresponding flow control unit to enable the first-type packet to be successfully sent, and when the first-type packet cannot be successfully sent, the first-type packet will be stored in the pending transaction buffer.
In step 206, the new process of the PCIE controller sends a Vendor-Specific DLLP as a link layer packet designated by a provider, and notifies the programmable PCIE device that the first type packet has been sent, for example, the configuration write request has been sent.
In step 207, after the programmable PCIe device receives the Vendor-Specific DLLP sent by the PCIe controller, the programmable PCIe device sends a first type data packet, for example, a memory read request, to trigger the PCIe controller to send a second type data packet.
In step 208, the PCIe controller responds to the first type data packet, such as the memory read request, sent by the PCIe device, and replies to the second type data packet, such as the data corresponding to the memory read request.
In step 209, the programmable PCIe device resumes updating the flow control after receiving the second type of packet.
Step 210, after the programmable PCIe device recovers the stream control update, a first type data packet sent by the PCIe controller is received, for example, a configuration write request.
The above is described by taking a programmable PCIE device as an example, and those skilled in the art should understand that the above process is also applicable to an interaction process between an FPGA and a PCIE controller. In addition, the sending of the first type data packet by the programmable PCIe device in step 207 is triggered by the notification message in step 206, and the sending of the first type data packet in step 204 is triggered by the third type data packet in step 203, and those skilled in the art should understand that one or both of steps 207 and step 204 may be modified to directly send the corresponding data packet after waiting for the predetermined time without triggering in steps 206 and 203, so as to simplify the interaction process between the PCIe controller and the programmable PCIe device.
As shown in fig. 3-4, a PCIE controller is used as a master device of a PCIE bus, an FPGA is used as a slave device of the PCIE bus, and an interaction process between the two is taken as an example to explain:
in step 301, the PCIE controller sends a first type data packet, for example, sends a memory read request.
And step 302, after responding to the first type data packet sent by the test program, the FPGA stops updating the NPH flow control.
Step 303, after the step 301, after waiting for a first predetermined time, for example, 10 milliseconds, the PCIE controller sends a first type data packet, for example, a memory read request, to exhaust a flow control unit corresponding to the first type data packet.
At step 304, the PCIE controller sends a first type packet, for example, a configuration write request. Since the sending of the first-type packet in step 303 depletes the corresponding flow control unit, there will be no corresponding flow control unit to enable the first-type packet to be successfully sent, and when the first-type packet cannot be successfully sent, the first-type packet will be stored in the pending transaction buffer.
Step 305, after stopping updating the flow control, the FPGA waits for a second predetermined time, for example, 1 second, to ensure that the memory read request is sent after the test program sends the configuration write request. The FPGA sends a first type data packet, such as a memory read request, to trigger the PCIE controller to send a second type data packet.
In step 306, the PCIe controller responds to the first type data packet, such as the memory read request, sent by the FPGA, and replies to the second type data packet, such as the data corresponding to the memory read request.
And 307, after receiving the second type data packet, the FPGA restores the updating of the flow control.
Step 308, after the flow control update is restored by the FPGA, a first type data packet, such as a configuration write request, sent by the PCIe controller is received.
The above is described by taking an FPGA as an example, and those skilled in the art should understand that the above process is also applicable to the interaction process between the programmable PCIE device and the PCIE controller. In addition, both of the above steps 303 and 305 directly transmit the corresponding data packet after waiting for a predetermined time, and it should be understood by those skilled in the art that one or both of the above steps 303 and 305 may be performed in a condition-triggered manner, for example, in steps 206 and 203, so as to avoid erroneous interaction due to timing errors.
The embodiment of the invention also provides a device for testing the sequencing rule of the expansion bus of the high-speed serial computer, which is applied to the main equipment of the PCIE bus of the expansion bus of the high-speed serial computer as shown in FIG. 5; the method comprises the following steps:
the flow control stopping module is used for sending a first type data packet to slave equipment of the PCIE bus so as to stop updating the flow control after the slave equipment responds to the first type data packet;
in some embodiments, the packet types generally include three types as follows: a non-forwarding request data packet NPH, a forwarding request data packet PH and a completion feedback data packet CPL; the correspondence between the types of the three data packets and the specific data processing procedure is as follows:
however, it should be understood by those skilled in the art that, after receiving an NPH type packet, a PCIE controller or a PCIE slave device is triggered to transmit a CPL type packet. For the above and the following descriptions, the first type packet and the second type packet refer to two types of packets that need to be sequenced in the process of processing PCIE transaction, for example, the d4 sequencing rule indicates that the CPL type packet should be able to pass through the NPH type packet, at this time, the first type packet may be the NPH type packet, and the second type packet may be the CPL type packet.
The flow control exhaustion module is used for sending the first type data packet to the slave device so as to exhaust flow control units corresponding to the first type data packet in the flow control;
in some embodiments, after stopping the flow control update, there is still a part of the flow control units that are not used yet, and therefore, in order to block the first type data packet in the subsequent verification process, in this step, after stopping the flow control update, the first type data packet is continuously sent, so that the flow control unit corresponding to the first type data packet is exhausted, and thus the sending of the first type data packet is blocked.
A first sending module, configured to send a first type of packet to the slave device, so that the first type of packet is stored in a pending transaction buffer;
in some embodiments, since the flow control unit corresponding to the first type packet is exhausted in the flow control exhaustion module, at this time, the first type packet cannot be sent, and the first type packet that cannot be sent successfully will be stored in the suspended transaction buffer of the PCIE controller.
And the second sending module is used for sending a second type of data packet to the slave device, so that the slave device starts to update the flow control in response to the second type of data packet, and the first type of data packet in the cache is sent to the slave device.
In some embodiments, the second type of packet is a packet type specified in the ordering rule that can be ordered with the first type of packet according to a predetermined rule, for example, still explained with the rule of d4 in step 101, the CPL type of packet is required to be transmitted beyond the NPH type of packet in the rule of d4, and therefore, the CPL type of packet may be used as the second type of packet, and the NPH type of packet is used as the first type of packet, and at step 103, the first type of packet is transmitted first, and the second type of packet is transmitted later, at which time, it is verified that the second type of packet can be transmitted beyond the first type of packet, it is only necessary to determine whether the second type of packet to be transmitted later can be successfully transmitted, when the second type of packet can be transmitted successfully, it is determined that the ordering rule can be executed successfully, and when the second type of packet cannot be transmitted successfully, it may be determined that the sort rule cannot be successfully executed.
In the technical scheme provided by the invention, the congestion is formed by the main equipment of the PCIE bus in sending the first type data packet by closing and exhausting the flow control, and a processing environment which needs to sequence the PCIE transaction is created, so that whether the sequencing rule of the PCIE things can be correctly executed can be verified.
As an optional implementation, the flow control exhaustion module is specifically configured to:
receiving a third type data packet sent by the slave device, and sending a first type data packet to the slave device in response to the third type data packet to exhaust a flow control unit corresponding to the first type data packet in the flow control; alternatively, the first and second electrodes may be,
and after waiting for the first preset time, sending a first type data packet to the slave equipment to exhaust a flow control unit corresponding to the first type data packet in the flow control.
In this embodiment, there are two trigger modes for the flow control exhaustion module to send the first type of packet, one is to wait for a predetermined time for triggering, and the other is to receive the third type of packet for triggering, which is specifically as follows:
in some embodiments, the third type of packet sent from the device is used to trigger the PCIE controller to send the first type of packet. The PCIE controller is configured to send the third type data packet after the flow control is closed by the slave device in this step, and send the first type data packet after the PCIE controller receives the third type data packet, so as to accurately consume the flow control unit corresponding to the first type data packet.
In other embodiments, since the slave device needs a certain period of operation time when the flow control is turned off and the update is stopped, enough waiting time needs to be reserved to ensure that the slave device turns off the flow control, and then the first type of data packet is sent. The embodiment reduces the interaction process, and only needs the PCIE controller to wait before sending the first type data packet.
As an optional implementation manner, the second sending module is specifically configured to receive a first type of data packet sent by the slave device, and send a second type of data packet to the slave device in response to the first type of data packet, so that the slave device starts to update a flow control in response to the second type of data packet, and sends the first type of data packet in the cache to the slave device.
In some embodiments, the first type of packet sent by the slave device is a condition for triggering the PCIE controller to send the second type of packet, for example, as described in the foregoing d4 sorting rule, since the second type of CPL type of packet is a packet fed back after receiving the NPH type of packet, that is, the first type of packet, needs to be sent from the slave device to the PCIE controller, and after the PCIE controller receives the NPH type of packet, the CPL type of packet, that is, the second type of packet, is fed back to the slave device.
The slave device sends the first type data packet in two triggering manners, one of which is that the PCIE controller newly creates a process and sends a vendor defined DLLP to the slave device to trigger the slave device to send the first type data packet. In some embodiments, since the PCIE controller has exhausted the flow control unit corresponding to the first type packet, the first type packet sent by the PCIE controller is cached and cannot be sent to the slave device, that is, the slave device cannot determine when to send the first type packet to trigger the PCIE controller, in this embodiment, after the PCIE controller sends the first type packet and the first type packet is cached, the PCIE controller sends the vendor definition DLLP to the slave device, so that the slave device obtains the state change of the PICE controller.
The other is that the PCIE controller sends the first type data packet to the slave device, so that after the flow control unit corresponding to the first type data packet in the flow control is exhausted, the PCIE controller is further configured to make the slave device wait for a second predetermined time and send the first type data packet. That is, after receiving the first type data packet sent by the flow control exhaustion module, the slave device waits for a second predetermined time and then sends the first type data packet. In this embodiment, after the PCIE controller exhausts the flow control unit corresponding to the first type of packet, the slave device waits for the second predetermined time, where the waiting time corresponds to a time for the PCIE controller to send the first type of packet and perform buffering, and therefore, the waiting time needs to ensure that the PCIE controller can complete sending and buffering the first type of packet. The mode reduces the interaction between the PCIE controller and the slave equipment and simplifies the interaction process.
Fig. 6 illustrates an application environment of the above-described apparatus and method, and the test program in the figure can execute the above-described method during execution.
It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for testing sequencing rules of an expansion bus of a high-speed serial computer is characterized by being applied to a main device of a PCIE bus of the expansion bus of the high-speed serial computer; the method comprises the following steps:
sending a first type data packet to slave equipment of a PCIE bus so that the slave equipment stops updating flow control after responding to the first type data packet;
sending a first type data packet to the slave device to exhaust a flow control unit corresponding to the first type data packet in the flow control;
sending a first type of packet to the slave device to cause the first type of packet to be stored in a pending transaction buffer;
and sending a second type of data packet to the slave device, so that the slave device starts to update the flow control in response to the second type of data packet, and the first type of data packet in the suspended transaction buffer is sent to the slave device.
2. The method according to claim 1, wherein sending the first type of packet to the slave device to exhaust flow control units corresponding to the first type of packet in the flow control comprises:
and receiving a third type data packet sent by the slave device, and sending a first type data packet to the slave device in response to the third type data packet so as to exhaust a flow control unit corresponding to the first type data packet in the flow control.
3. The method according to claim 1, wherein sending the first type of packet to the slave device to exhaust flow control units corresponding to the first type of packet in the flow control comprises:
and after waiting for the first preset time, sending a first type data packet to the slave equipment to exhaust a flow control unit corresponding to the first type data packet in the flow control.
4. The method of claim 1, wherein sending the second type of packet to the slave device comprises:
and receiving a first type data packet sent by the slave device, and sending a second type data packet to the slave device in response to the first type data packet.
5. The method of claim 4, wherein sending the second type of packet to the slave device is preceded by:
and newly building a process and sending a data link layer packet DLLP defined by a manufacturer to the slave equipment so as to trigger the slave equipment to send a first type packet.
6. The method according to claim 4, wherein the first type data packet is sent to the slave device, so that after the flow control unit corresponding to the first type data packet in the flow control is exhausted, the slave device is further configured to send the first type data packet after waiting for a second predetermined time.
7. The method of claim 1, wherein the slave device comprises a programmable PCIE device or a field programmable gate array FPGA.
8. A high-speed serial computer expansion bus transaction sequencing rule testing device is characterized by being applied to a main device of a PCIE bus of a high-speed serial computer expansion bus; the method comprises the following steps:
the flow control stopping module is used for sending a first type data packet to slave equipment of the PCIE bus so as to stop updating the flow control after the slave equipment responds to the first type data packet;
the flow control exhaustion module is used for sending the first type data packet to the slave device so as to exhaust flow control units corresponding to the first type data packet in the flow control;
a first sending module, configured to send a first type of packet to the slave device, so that the first type of packet is stored in a pending transaction buffer;
and a second sending module, configured to send a second type of packet to the slave device, so that the slave device starts to update the flow control in response to the second type of packet, and send the first type of packet in the pending transaction buffer to the slave device.
9. The apparatus of claim 8, wherein the flow control depletion module is specifically configured to:
receiving a third type data packet sent by the slave device, and sending a first type data packet to the slave device in response to the third type data packet to exhaust a flow control unit corresponding to the first type data packet in the flow control; alternatively, the first and second electrodes may be,
and after waiting for the first preset time, sending a first type data packet to the slave equipment to exhaust a flow control unit corresponding to the first type data packet in the flow control.
10. The apparatus according to claim 8, wherein the second sending module is specifically configured to receive a first type of packet sent by the slave device, and send a second type of packet to the slave device in response to the first type of packet, so that the slave device starts to update the flow control in response to the second type of packet, and sends the first type of packet in the pending transaction buffer to the slave device.
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