CN113156799A - Clock testing method and device, mass production testing method and testing platform - Google Patents
Clock testing method and device, mass production testing method and testing platform Download PDFInfo
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- CN113156799A CN113156799A CN202110267015.4A CN202110267015A CN113156799A CN 113156799 A CN113156799 A CN 113156799A CN 202110267015 A CN202110267015 A CN 202110267015A CN 113156799 A CN113156799 A CN 113156799A
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Abstract
The application discloses a clock testing method, a clock testing device, a mass production testing method and a testing platform. The clock testing method comprises the steps of obtaining a clock window based on a clock to be tested generated by a chip to be tested, wherein the size of the clock window is preset; counting the clock window by using a standard clock to obtain an accumulated clock count; the frequency of the standard clock is greater than that of the clock to be measured; and calculating the difference value of the accumulated clock count and the standard clock count to obtain an accumulated clock difference value, comparing the accumulated clock difference value with a preset clock threshold value, and determining the test result of the chip to be tested based on the comparison result. The clock testing method can improve the testing efficiency, reduce the misjudgment and greatly reduce the cost.
Description
Technical Field
The application relates to the technical field of measurement, in particular to a clock testing method, a clock testing device, a mass production testing method and a mass production testing platform.
Background
For a high-speed clock, especially for a phase-locked loop module, accumulated clock jitter is a very important index, and process angle deviation in a mass-produced chip may cause clock circuits such as a phase-locked loop to be abnormal, resulting in instability of the clock circuits, such as large accumulated clock jitter, and even causing the phase-locked loop to lose lock in a severe case. Therefore, it is necessary to measure the accumulated jitter of the high-speed clock in the test of mass production of chips.
Professional clock test equipment can judge the precision of the clock through the proportional relation between the internal clock and the input clock of the test platform, but the cost of the frequency instrument is high. The test can be done in an indirect way when the accumulated clock jitter cannot be directly acquired. For example by observing the stability of the image and judging by reading the clock register. However, since the parameter index is estimated by means of phenomenon observation, not only the test efficiency is low, but also erroneous judgment is easy to occur in the mass production test.
Disclosure of Invention
Therefore, the application provides a clock testing method, a clock testing device, a mass production testing method and a mass production testing platform, so as to solve the problems of low testing efficiency and easy occurrence of misjudgment in the prior art.
In order to achieve the above object, a first aspect of the present application provides a clock testing method, including:
acquiring a clock window based on a clock to be tested generated by a chip to be tested, wherein the size of the clock window is preset;
counting the clock window by using a standard clock to obtain an accumulated clock count; the frequency of the standard clock is greater than that of the clock to be tested;
calculating the difference value of the accumulated clock count and a preset clock count to obtain an accumulated clock difference value;
and comparing the accumulated clock difference value with a preset clock threshold value, and determining the test result of the chip to be tested based on the comparison result.
Wherein counting the clock window with a standard clock to obtain an accumulated clock count comprises:
counting the clock window with a high level or a low level of the clock window.
After comparing the accumulated clock difference with a preset clock threshold and determining a test result of the chip to be tested based on the comparison result, the method further includes:
and storing the test result for inquiring the test result.
In order to achieve the above object, a second aspect of the present application provides a clock testing apparatus comprising:
the clock generator is used for acquiring a clock window based on a clock to be detected generated by the chip to be detected; wherein the size of the clock window is preset;
the clock management module is used for generating a standard clock; the frequency of the standard clock is greater than that of the clock to be tested;
a counter for counting the clock window based on the standard clock to obtain an accumulated clock count;
the calculation module is used for calculating the difference value between the accumulated clock count and the standard clock count to obtain an accumulated clock difference value;
and the judging module is used for comparing the accumulated clock difference value with a preset clock threshold value and determining the test result of the chip to be tested based on the comparison result.
The clock management module is a delay locked loop or a delay locked loop.
In order to achieve the above object, a third aspect of the present application provides a test platform, including a clock testing apparatus, where the clock testing apparatus employs the clock testing apparatus provided in the present application.
Wherein, still include:
the clock distributor is used for distributing the clock to be tested generated by the chip to be tested to obtain a first path of clock to be tested and a second path of clock to be tested;
the clock distributor is used for distributing the clock to be tested generated by the chip to be tested to obtain at least two paths of clocks to be tested, wherein one path of clock to be tested is connected with the clock testing device.
Wherein, still include:
and the level conversion module is used for converting the level of the second path of clock to be tested into the level consistent with the level of the standard clock.
In order to achieve the above object, a fourth aspect of the present application provides a method for mass production testing, comprising:
acquiring a clock to be tested generated by a chip to be tested;
generating a clock window based on the clock to be tested; wherein the size of the clock window is preset;
counting the clock window by using a standard clock to obtain an accumulated clock count; the frequency of the standard clock is greater than that of the clock to be tested;
calculating the difference value between the accumulated clock count and the standard clock count to obtain an accumulated clock difference value;
and comparing the accumulated clock difference with a preset clock threshold value, and determining the test result of the chip to be tested based on the comparison result.
Before acquiring the clock to be tested generated by the chip to be tested, the method further comprises the following steps:
and delaying the chip to be tested by a preset delay length after the chip to be tested generates the clock to be tested.
Before delaying the preset time length after the chip to be tested generates the clock to be tested, the method further comprises the following steps:
setting the clock threshold and the clock window with the standard clock generator turned off.
This application has following advantage:
according to the clock testing method, a clock window determined according to a clock to be tested is counted based on a standard clock to obtain accumulated clock counting; the difference value of the accumulated clock count and the standard clock count is calculated to obtain an accumulated clock difference value, the accumulated clock difference value is compared with a preset clock threshold value, and the test result of the chip to be tested is determined based on the comparison result. In addition, compared with professional clock testing equipment, the method can greatly reduce the cost. In addition, the clock testing method can be directly applied to a mass production testing platform.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application.
Fig. 1 is a flowchart of a clock testing method according to an embodiment of the present disclosure;
FIG. 2 is a diagram of a clock to be tested, a standard clock, and a clock window in an embodiment of the present application; wherein, the uppermost waveform is a clock to be tested, the middle is a clock window, and the lowermost waveform is a standard clock;
fig. 3 is a schematic block diagram of a clock testing apparatus according to an embodiment of the present disclosure;
FIG. 4 is a functional block diagram of a test platform provided in an embodiment of the present application;
FIG. 5 is a schematic block diagram of another test platform provided in an embodiment of the present application;
FIG. 6 is a functional block diagram of another testing platform provided in an embodiment of the present application;
FIG. 7 is a flowchart of a method for testing mass production according to an embodiment of the present disclosure;
fig. 8 is a diagram of measurement data and measurement waveforms obtained by measuring a chip to be measured.
Detailed Description
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present application, are given by way of illustration and explanation only, and are not intended to limit the present application.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
When the terms "comprises" and/or "comprising … …" are used herein, the presence of the stated features, integers, steps, operations, elements, and/or components are specified, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In a first aspect, the present application provides a clock testing method for the defects of high cost, low testing efficiency and possible test misjudgment in high-speed clock measurement of a chip and the like.
Fig. 1 is a flowchart of a clock testing method according to an embodiment of the present disclosure. Fig. 2 is a schematic diagram of a clock and a clock window according to an embodiment of the present application. Referring to fig. 1 and 2, a clock testing method includes:
step S101, acquiring a clock window based on a clock to be tested generated by a chip to be tested.
The chip to be tested can be any chip to be tested, and the clock to be tested is a clock generated by the chip to be tested. The clock window is a window generated based on the clock under test.
In some embodiments, the size of the clock window may be set by the user as desired. The size of the clock window may be any value between 20 microseconds and 500 microseconds.
In some embodiments, the size of the clock window may be adjusted by a register.
Step S102, counting the clock window based on the standard clock to obtain the accumulated clock count.
And the frequency of the standard clock is greater than that of the clock to be tested.
In some embodiments, the standard Clock is an FPGA Clock generated by a Clock management unit, wherein the Clock management unit may be a Delay Locked Loop (DCM) or a Delay Locked Loop (DLL).
Counting the clock windows is to determine the number of clock windows in a set time period so as to determine the accuracy of the clock to be measured based on the number of clock windows.
In some embodiments, the clock window is counted using a high level of the clock window, and the cumulative clock difference is calculated using a low level of the clock window; alternatively, the clock window is counted using the low level of the clock window, and the accumulated clock difference is calculated using the high level of the clock window.
The accumulated clock count refers to the number of clock windows of the clocks to be verified in a preset time period, that is, the number of clock cycles of the clocks to be verified in the preset time period is counted.
Step S103, calculating a difference between the accumulated clock count and the standard clock count to obtain an accumulated clock difference.
The standard clock count is the accumulated clock number of the standard clock in the clock window, the difference between the accumulated clock count and the standard clock count is calculated, and the smaller the difference between the accumulated clock count and the standard clock count is, the closer the clock to be measured is to the ideal state is.
And step S104, comparing the maximum value in the accumulated clock difference value with a preset clock threshold value, and determining the test result of the chip to be tested based on the comparison result.
Wherein, the clock threshold value can be set by a user according to the test precision.
In some embodiments, the maximum value of the accumulated clock difference values is compared with a preset clock threshold value, and if the maximum value of the accumulated clock difference values is greater than or equal to the clock threshold value, the test result indicates that the chip to be tested does not meet the design requirement. And if the maximum value in the accumulated clock difference value is smaller than the clock threshold value, the test result indicates that the chip to be tested meets the design requirement.
In some embodiments, step S103 may also be obtained in another manner, that is, each accumulated clock difference value is compared with a clock threshold, and if one accumulated clock difference value is greater than or equal to the clock threshold, the test result indicates that the chip to be tested does not meet the design requirement. And if each accumulated clock difference value is smaller than the clock threshold value, the test result indicates that the chip to be tested meets the design requirement.
In some embodiments, after comparing the maximum value of the accumulated clock difference values with a preset clock threshold and determining the test result of the chip to be tested based on the comparison result, the method may further include storing the test result for querying the test result.
In some embodiments, the test results are stored in a register.
In the clock testing method provided by this embodiment, a clock window is counted based on a standard clock, and clock counts are accumulated; the difference value of the accumulated clock count and the standard clock count is calculated to obtain an accumulated clock difference value, the accumulated clock difference value is compared with a preset clock threshold value, and a test result of the chip to be tested is determined based on the comparison result. In addition, compared with professional clock testing equipment, the cost is greatly reduced. In addition, the clock testing method can be directly applied to a mass production testing platform.
In a second aspect, an embodiment of the present application provides a clock testing apparatus. Fig. 3 is a schematic block diagram of a clock testing apparatus according to an embodiment of the present disclosure.
As shown in fig. 3, the clock test apparatus includes:
the clock generator 301 is configured to obtain a clock window based on a clock to be tested generated by the chip to be tested.
The chip to be tested can be any chip to be tested, and the clock to be tested is a clock generated by the chip to be tested. The clock window is a window obtained based on the clock to be measured, and the size of the clock window is preset.
In some embodiments, the size of the clock window may be adjusted by a register. The size of the clock window is set by the user according to the test requirements. The clock window may be any value between 20 microseconds and 500 microseconds.
And a clock management module 302 for generating a standard clock.
And the frequency of the standard clock is greater than that of the clock to be tested. The standard clock may be generated by an FPGA.
In some embodiments, the standard clock is a delay locked loop or a delay locked loop.
A counter 303, configured to count the clock window based on the standard clock to obtain an accumulated clock count.
In some embodiments, the counter 303 may count the clock window with a high level of the clock window or count the clock window with a low level of the clock window. After the count result of the clock window is obtained, the count result is stored in a register.
In some embodiments, the address and function descriptions of the registers are as in table 1.
TABLE 1
And the calculating module 304 is configured to calculate a difference between the accumulated clock count and the standard clock count to obtain an accumulated clock difference.
In some embodiments, the difference between the accumulated clock count for each clock window and a preset clock count is calculated to obtain a corresponding accumulated clock difference value.
And the judging module 305 is configured to compare the accumulated clock difference with a preset clock threshold, and determine a test result of the chip to be tested based on the comparison result.
Wherein, the clock threshold value can be set by a user according to the test precision.
In some embodiments, the determining module 305 compares the maximum value of the accumulated clock difference with a preset clock threshold, and if the maximum value of the accumulated clock difference is greater than or equal to the clock threshold, the test result is that the chip under test does not meet the design requirement. And if the maximum value in the accumulated clock difference value is smaller than the clock threshold value, the test result indicates that the chip to be tested meets the design requirement.
In some embodiments, the determining module 305 may further compare each accumulated clock difference value with a clock threshold, and if at least one of the accumulated clock difference values is greater than or equal to the clock threshold, the test result is that the chip under test does not meet the design requirement. And if each accumulated clock difference value is smaller than the clock threshold value, the test result indicates that the chip to be tested meets the design requirement.
In some embodiments, after comparing the maximum value of the accumulated clock difference values with a preset clock threshold and determining the test result of the chip to be tested based on the comparison result, the method may further include storing the test result for querying the test result.
In some embodiments, the test results may be stored in a register. When the test result is that the maximum value of the accumulated clock difference values is greater than the clock threshold, the register 0xA is set to "1".
In some embodiments, the clock testing apparatus further includes a read-write memory for storing data obtained by the counter and the accumulation module. The read-write memory can adopt a 20-bit memory.
In this embodiment, the clock test apparatus is an apparatus obtained based on a Field-Programmable Gate Array (FPGA).
In the clock testing apparatus provided in this embodiment, the counter counts the clock window based on the standard clock to obtain the accumulated clock count, and the calculating module obtains the difference between the accumulated clock count and the standard clock count to obtain the accumulated clock difference; the accumulated clock difference value is compared with a preset clock threshold value by using the judging module, and the test result of the chip to be tested is determined based on the comparison result. Compared with professional clock test equipment, the cost is greatly reduced. In addition, the clock testing device can be directly applied to a mass production testing platform.
In a third aspect, an embodiment of the present application provides a test platform, which can be applied to mass production tests on chips.
Fig. 4 is a schematic block diagram of a test platform according to an embodiment of the present disclosure. As shown in fig. 4, the test platform 400 includes a clock testing apparatus 401, wherein the clock testing apparatus 401 employs the clock testing apparatus provided in the embodiment of the present application. The clock testing apparatus 401 receives a clock to be tested generated by the chip to be tested 402, and is configured to measure the precision of the clock to be tested, so as to obtain whether the chip to be tested meets the design requirement of the clock precision.
Fig. 5 is a schematic block diagram of another test platform provided in an embodiment of the present application. As shown in fig. 5, in some embodiments, the test platform 500 includes:
the clock distributor 501 is configured to distribute the clocks to be tested generated by the chip to be tested 503 to obtain at least one path of clocks to be tested.
The clock testing device 502 is used for testing the accumulated clock jitter of the chip. The clock testing apparatus 502 is connected to one of the clocks to be tested, and the other clocks to be tested can be used for other test items.
The level of the clock to be tested output by the chip to be tested may be different from the level of the standard clock, and in order to make the level of the clock to be tested and the level of the standard clock consistent, the test platform 500 further includes a level conversion module.
As shown in fig. 6, the test platform 600 includes:
the clock distributor 601 is configured to distribute the clocks to be tested generated by the chip 605 to be tested, so as to obtain at least one path of clocks to be tested. For example, the frequency division is performed on the clock to be tested to obtain a first path of clock to be tested and a second path of clock to be tested.
The clock testing apparatus 602 is connected to the first path of clock to be tested, and is configured to test accumulated clock jitter of the chip.
The level conversion module 603 is disposed in a clock path between the clock distributor 601 and the clock testing apparatus 602, and is configured to convert a level of the first path of clock to be tested to be consistent with a level of the standard clock.
And the machine interface 604 is connected with the second path of clock to be tested and is used for measuring other test items of the chip.
In this embodiment, the clock testing apparatus may communicate with the external device through I2C, and the test platform may determine whether the test result passes by reading the register state in the clock testing apparatus.
In some embodiments, the clock testing device may adopt an FPGA clock testing device, and the testing standards of the FPGA are set to meet various testing requirements. Moreover, the FPGA can also increase the frequency meter test, namely one FPGA completes all tests related to the clock performance parameters in the mass production test.
According to the test platform provided by the embodiment of the application, the clock test device provided by the embodiment of the application is adopted to count the clock windows based on the standard clock, and the accumulated clock difference of each clock window is obtained; the accumulated clock difference is compared with a preset clock threshold value, and a test result of the chip to be tested is determined based on the comparison result. Moreover, compared with professional clock testing equipment, the cost is greatly reduced.
In a fourth aspect, an embodiment of the present application provides a method for testing mass production. Fig. 7 is a flowchart of a mass production testing method according to an embodiment of the present application. As shown in fig. 7, the mass production test method includes:
step S701, acquiring a clock to be tested generated by a chip to be tested.
And connecting the chip to be tested with the mass production test platform so as to connect the clock to be tested generated by the chip to be tested into the clock test device.
Step S702, a clock window is obtained based on the clock to be tested.
In some embodiments, the size of the clock window is adjusted by a register.
Step S703, counting the clock window based on the standard clock, and obtaining the accumulated clock difference.
And the frequency of the standard clock is greater than that of the clock to be tested. The standard clock may be an FPGA clock.
In some embodiments, the clock window is counted using either a high or low level of the clock window.
In step S704, the difference between the accumulated clock count and the standard clock count is calculated to obtain an accumulated clock difference.
Step S705, comparing the accumulated clock difference with a preset clock threshold, and determining a test result of the chip to be tested based on the comparison result.
Wherein, the clock threshold value can be set by a user according to the test precision.
In some embodiments, the maximum value of the accumulated clock difference values is compared with a preset clock threshold value, and if the maximum value of the accumulated clock difference values is greater than or equal to the clock threshold value, the test result indicates that the chip to be tested does not meet the design requirement. And if the maximum value in the accumulated clock difference value is smaller than the clock threshold value, the test result indicates that the chip to be tested meets the design requirement.
In some embodiments, each accumulated clock difference value is compared with a clock threshold value, and if at least one accumulated clock difference value is greater than or equal to the clock threshold value, the test result indicates that the chip to be tested does not meet the design requirement. And if each accumulated clock difference value is smaller than the clock threshold value, the test result indicates that the chip to be tested meets the design requirement.
In some embodiments, after comparing the maximum value of the accumulated clock difference values with a preset clock threshold and determining the test result of the chip to be tested based on the comparison result, the method may further include storing the test result for querying the test result.
In some embodiments, the test results may be stored in a register.
In some embodiments, before acquiring the clock to be tested generated by the chip to be tested, the method may further include: and the chip to be tested generates a clock to be tested and delays the clock by a preset delay length.
Wherein the delay length is determined by the test requirement of the chip to obtain enough clock cycles to be tested. The delay length depends on the test requirements of the chip. The delay length may be set to a millisecond level, for example, to several tens of milliseconds.
In some embodiments, before the chip under test generates the clock under test and delays for the preset time length, the method further includes: in case the standard clock generator is turned off, the clock threshold and the clock window are set, i.e. the enabling of the standard clock generator is turned off before the clock threshold and the clock window are set.
In some embodiments, in order to stabilize the clock to be tested output by the chip to be tested, after the enable of the chip to be tested is turned on, the enable of the standard clock generator is turned on after delaying for a preset time.
Fig. 8 is a diagram of measurement data and measurement waveforms obtained by measuring a chip to be measured. The method comprises the following steps of (a) obtaining a measurement waveform diagram by adopting a test of a mass production test method provided by the embodiment of the application; (b) is a measurement oscillogram obtained by testing with an oscilloscope; (c) and (d) obtaining measurement data for a test using the mass production test method provided by the embodiment of the present application; wherein the abscissa represents the number of clock windows and the ordinate represents the counter difference; wherein, the test result of (c) is that the chip test requirement is satisfied, and the test result of (d) is that the chip test requirement is not satisfied.
As can be seen from fig. 8(a), the test result of the chip to be tested using the mass production test method provided in the embodiment of the present application needs 10 ns. As can be seen from fig. 8(b), the test using the oscilloscope requires 20ns to obtain the test result. Therefore, the mass production test method provided by the embodiment of the application can obtain the test result more quickly under the same test condition.
As can be seen from fig. 8(c) and 8(d), test results can be obtained within several hundred clock windows.
The steps of the above methods are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the same logical relationship is included, which are all within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the algorithms or processes or to introduce insignificant design changes to the core design without changing the algorithms or processes.
According to the mass production test method provided by the embodiment of the application, the clock window is counted based on the standard clock to obtain the accumulated clock count, and the difference value between the accumulated clock count and the standard clock count is calculated to obtain the accumulated clock difference value; the accumulated clock difference value is compared with a preset clock threshold value, the test result of the chip to be tested is determined based on the comparison result, and the accumulated clock of the clock to be tested can be directly obtained, so that the test efficiency is improved, the misjudgment is reduced, and the method can be applied to millisecond-level test. Moreover, compared with professional clock testing equipment, the cost is greatly reduced.
Each module in the present embodiment is a logical module, and in practical applications, one logical unit may be one physical unit, may be a part of one physical unit, or may be implemented by a combination of a plurality of physical units. In addition, in order to highlight the innovative part of the present application, a unit that is not so closely related to solving the technical problem proposed by the present application is not introduced in the present embodiment, but it does not indicate that no other unit exists in the present embodiment.
The present embodiments also provide an electronic device, comprising one or more processors; when the one or more programs are executed by the one or more processors, the one or more processors implement the clock testing method and the mass production testing method provided by the embodiment, and in order to avoid repeated descriptions, specific steps of the clock testing method and the mass production testing method are not described herein again.
The present embodiment further provides a computer readable medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the clock testing method and the mass production testing method provided in the present embodiment, and in order to avoid repeated descriptions, detailed steps of the clock testing method and the mass production testing method are not described herein again.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices, as claimed above, may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than others, combinations of features of different embodiments are meant to be within the scope of the embodiments and form different embodiments.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present application, and that the present application is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the application, and these changes and modifications are to be considered as the scope of the application.
Claims (11)
1. A clock testing method, comprising:
acquiring a clock window based on a clock to be tested generated by a chip to be tested, wherein the size of the clock window is preset;
counting the clock window by using a standard clock to obtain an accumulated clock count; the frequency of the standard clock is greater than that of the clock to be tested;
calculating the difference value between the accumulated clock count and the standard clock count to obtain an accumulated clock difference value;
and comparing the accumulated clock difference value with a preset clock threshold value, and determining the test result of the chip to be tested based on the comparison result.
2. The clock testing method of claim 1, wherein the counting the clock window with a standard clock and obtaining a cumulative clock count comprises:
counting the clock window with a high level or a low level of the clock window.
3. The clock testing method of claim 1, wherein after comparing the accumulated clock difference value with a preset clock threshold and determining a testing result of the chip under test based on the comparison result, the method further comprises:
and storing the test result for inquiring the test result.
4. A clock test apparatus comprising:
the clock generator is used for acquiring a clock window based on a clock to be detected generated by the chip to be detected; wherein the size of the clock window is preset;
the clock management module is used for generating a standard clock; the frequency of the standard clock is greater than that of the clock to be tested;
a counter for counting the clock window based on a standard clock to obtain an accumulated clock count;
the calculation module is used for calculating the difference value between the accumulated clock count and the standard clock count to obtain an accumulated clock difference value;
and the judging module is used for comparing the accumulated clock difference value with a preset clock threshold value and determining the test result of the chip to be tested based on the comparison result.
5. The clock test apparatus of claim 4, wherein the clock management module is a delay locked loop or a delay locked loop.
6. A test platform comprising a clock test apparatus, wherein the clock test apparatus employs the clock test apparatus of claim 4 or 5.
7. The test platform of claim 6, further comprising:
the clock distributor is used for distributing the clock to be tested generated by the chip to be tested to obtain at least two paths of clocks to be tested, wherein one path of clock to be tested is connected with the clock testing device.
8. The test platform of claim 7, further comprising:
and the level conversion module is used for converting the level of the clock to be tested connected with the clock testing device into the level consistent with the level of the standard clock.
9. A method of mass production testing, comprising:
acquiring a clock to be tested generated by a chip to be tested;
generating a clock window based on the clock to be tested; wherein the size of the clock window is preset;
counting the clock window by using a standard clock to obtain an accumulated clock count; the frequency of the standard clock is greater than that of the clock to be tested;
calculating the difference value between the accumulated clock count and the standard clock count to obtain an accumulated clock difference value;
and comparing the accumulated clock difference with a preset clock threshold value, and determining the test result of the chip to be tested based on the comparison result.
10. The mass production test method according to claim 9, wherein before obtaining the clock to be tested generated by the chip to be tested, the method further comprises:
and delaying the chip to be tested by a preset delay length after the chip to be tested generates the clock to be tested.
11. The mass production test method according to claim 9, wherein the step of delaying the time for the preset time length after the chip under test generates the clock under test further comprises:
setting the clock threshold and the clock window with the standard clock generator turned off.
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