CN113140539A

CN113140539A - Semiconductor device and method of zone shielding using bond wires

Info

Publication number: CN113140539A
Application number: CN202110052611.0A
Authority: CN
Inventors: Y·C·金; C·H·李; W·G·金
Original assignee: Stats Chippac Pte Ltd
Current assignee: Stats Chippac Pte Ltd
Priority date: 2020-01-17
Filing date: 2021-01-15
Publication date: 2021-07-20
Anticipated expiration: 2041-01-15
Also published as: CN113140539B

Abstract

Semiconductor device and method of zone shielding using bond wires. A semiconductor device has a substrate and a plurality of bonding wires are disposed in a pattern across the substrate. The pattern of bond wires may be a plurality of rows of bond wires. A plurality of electrical components are disposed above the substrate as SIP modules. An encapsulant is deposited over the substrate, the electrical components, and the bond wires. Openings are formed in the encapsulant that extend to the bond lines. The opening may be a groove extending across a bond wire disposed on the substrate, or a plurality of openings individually exposing each of a plurality of bond wires. The conductive material is disposed in the opening. A shielding layer formed over the encapsulant and in contact with the conductive material. The shielding layers, conductive materials, and bond wires reduce the effects of EMI, RFI, and other inter-device interference.

Description

Semiconductor device and method of zone shielding using bond wires

Require domestic priority

This application claims the benefit of united states provisional application No. 62/962,288, filed on day 1, 17, 2020 and incorporated herein by reference.

Technical Field

The present invention relates generally to semiconductor devices and, more particularly, to semiconductor devices and methods of forming a shield layer in contact with bond wires disposed between electrical components to form a compartmentalized shield in a system-in-package (SIP) module.

Background

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide variety of functions such as signal processing, high speed computing, transmitting and receiving electromagnetic signals, controlling electronics, photovoltaics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices, particularly in high frequency applications such as Radio Frequency (RF) wireless communications, often contain one or more Integrated Passive Devices (IPDs) to perform the necessary electrical functions. IPDs are susceptible to electromagnetic interference (EMI), Radio Frequency Interference (RFI), harmonic distortion, or other inter-device (inter-device) interference, such as capacitive, inductive, or conductive coupling, also known as crosstalk, which may interfere with their operation. High speed switching of digital circuits also generates interference.

For higher density and extended electrical functionality in small spaces, multiple semiconductor dies and discrete IPDs may be integrated into a system-in-package (SIP) module. Within the SIP module, a semiconductor die and a discrete IPD are mounted to the substrate for structural support and electrical interconnection. An encapsulant is deposited over the semiconductor die, the discrete IPD and the substrate. A shield layer is formed over the encapsulant to isolate the sensitive circuitry. In many applications, the encapsulant must be planarized with a grinder in order to make a good connection for the barrier layer. The grinding operation increases the manufacturing cost.

Drawings

FIGS. 1a-1c illustrate a semiconductor wafer having a plurality of semiconductor die separated by saw streets (saw streets);

FIGS. 2a-2m illustrate a process of forming a shielding layer in contact with bond wires between electrical components disposed in a SIP module;

FIGS. 3a-3f illustrate various shapes of openings for exposing bond wires;

FIGS. 4a-4k illustrate a process of forming a shielding layer in contact with rows of bond wires disposed between electrical components in a SIP module;

FIG. 5 shows another SIP module having a shield layer in contact with rows of bond wires disposed between electrical components;

FIG. 6 shows another SIP module having a shield layer in contact with rows of bond wires disposed between electrical components;

FIGS. 7a-7d illustrate other patterns of bond wires disposed between electrical components in a SIP module;

8a-8b illustrate another SIP module having a shield layer in contact with a plurality of rows of bond wire loops disposed between electrical components;

FIGS. 9a-9b illustrate another SIP module having a shield layer in contact with a plurality of rows of bond wire loops disposed over electrical components; and

fig. 10 shows a Printed Circuit Board (PCB) with a different type of package mounted to a surface of the PCB.

Detailed Description

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numbers represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of words and, thus, may refer to both a single semiconductor device and a plurality of semiconductor devices.

Semiconductor devices are typically manufactured using two complex manufacturing processes: front end manufacturing and back end manufacturing. Front end fabrication involves forming a plurality of dies on a surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form functional circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, produce the relationship between voltage and current required to perform a circuit function.

Back-end fabrication refers to the dicing or singulating of the finished wafer into individual semiconductor dies and packaging of the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate semiconductor dies, the wafer is scribed (score) and broken along non-functional areas of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade (saw blade). After singulation, the individual semiconductor dies are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections may be made with conductive layers, bumps (bump), stud bumps (stub bump), conductive paste, or wire bonding. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

Fig. 1a shows a semiconductor wafer 100 having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk (bulk) material, 102 for structural support. A plurality of semiconductor die or components 104 are formed on the wafer 100 separated by inactive, inter-die wafer regions or streets 106. The saw streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100 and 450 millimeters (mm).

Fig. 1b shows a cross-sectional view of a portion of a semiconductor wafer 100. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110 that contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 110 to implement analog circuits or digital circuits, such as Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), memory, or other signal processing circuits. Semiconductor die 104 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. The conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layer 112 operates as contact pads that are electrically connected to circuitry on the active surface 110.

A conductive bump material is deposited over conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop (ball drop) or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux (flux) solution. For example, the bump material may be eutectic (eutectic) Sn/Pb, high lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, the bump 114 is formed over an Under Bump Metallization (UBM) with a wetting layer, a barrier layer, and an adhesion layer. Bumps 114 may also be compression bonded or thermo-compression bonded to conductive layer 112. Bumps 114 represent one type of interconnect structure that can be formed over conductive layer 112. The interconnect structure may also use bond wires, conductive paste, stud bumps, micro bumps, or other electrical interconnects.

In fig. 1c, semiconductor wafer 100 is singulated through saw streets 106 into individual semiconductor die 104 using a saw blade or laser cutting tool 118. Individual semiconductor dies 104 can be inspected and electrically tested for post-KGD singulation identification.

Figures 2a-2m illustrate a process of forming a shielding layer in direct contact with bond wires between electrical components disposed in a SIP module. Fig. 2a shows a cross-sectional view of a substrate 120 comprising a conductive layer 122 and an insulating layer 124. Conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Conductive layer 122 provides a horizontal electrical interconnect across substrate 120 and a vertical electrical interconnect between top surface 126 and bottom surface 128 of substrate 120. Portions of conductive layer 122 may be electrically common or electrically isolated, depending on the design and function of semiconductor die 104 and other electrical components. The insulating layer 124 contains one or more layers of silicon dioxide (SiO 2), silicon nitride (Si 3N 4), silicon oxynitride (SiON), tantalum pentoxide (Ta 2O 5), aluminum oxide (Al 2O 3), solder resist, polyimide, benzocyclobutene (BCB), Polybenzoxazole (PBO), and other materials having similar insulating and structural properties. Insulating layer 124 provides isolation between conductive layers 122.

In FIG. 2b, a plurality of electrical components 130a-130g are mounted to substrate 120 and electrically and mechanically connected to conductive layer 122. Each of the electrical components 130a-130g is positioned over the substrate 120 using a pick and place operation. For example, the electrical component 130a may be the semiconductor die 104 from fig. 1c having the active surface 110 and the bumps 114 oriented toward the surface 126 of the substrate 120. Alternatively, the electrical components 130a-130g may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, or IPDs, such as resistors, capacitors, and inductors. Electrical components 130a-130g are reflowed to make mechanical and electrical connections to conductive layer 122, as shown in figure 2 c.

As a feature of the SIP module, a plurality of bond wires 132 are formed in a pattern across the bond wire attachment area 134 of fig. 2 c. The bond wires 132 may be Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Each bond wire 132 has a ball (bulbus) or circular portion 132a and a stem (stem) portion 132 b. The bulbous portion 132a may be formed by pressing a straight wire heated to its melting point into the conductive layer 122. Bulbous portion 132a is thus joined to conductive layer 122, leaving stem portion 132b extending from the bulbous portion. FIG. 2c shows bond wires 132 formed after the electrical components 130a-130g are mounted to the substrate 120. In another embodiment, the bond wires 132 are formed on the substrate 120 in bond wire attachment areas 134, as shown in FIG. 2d, prior to mounting the electrical components 130a-130 g. In one embodiment, the bond wires 132 may be formed as rows on the substrate 120 in the bond wire attachment areas 134 prior to mounting the electrical components 130a-130 g. FIG. 2e shows an orthogonal view (orthogonalization) of the rows of bond wires 132 formed on the surface 126 of the substrate 120 in the bond wire attachment area 134 prior to mounting the electrical components 130a-130 g. The electrical components 130a-130g are mounted after the bond wires 132 are formed, resulting in a transitional (inter) SIP module similar to FIG. 2 c.

In FIG. 2f, an encapsulant or molding compound 138 is deposited over the electrical components 130a-103g, the bond wires 132, and the substrate 120 using a solder paste printing (paste printing), compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 138 may be a polymer composite material such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 138 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. In particular, after bonding the bond wires and electrical components to the substrate, an encapsulant 138 is deposited over the electrical components 130a-103g, the bond wires 132, and the substrate 120. Encapsulant 138 is deposited with sufficient thickness to cover bond wires 132.

In fig. 2g, a portion of the encapsulant 138 is removed by an etching process, mechanical sawing, or Laser Direct Ablation (LDA) using a laser 144 to form a trench or opening 146 that extends substantially across or completely across the substrate 120. The depth of the groove 146 is sufficient to expose the side surface of the rod portion 132 b. The groove 146 may have vertical or sloped side surfaces. Fig. 2h shows an orthogonal view of a groove 146 formed in the encapsulant 138 with the exposed stem portion 132b of the bond wire 132 within the groove. In another embodiment, a separate opening 148 is formed by LDA over each stem portion 138b of the bond wire 132. Fig. 2i shows an orthogonal view of the encapsulant 138 with the exposed stem portion 132b of the bond wire 132 through a separate opening 148.

In fig. 2j, a conductive paste 150 is deposited into the trench 146. In one embodiment, the conductive paste 150 is a solder paste. Fig. 2k shows an orthogonal view of the conductive paste 150 in the trenches 146 of the row that extends substantially across or completely across the substrate 120 to contact the stem portion 132 b. The side surfaces of the stem portion 132b extend into the trench 146, i.e., above the bottom surface of the trench, to expose more of the stem portion into the conductive paste 150 for additional electrical contact surface area of the side surfaces of the stem portion. FIG. 2l shows an orthogonal view of conductive paste 150 in the openings 148 of each stem portion 132b in the individual contact rows according to FIG. 2 i.

Fig. 3a-3f show various types of openings 146 filled with conductive paste 150. Fig. 3a shows a beveled side surface 152 of the groove 146 extending to the top surface of the rod portion 132 b. FIG. 3b shows vertical side surfaces 154 of channel 146 extending to the top surface of rod portion 132b and within the footprint (footing) of rod portion 132 b. Fig. 3c shows a beveled side surface 156 of the groove 146 extending to the top surface of the rod portion 132 b. The grooves 146 extend beyond the footprint of the stem portion 132 b. Fig. 3d shows vertical side surfaces 158 of groove 146 extending to the top surface of rod portion 132 b. The grooves 146 extend beyond the footprint of the stem portion 132 b. Fig. 3e shows beveled side surfaces 160 of the channel 146 extending below the top surface of the rod portion 132b, leaving the side surfaces of the rod portion 132b exposed within the channel 146. The grooves 146 extend beyond the footprint of the stem portion 132 b. Fig. 3f shows vertical side surfaces 162 of channel 146 extending below the top surface of rod portion 132b, leaving the side surfaces of rod portion 132b exposed within channel 146. The grooves 146 extend beyond the footprint of the stem portion 132 b. Fig. 3e and 3f are similar to the embodiment of fig. 2j, with the exposed side surface of the stem portion 132b increasing the electrical contact surface area with the side surface of the stem portion.

The electrical components 130a-130g may contain IPDs, which are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included within electrical components 130a-130g provide the electrical characteristics needed for high frequency applications, such as resonators, high pass filters, low pass filters, band pass filters, symmetric Hi-Q resonant transformers, and tuning capacitors. In another embodiment, electrical components 130a-130g contain digital circuits that switch at high frequencies, which may interfere with the operation of the IPD in the SIP module.

Continuing from fig. 2l, an electromagnetic shield layer 170 is formed or disposed over surface 142 of encapsulant 138 and conductive paste 150 within trench 146, as shown in fig. 2 m. The shield layer 170 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, the shield layer 170 may be carbonyl iron, stainless steel, nickel silver (nickel silver), low carbon steel, silicon-iron steel, foil, conductive resin, carbon black, aluminum flake (aluminum flake), and other metals and composites capable of reducing the effects of EMI, RFI, and other inter-device interference. The conductive paste 150 is reflowed to make electrical connection between the shielding layer 170 and the bonding wires 132. In particular, the shield layer 170 uses the trench 146 or opening 148 and the conductive paste 150 to make electrical contact with the bond wire 132 for external grounding. In addition, the shielding layer 170 covers a side surface 172 of the encapsulant 138 and a side surface 174 of the substrate 120.

The SIP module 176 containing the electrical components 130a-130g is electrically connected to the bond wires 132 between the substrate 120 and the electromagnetic shield layer 170. The top end of stem portion 132b is exposed from encapsulant 138 within either trench 146 or separate opening 148. The trench 146 is filled with a conductive paste 150. A shield layer 170 is formed over the SIP module and electrically connected to the bond wires 132 by reflowing the conductive paste 150. In particular, the stem portion 132b of the bonding wire 132 is electrically connected to the shielding layer 170 using a conductive paste. The use of the trench 146 or opening 148 and the conductive paste 150 eliminates the need to grind the top surface of the encapsulant 138.

In another embodiment, the layout of the bond wires 132 may have multiple patterns. For example, before the electrical components 130a-130g are mounted, a plurality of rows (2 or more rows) of bond wires 132 are formed on the substrate 120 in a bond wire attachment area 134, as shown in FIG. 4 a. Elements having a similar function to that described in fig. 2a-2m are assigned the same reference numerals. FIGS. 4b-4c are orthogonal views of rows of bond wires 132 formed on the surface 126 of the substrate 120 in a bond wire attachment area 134 prior to mounting the electrical components 130a-130 g. The individual bond wires 132 may be aligned between rows as shown in fig. 4b or offset between rows as shown in fig. 4 c. In FIG. 4d, the electrical components 130a-130g are mounted after forming multiple rows of bond wires 132, resulting in a transitional SIP module similar to FIG. 2 c.

In FIG. 4e, an encapsulant or molding compound 138 is deposited over the electrical components 130a-103g, the bond wires 132, and the substrate 120 using a solder paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant 138 may be a polymer composite material such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant 138 is electrically non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. In particular, after bonding the bond wires and electrical components to the substrate, an encapsulant 138 is deposited over the electrical components 130a-103g, the bond wires 132, and the substrate 120. Encapsulant 138 is deposited with sufficient thickness to cover the rows of bond wires 132.

In fig. 4f, a portion of the encapsulant 138 is removed by an etching process, mechanical sawing, or LDA using a laser 144 to form a trench 146 that extends substantially across or completely across the substrate 120. The depth of the grooves 146 is sufficient to expose the side surfaces of the rows of stem portions 132 b. The groove 146 may have vertical or sloped side surfaces. Fig. 4g shows an orthogonal view of encapsulant 138 with grooves 146 exposing rows of stem portions 132b of bond wires 132. In another embodiment, a separate opening 148 is formed by LDA over each stem portion 138b of the bond wire 132, as seen in fig. 4 h.

In fig. 4i, a conductive paste 150 is deposited into the trenches 146, the trenches 146 being made wide enough to expose multiple rows of bond wires. Fig. 4j shows an orthogonal view of conductive paste 150 in trenches 146 extending substantially across or completely across substrate 120 having a width sufficient to expose multiple rows of stem portions 132 b. The side surface of stem portion 132b extends over trench 146 to expose more of the stem portion for additional electrical contact surface area of the side surface of the stem portion. Alternatively, conductive paste 150 is deposited into individual openings 148 to contact individual stem portions 132b in multiple rows of bond wires 132, as shown in fig. 4 k.

Continuing from fig. 4i, as shown in fig. 5, an electromagnetic shield layer 170 is formed over surface 142 of encapsulant 138 and conductive paste 150 within trench 146. The shield layer 170 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, the shield layer 170 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, silicon-iron steel, foil, conductive resin, carbon black, aluminum foil, and other metals and composite materials capable of reducing the effects of EMI, RFI, and other inter-device interference. The conductive paste 150 is reflowed to make electrical connection between the shielding layer 170 and the bonding wires 132. In particular, the shielding layer 170 makes electrical contact with the bond wires 132 for external grounding. In addition, the shielding layer 170 covers a side surface 172 of the encapsulant 138 and a side surface 174 of the substrate 120.

Continuing from fig. 4k, as shown in fig. 6, an electromagnetic shield layer 170 is formed over the surface 142 of the encapsulant 138 and the conductive paste 150 within the individual openings 148. The shield layer 170 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Alternatively, the shield layer 170 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, silicon-iron steel, foil, conductive resin, carbon black, aluminum foil, and other metals and composite materials capable of reducing the effects of EMI, RFI, and other inter-device interference. The conductive paste 150 is reflowed to make electrical connection between the shielding layer 170 and the bonding wires 132. In particular, the shield layer 170 uses the trench 146 or opening 148 and the conductive paste 150 to make electrical contact with the bond wire 132 for external grounding. In addition, the shielding layer 170 covers a side surface 172 of the encapsulant 138 and a side surface 174 of the substrate 120.

FIGS. 7a-7d show additional layouts of bond wires 132 arranged to demarcate one or more electrical components 130a-130 g. In fig. 7a, the bond wires 132 are arranged to provide four

compartments

178a, 178b, 178c, and 178d in which one or more electronic components 130a-130g are disposed. In fig. 7b, the bonding wires 132 are arranged in an inner square with an outer divider (divider) to provide five

compartments

182a, 182b, 182c, 182d and 182e, in which one or more electronic components 130a-130g are disposed. In fig. 7c, the bond wires 132 are arranged in an inner square with an outer diagonal divider to provide five

compartments

184a, 184b, 184c, 184d and 184e in which the electronic components 130a-130g are disposed. In fig. 7d, the bond wires 132 are arranged to provide

individual compartments

186a, 186b, 186c, 186d, 186e, and 186f in which one or more electronic components 130a-130g are disposed. The combination of the bond wires 132 and the shielding layer 170 compartmentalize the electrical components 103a-130g for electrical isolation to reduce the effects of EMI, RFI and other inter-device interference.

Fig. 8a-8b illustrate another embodiment having a bond wire loop 190 formed over the substrate 120. In fig. 8a, bond wire loop 190 makes electrical contact with conductive layer 122 on substrate 120 at both ends of the loop. In FIG. 8b, the electrical components 130a-130g are mounted to a substrate as described in FIG. 2 c. Encapsulant 138 is deposited over electrical components 130a-130g, wire bond loops 190, and substrate 120, as depicted in figure 2 f. As depicted in fig. 2g-2i, a groove 146 is formed in encapsulant 138 to expose bond wire loop 190. As depicted in fig. 2j, a conductive paste 150 is deposited in the trench 146. As depicted in fig. 2m, a shield layer 170 is formed over the encapsulant 138 and the conductive paste 150 within the trench 146. The conductive paste 150 is reflowed to make electrical connection between the shield layer 170 and the bond wire loops 190. In particular, the shield layer 170 uses the trench 146 or opening 148 and the conductive paste 150 to make electrical contact with the bond wire loop 190 for external grounding.

Figures 9a-9b illustrate another embodiment having a wire bond loop 196 formed over electrical components 130e-130f on substrate 120. In FIG. 9a, wire bond loop 196 extends over electrical components 130e-130f and makes electrical contact with conductive layer 122 on substrate 120 at both ends of the loop. In FIG. 9b, the electrical components 130a-130g are mounted to a substrate as described in FIG. 2 c. Encapsulant 138 is deposited over electrical components 130a-130g, bond wire loops 196, and substrate 120, as depicted in figure 2 f. As depicted in fig. 2g-2i, a groove 146 is formed in encapsulant 138 to expose bond wire loop 196. As depicted in fig. 2j, a conductive paste 150 is deposited in the trench 146. As depicted in fig. 2m, a shield layer 170 is formed over the encapsulant 138 and the conductive paste 150 within the trench 146. The conductive paste 150 is reflowed to make electrical connection between the shield layer 170 and the bond wire loop 196. In particular, the shield 170 makes electrical contact with the bond wire loop 196 for external grounding.

The SIP module 192 from figure 8b and the SIP module 198 from figure 9b contain electrical components 130a-130g that utilize bond wires 132 electrically connected between the substrate 120 and the electromagnetic shield layer 170. The top of

bond wire loop

190 or 196 is exposed from encapsulant 138 by way of groove 146. The trench 146 is filled with a conductive paste 150. The shield layer 170 is formed over the SIP module and electrically connected to the

wire loop

190 or 196 by reflowing the conductive paste 150. In particular, the top of the

wire loop

190 or 196 is electrically connected to the shield layer 170 using conductive paste. The use of the trench 146 or opening 148 and the conductive paste 150 eliminates the need for the abrasive encapsulant 138.

Fig. 10 shows an electronic device 200 having a chip carrier substrate or PCB 202 with a plurality of semiconductor packages mounted on a surface of PCB 202, including

SIP modules

176, 192, and 198. The electronic device 200 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

Electronic device 200 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 200 may be a sub-component of a larger system. For example, the electronic device 200 may be part of a tablet computer, cellular telephone, digital camera, communication system, or other electronic device. Alternatively, the electronic device 200 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. A semiconductor package may include a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for products to be accepted by the market. The distance between the semiconductor devices can be reduced to achieve higher density.

In fig. 10, PCB 202 provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. The conductive signal traces 204 are formed over or within the surface of the PCB 202 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. The signal traces 204 provide electrical communication between each of the semiconductor packages, the mounted components, and other external system components. Traces 204 also provide power and ground connections to each of the semiconductor packages.

In some embodiments, the semiconductor device has two package levels (levels). First level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching an intermediate substrate to the PCB. In other embodiments, the semiconductor device may have only a first level package, where the die is mechanically and electrically mounted directly to the PCB.

For illustrative purposes, several types of first level packages are shown on the PCB 202, including a bond wire package 206 and a flip chip 208. In addition, several types of second level packages, including Ball Grid Array (BGA) 210, Bump Chip Carrier (BCC) 212, Land Grid Array (LGA) 216, multi-chip module (MCM) 218, quad flat (quad flat) non-leaded package (QFN) 220 and quad flat package 222, embedded wafer level ball grid array (eWLB) 224, and Wafer Level Chip Scale Package (WLCSP) 226 are shown mounted on PCB 202. In one embodiment, the eWLB 224 is a fan-out wafer level package (Fo-WLP) and the WLCSP 226 is a fan-in wafer level package (Fi-WLP). Any combination of semiconductor packages configured with any combination of first and second level packaging styles, as well as other electronic components, may be connected to PCB 202 depending on system requirements. In some embodiments, the electronic device 200 comprises a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and less expensive to manufacture, resulting in lower cost for the consumer.

While one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

providing a bonding wire on a substrate;

depositing an encapsulant over the substrate and the bond wires;

forming an opening in the encapsulant extending to the bond line; and

a conductive material is disposed in the opening.

2. The method of claim 1, further comprising:

disposing electrical components over a substrate; and

a shielding layer is formed over the encapsulant and in contact with the conductive material.

3. The method of claim 1, further comprising providing a plurality of bond wires arranged in a pattern across the substrate.

4. The method of claim 1, wherein the opening comprises a trench extending across a plurality of bond wires disposed on the substrate.

5. The method of claim 1, further comprising forming a plurality of openings that individually expose each of a plurality of bond wires.

6. A semiconductor device, comprising:

a substrate;

a bonding wire disposed on the substrate;

electrical components disposed over the substrate;

an encapsulant deposited over the substrate, the electrical component, and the bond wires, wherein the openings in the encapsulant extend to the bond wires; and

and a conductive material deposited in the opening.

7. The semiconductor device of claim 6, further comprising a shield layer formed over the encapsulant and in contact with the conductive material.

8. The semiconductor device of claim 6, further comprising a plurality of bond wires arranged in a pattern across the substrate.

9. The semiconductor device of claim 6, wherein the opening comprises a trench extending across a plurality of bond wires disposed on the substrate.

10. The semiconductor device of claim 6, further comprising a plurality of openings individually exposing each of a plurality of bond wires.

11. A semiconductor device, comprising:

a substrate;

a bonding wire disposed on the substrate;

an encapsulant deposited over the substrate and the bond wires, wherein openings in the encapsulant extend to the bond wires; and

and a conductive material disposed in the opening.

12. The semiconductor device of claim 11, further comprising:

electrical components disposed over the substrate; and

a shield layer formed over the encapsulant and in contact with the conductive material.

13. The semiconductor device of claim 11, further comprising a plurality of bond wires arranged in a pattern across the substrate.

14. The semiconductor device of claim 11, wherein the opening comprises a trench extending across a plurality of bond wires disposed on the substrate.

15. The semiconductor device of claim 11, further comprising a plurality of openings individually exposing each of a plurality of bond wires.