CN113138938A - Memory protection device and method and electronic equipment - Google Patents
Memory protection device and method and electronic equipment Download PDFInfo
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- CN113138938A CN113138938A CN202010062769.1A CN202010062769A CN113138938A CN 113138938 A CN113138938 A CN 113138938A CN 202010062769 A CN202010062769 A CN 202010062769A CN 113138938 A CN113138938 A CN 113138938A
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- memory
- reset
- power supply
- controller
- protection device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
Abstract
The invention provides a memory protection device and method and electronic equipment, wherein the memory protection device comprises: the controller is used for outputting an erasing and writing command to the memory, and the erasing and writing command is used for indicating the memory to execute the operation of erasing and writing data; the reset detection module is connected with the power supply module and a reset pin of the controller and is used for detecting whether the power supply module is abnormally powered down or not and generating a reset signal when the power supply module is abnormally powered down so as to control the controller to be in a reset state; when the controller is in a reset state, the erasing instruction is stopped from being sent to the memory, and the erasing operation on the memory can be stopped so as to ensure that the data of the memory is not lost or abnormally changed.
Description
Technical Field
The present application relates to the field of radio frequency technologies, and in particular, to a memory protection device and method, and an electronic device.
Background
While an intelligent device (or simply a device) is in operation, a controller (e.g., a CPU) in the device may erase/write memory (e.g., FLASH, etc.) at any time. In some working scenes, the power module of the equipment may have no early warning power failure (referred to as abnormal power failure for short), any power failure lasts for a period of time, and the power supply is unstable due to continuous reduction in the period of time; therefore, if an abnormal power failure occurs during the operation of the controller flash memory, the data in any area of the memory may be lost or abnormally changed due to the poor stability of the power module, so that the program or data may be disordered, and the device may not work normally.
Disclosure of Invention
The invention provides a memory protection device and method and electronic equipment, which can stop erasing operation of a memory when a power module is abnormally powered down so as to ensure that data of the memory is not lost or abnormally changed.
The invention provides a memory protection device, which is used for including data of a memory, and comprises:
a power supply module for supplying power to the power supply module,
the controller is at least provided with a reset pin and is used for outputting an erasing command to the memory, and the erasing command is used for indicating the memory to execute data erasing operation;
the reset detection module is connected with the power supply module and a reset pin of the controller and is used for detecting whether the power supply module is abnormally powered down or not and generating a reset signal when the power supply module is abnormally powered down so as to control the controller to be in a reset state; and when the controller is in a reset state, stopping sending the erasing instruction to the memory.
In one embodiment, the reset detection module comprises:
the comparison circuit is connected with the power supply module and used for detecting the output voltage of the power supply module, comparing the output voltage with a reference voltage and outputting a comparison result of abnormal power failure when the difference value of the output voltage and the reference voltage exceeds a preset standard;
and the reset circuit is connected with the comparison circuit and a reset pin of the controller and used for receiving the comparison result of the abnormal power failure and generating the reset signal according to the comparison result.
In one embodiment, the comparison circuit comprises a first resistor, a second resistor, a voltage generation unit and a comparison unit, wherein the power module is grounded through the first resistor and the second resistor in sequence; wherein the content of the first and second substances,
the first input end of the comparison unit is respectively connected with the first resistor and the second resistor, the second end of the comparison unit is grounded through the voltage generation unit, the output end of the comparison unit is connected with the reset circuit,
the voltage generation unit is used for generating the reference voltage.
In one embodiment, the reset signal is a pulse signal or a level signal.
In one embodiment, the apparatus further includes a capacitor, and the capacitor is respectively connected to the power supply module and the conversion module, or the capacitor is connected to the memory, wherein the capacitor is used for supplying power to the memory.
In one embodiment, the capacitance value of the capacitor is greater than a preset value, and the preset value meets the condition of providing working voltage for the memory within a preset time period.
In one embodiment, the apparatus further comprises:
and the conversion module is respectively connected with the power supply module and the controller and is used for converting the first voltage output by the power supply module into a second voltage suitable for supplying power to the controller.
The invention also provides a memory protection method, which is applied to a memory protection device, wherein the data protection device comprises: the device comprises a power supply module used for supplying power to the memory and a reset detection module connected with the power supply module, wherein the method comprises the following steps:
detecting whether the power supply module is abnormally powered down or not based on the reset detection module;
when the power supply module is abnormally powered off, the reset detection module generates a reset signal;
and receiving the reset signal, and stopping sending the erasing instruction to the memory according to the reset signal so as to stop erasing operation on the memory.
In one embodiment, the memory protection device further comprises a capacitor, and the method further comprises:
and when the power supply module is abnormally powered off, the capacitor is controlled to supply power to the memory.
The present invention also provides an electronic device comprising: the memory protection device comprises a memory and the memory protection device, wherein a controller in the memory protection device is connected with the memory.
The memory protection device and method and the electronic equipment provided by the invention can detect the abnormal power failure of the power supply module, can generate the reset signal to immediately reset the controller when the power supply module is abnormally powered down, and the controller cannot erase and write the memory in a reset state, namely, the controller can stop erasing and writing operations on the memory so as to ensure that data of the memory is not lost or abnormally changed.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram illustrating an exemplary internal structure of a memory protection device;
FIG. 2 is a schematic diagram of the internal structure of another embodiment of a memory protection device;
FIG. 3 is a schematic diagram of the internal structure of a memory protection device in another embodiment;
FIG. 4 is a diagram illustrating operating voltages and operating times of a memory according to an embodiment;
FIG. 5 is a diagram illustrating the operating voltage and operating time of the memory after the capacitor is disposed in one embodiment;
FIG. 6 is a flow diagram of a method for memory protection in one embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. In the description of the present application, "a number" means at least one, such as one, two, etc., unless specifically limited otherwise.
As shown in fig. 1, the present invention provides a memory protection device 10 for protecting a memory 20. The memory 20 may be a FLASH memory, also known as FLASH memory, in the form of an Electrically Erasable Programmable Read Only Memory (EEPROM) that allows multiple erases or writes during operation, with EEPROM and high speed RAM being the two most commonly used and most rapidly developing memory technologies at the present time. FLASH combines the advantages of ROM and RAM, not only has the performance of electrically erasable programmable read-only memory (EEPROM), but also can not lose data when power is cut off, and can read data quickly (the advantage of NVRAM).
In the present invention, the memory may also be other types of memories, and the type of the memory is not further limited. In the present invention, a FLASH memory is used as an example.
The apparatus includes a power module 110, a reset detection module 120, and a controller 130. The controller 130 may be a central processing unit CPU, and the controller 130 may erase and write the FLASH memory. Specifically, the controller 130 can erase the FLASH memory in two stages. The first phase may be understood as an erasure command transmission phase, and the second phase may be understood as an erasure command execution phase. When the controller 130 completes the first and second operations on the memory 20, it indicates that the controller 130 completes erasing and writing the FLASH memory.
For example, in the first stage, the controller 130 may transmit an erase command to the FLASH memory through a signal line; if the power failure occurs abnormally at this stage, the power failure process may cause power supply fluctuation of the controller 130 and the FLASH memory, which may cause erasing errors of the controller 130 and the FLASH memory; in the second stage, the FLASH memory is erased and written, and the erasing and writing errors of the FLASH memory can be caused due to power fluctuation in the power failure process.
The power module 110 is connected to the controller 130, the reset detection module 120, and the memory 20, respectively, and is configured to supply power to each module or device. A controller 130 at least configured with a reset pin rst, wherein the controller 130 is configured to output an erasure command to the memory 20, and the erasure command is used to instruct the memory 20 to perform an operation of data erasure; the Reset detection module 120 is connected to the power module 110 and a Reset pin rst of the controller 130, and is configured to detect whether the power module 110 is abnormally powered down, and generate a Reset signal Reset when the power module is abnormally powered down, so as to control the controller 130 to be in a Reset state; when the controller 130 is in the reset state, the erasing instruction is stopped being sent to the memory 20, so that current or voltage fluctuation of the memory 20 or the controller 130 caused by power failure can be prevented, and further, erroneous erasing of the memory 20 by the controller 130 can be avoided.
As shown in fig. 2 and 3, in one embodiment, the reset detection module 120 includes: a comparison circuit 121 and a reset circuit 122. The comparison circuit 121 is connected to the power module 110, and configured to detect an output voltage of the power module 110, compare the output voltage with a reference voltage, and output a comparison result of abnormal power failure when a difference between the output voltage and the reference voltage exceeds a preset standard.
Specifically, the comparison circuit 121 includes a first resistor R1, a second resistor R2, a voltage generation unit M, and a comparison unit 1211, wherein the power module 110 is grounded via the first resistor R1 and the second resistor R2 in sequence; wherein, a first input terminal of the comparing unit 1211 is connected to the first resistor R1 and the second resistor R2, respectively, a second terminal of the comparing unit 1211 is grounded via the voltage generating unit M, an output terminal of the comparing unit 1211 is connected to the reset circuit 122,
the first resistor R1 and the second resistor R2 may be understood as resistors for voltage, and may be configured to collect a voltage signal provided by the power module 110 and input the collected voltage signal to the first terminal of the value comparing unit 1211.
The voltage generating unit M is configured to generate the reference voltage, and input the generated reference voltage to the second end of the comparing unit.
The comparing unit 1211 receives the voltage signal output by the power module 110 and the reference voltage generated by the voltage generating unit M, which are collected by the sampling resistor, compares the voltage signal with the reference voltage, and if the voltage signal is greater than the reference voltage, the comparing unit 1211 outputs a comparison result of abnormal power failure. Specifically, the comparing unit 1211 may be a voltage comparator, a comparing circuit 121 formed by an operational amplifier, or the like. In the present invention, the specific form of the comparison unit 1211 is not further limited.
In one embodiment, the Reset circuit 122 may be respectively connected to the comparison circuit 121 and the Reset pin rst of the controller 130, and configured to receive the comparison result of the abnormal power down and generate the Reset signal Reset according to the comparison result. The reset circuit 122 is connected to the comparison circuit 121, and the reset circuit 122 may receive a comparison result of the abnormal power failure output by the comparison circuit 121. When the Reset circuit 122 receives the comparison result of the abnormal power down, the Reset circuit 122 may generate a Reset signal Reset.
Specifically, the Reset signal Reset is a pulse signal or a level signal.
The Reset signal Reset generated by the Reset circuit 122 may be output to the Reset pin rst of the controller 130, so that the controller 130 may be Reset. When the controller 130 is in the reset state, the PC pointers in the controller 130 cannot be accumulated, and thus cannot fetch and execute program instructions. That is, the controller 130 cannot continue to transmit the erasing command to the FLASH memory, so that the problem that the data of the FLASH memory is erased by mistake can be avoided, and the data protection of the FLASH memory is realized when abnormal power failure occurs.
In one embodiment, the device further comprises a capacitor C, as shown in fig. 3. The capacitor C may directly or indirectly supply power to the FLASH memory, and when the power module 110 is abnormally powered down, the capacitor C may supply power to the FLASH memory and the controller 130 to maintain the transient stability of the FLASH memory.
In one embodiment, the capacitor C may be connected to the power module 110 and the converting module, respectively. Optionally, the capacitor C may be connected to the memory 20.
In one embodiment, the capacitance value of the capacitor C is greater than a preset value, and the preset value meets the condition of providing the working voltage for the memory 20 within a preset time period. For example, the voltage signal output by the power module 110 is 5V, the reference voltage is 4.1V, and the operating voltage of the memory 20 is 1.8V. As shown IN fig. 4, wherein VDD IN is the input voltage of the power module 110, Vth is the reference voltage, VIO is the operating voltage of the FLASH memory, and RESET is the RESET signal RESET of the controller 130; the time Ta is the time when the abnormal power down occurs, and the time Tb is the time when the power supply of the LASH memory 20 starts to fluctuate due to the abnormal power down. Capacitor C may maintain stable operating voltage VIO of last memory 20 up to Tb time at the time Ta occurs during abnormal power down.
Specifically, the capacitance value of the capacitor C can still maintain the difference between the Tb time and the Ta time when the memory 20FLASH is abnormally powered down, and the difference is not less than the time (e.g. 3ms) for erasing one block by the memory 20 FLASH. Referring to fig. 5, after the capacitor C is provided in the protection device, the capacitor C can still provide a voltage signal of 1.8V to the FLASH memory when the power is abnormally turned off, and can maintain 3 ms. In the figure, CS may indicate a chip select signal for the controller 130 to access the FLASH memory, and reflect whether the controller 130 is erasing the FLASH memory and whether the operating voltage of the FLASH memory is changed.
In the invention, after the protection device is provided with the capacitor C, the capacitor C can maintain the working voltage of the FLASH memory to be transient and stable, thereby realizing the protection of the FLASH memory data; because the FLASH memory has a short erasing time (the FLASH memory uses a block as a minimum erasing unit, and the erasing time of 1 block is usually less than 3ms), the time for keeping the working voltage stable is longer than that, and the capacitance value of the capacitor C can be realized without being too large.
In one embodiment, the apparatus further comprises: a conversion module 140, respectively connected to the power module 110 and the controller 130, for converting the first voltage output by the power module 110 into a second voltage suitable for supplying power to the controller 130.
The invention can also provide a memory 20 protection method, which is applied to a memory 20 protection device 10, wherein the data protection device comprises: the memory comprises a power supply module 110 for supplying power to the memory 20, and a reset detection module 120 connected with the power supply module 110.
As shown in FIG. 6, in one embodiment, the method includes steps 602-606.
In one embodiment, the reset detection module 120 includes: a comparison circuit 121 and a reset circuit 122. The comparison circuit 121 is connected to the power module 110, and configured to detect an output voltage of the power module 110, compare the output voltage with a reference voltage, and output a comparison result of abnormal power failure when a difference between the output voltage and the reference voltage exceeds a preset standard.
The Reset circuit 122 may be respectively connected to the comparison circuit 121 and the Reset pin rst of the controller 130, and configured to receive the comparison result of the abnormal power failure and generate the Reset signal Reset according to the comparison result. The reset circuit 122 is connected to the comparison circuit 121, and the reset circuit 122 may receive a comparison result of the abnormal power failure output by the comparison circuit 121. When the Reset circuit 122 receives the comparison result of the abnormal power down, the Reset circuit 122 may generate a Reset signal Reset. Specifically, the Reset signal Reset is a pulse signal or a level signal.
The Reset signal Reset generated by the Reset circuit 122 may be output to the Reset pin rst of the controller 130, so that the controller 130 may be Reset. When the controller 130 is in the reset state, the PC pointers in the controller 130 cannot be accumulated, and thus cannot fetch and execute program instructions. That is, the controller 130 cannot continue to transmit the erasing command to the FLASH memory to stop the erasing operation on the memory 20, so that the problem that the data of the FLASH memory is erased incorrectly can be avoided, and the data protection of the FLASH memory is realized when abnormal power failure occurs.
In one embodiment, the memory 20 protection device 10 further includes a capacitor C, and the method further includes:
when the power module 110 is abnormally powered down, the capacitor C is controlled to supply power to the memory 20. That is, when the power supply module 110 is abnormally powered down, the capacitor C can maintain the working voltage of the FLASH memory to be temporarily stable, so as to protect the data of the FLASH memory; because the FLASH memory has a short erasing time (the FLASH memory uses a block as a minimum erasing unit, and the erasing time of 1 block is usually less than 3ms), the time for keeping the working voltage stable is longer than that, and the capacitance value of the capacitor C can be realized without being too large.
The embodiment of the application also provides the electronic equipment. The electronic device may be any terminal device including a mobile phone, a tablet computer, a PDA (Personal Digital Assistant), a Point of Sales (POS), a vehicle-mounted computer, a wearable device, and the like.
In one embodiment, the electronic device includes a memory 20, and the memory 20 protection device 10 is described above, wherein the controller 130 in the memory 20 protection device 10 is connected to the memory 20. When the protection device is provided in the electronic device, the memory 20 in the electronic device may be protected, for example, a Reset signal Reset is generated when the power module 110 in the electronic device is abnormally powered down, so as to control the controller 130 to be in a Reset state; when the controller 130 is in the reset state, the erasing instruction is stopped being sent to the memory 20, so that current or voltage fluctuation of the memory 20 or the controller 130 caused by power failure can be prevented, and further, erroneous erasing of the memory 20 by the controller 130 can be avoided.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A memory protection device, the device configured to protect memory, the device comprising:
a power supply module for supplying power to the power supply module,
the controller is at least provided with a reset pin and is used for outputting an erasing command to the memory, and the erasing command is used for indicating the memory to execute data erasing operation;
the reset detection module is connected with the power supply module and a reset pin of the controller and is used for detecting whether the power supply module is abnormally powered down or not and generating a reset signal when the power supply module is abnormally powered down so as to control the controller to be in a reset state; and when the controller is in a reset state, stopping sending the erasing instruction to the memory.
2. The memory protection device of claim 1, wherein the reset detection module comprises:
the comparison circuit is connected with the power supply module and used for detecting the output voltage of the power supply module, comparing the output voltage with a reference voltage and outputting a comparison result of abnormal power failure when the difference value of the output voltage and the reference voltage exceeds a preset standard;
and the reset circuit is connected with the comparison circuit and a reset pin of the controller and used for receiving the comparison result of the abnormal power failure and generating the reset signal according to the comparison result.
3. The memory protection device according to claim 2, wherein the comparison circuit comprises a first resistor, a second resistor, a voltage generation unit and a comparison unit, wherein the power module is grounded via the first resistor and the second resistor in sequence; wherein the content of the first and second substances,
the first input end of the comparison unit is respectively connected with the first resistor and the second resistor, the second end of the comparison unit is grounded through the voltage generation unit, the output end of the comparison unit is connected with the reset circuit,
the voltage generation unit is used for generating the reference voltage.
4. The memory protection device of claim 2, wherein the reset signal is a pulse signal or a level signal.
5. The memory protection device according to claims 1-4, further comprising a capacitor connected to the power module, the switching module, or the memory, respectively, wherein the capacitor is configured to supply power to the memory.
6. The memory protection device of claim 5, wherein the capacitance of the capacitor is greater than a predetermined value, and the predetermined value is adapted to provide an operating voltage to the memory for a predetermined period of time.
7. The memory protection device of claim 1, further comprising:
and the conversion module is respectively connected with the power supply module and the controller and is used for converting the first voltage output by the power supply module into a second voltage suitable for supplying power to the controller.
8. A memory protection method applied to a memory protection device, the data protection device comprising: the device comprises a power supply module used for supplying power to the memory and a reset detection module connected with the power supply module, wherein the method comprises the following steps:
detecting whether the power supply module is abnormally powered down or not based on the reset detection module;
when the power supply module is abnormally powered off, the reset detection module generates a reset signal;
and receiving the reset signal, and stopping sending the erasing instruction to the memory according to the reset signal so as to stop erasing operation on the memory.
9. The method of claim 8, wherein the memory protection device further comprises a capacitor, the method further comprising:
and when the power supply module is abnormally powered off, the capacitor is controlled to supply power to the memory.
10. An electronic device, comprising:
a memory, and
the memory protection device of any one of claims 1-7, wherein a controller in the memory protection device is coupled to the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010062769.1A CN113138938A (en) | 2020-01-19 | 2020-01-19 | Memory protection device and method and electronic equipment |
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| CN202010062769.1A CN113138938A (en) | 2020-01-19 | 2020-01-19 | Memory protection device and method and electronic equipment |
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