CN113138475A - Anti-static structure and method for array substrate - Google Patents

Anti-static structure and method for array substrate Download PDF

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Publication number
CN113138475A
CN113138475A CN202110360189.5A CN202110360189A CN113138475A CN 113138475 A CN113138475 A CN 113138475A CN 202110360189 A CN202110360189 A CN 202110360189A CN 113138475 A CN113138475 A CN 113138475A
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data line
wire
array substrate
wire section
discontinuous
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沈志英
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133351Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306Details
    • G02F1/1309Repairing; Testing
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05FSTATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00Carrying-off electrostatic charges

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)

Abstract

The application provides an antistatic structure and a method for an array substrate, wherein the antistatic structure comprises: at least one metal wire arranged in an array substrate; at least one data line connecting the metal wire to an electronic device in the array substrate; the data wire is cut into a first wire section and a second wire section which are arranged oppositely; a discontinuous area is formed between the first conducting wire section and the second conducting wire section. When the coupling energy generated by the data line is inversely proportional to the square of the spacing between the discontinuous regions, the spacing between the discontinuous regions is maximized, thereby completely preventing the electrostatic explosion of the chip on film and the driving IC.

Description

Anti-static structure and method for array substrate
Technical Field
The present disclosure relates to display technologies, and particularly, to an anti-static structure and method for an array substrate.
Background
Liquid Crystal Display (LCD) devices have many advantages such as thin body, power saving, and no radiation, and are widely used. Most of the lcd devices in the market are backlight lcd devices, which include a housing, an lcd panel disposed in the housing, and a backlight module (backlight module) disposed in the housing and opposite to the lcd panel. The liquid crystal display panel has the working principle that liquid crystal molecules are placed in two parallel glass substrates, and a driving voltage is applied to the two glass substrates to control the rotation of the liquid crystal molecules, so that light rays of the backlight module are refracted out to generate a picture.
Electrostatic discharge (ESD) has been a pending problem in the semiconductor manufacturing industry, and the ESD causes a reduction in product yield, an increase in cost, and a reduction in throughput. In the manufacturing process of the liquid crystal display device, static electricity also affects the quality of the liquid crystal display device, especially the manufacturing process of the liquid crystal display panel.
The generation of static electricity is mainly divided into three major factors:
one is particles (particles), any of which may cause device damage or even product rejection, and therefore, controlling the particles is an important task in the semiconductor manufacturing process.
Second, engineering conditions and raw materials, in the process of the liquid crystal display panel, static electricity is generated under the process conditions of a deposition (deposition) process, a photo (photo) process, an etching (etch) process, a strip (strip) process, a clean (clean) process, and the like, and static electricity is also generated by the raw materials used in the processes due to material defects.
Thirdly, the design factor, the product design directly influences the static condition.
In order to improve the product quality and reduce the production cost, the production process of the liquid crystal display panel can carry out electrostatic protection work. This electrostatic protection work includes two broad categories: the method comprises the steps that firstly, internal devices of the liquid crystal display panel are protected, and an anti-static ring (ESD ring) is designed at the beginning and the end of a circuit (a Gate line and a Data line) of the liquid crystal display panel; the protection of the peripheral circuit of the liquid crystal display panel is mainly used for protecting the damage of static electricity to the peripheral circuit of the panel in the array process and the back-end process.
In the TFT _ LCD panel display process, in order to predict the product risk, it is necessary to perform image quality inspection before the Cell segment process. Generally, the method for detecting image quality includes: in the olb (outer lead bonding) area, the shorting bar is designed to overlap the data line in the plane, so that the shorting bar (shorting bar) is shorted with the data line (data line) in the plane. After the image quality detection, in order not to affect the performance of the product, a person skilled in the art may use a laser cutting (lasercut) process to disconnect the shorting bar and the in-plane data line from each other. The area of the wiring at the overlapping position of the short-circuit bar and the data line in the plane is large, so that more charges are easily accumulated and cannot be led out. However, in the process of disconnecting the shorting bar from the in-plane data line, the discontinuity area between the shorting bar and the in-plane data line is narrow, and therefore the following two cases occur: 1. the shorting bar and the data line in the plane cannot be completely disconnected; 2. debris remains in the laser-irradiated area. Both of the above two situations will lead external static electricity to the interior of the driving IC (cof IC) disposed on the chip on film through the shorting bar in the discontinuity region, thereby causing the chip on film and the driving IC to be damaged by static electricity, and affecting the product quality. The OLB area refers to a bonding area between a Chip On Film (COF) and a driver IC.
Disclosure of Invention
The present invention is directed to an anti-static structure and method for an array substrate, so as to solve the technical problem that a Chip On Film (COF) and a driving IC are damaged by static electricity due to external static electricity introduced into the driving IC.
In order to achieve the above object, the present invention provides an anti-static structure for an array substrate, including: at least one metal wire arranged in an array substrate; at least one data line connecting the metal wire to an electronic device in the array substrate; the data wire is cut into a first wire section and a second wire section which are arranged oppositely; a discontinuous area is formed between the first conducting wire section and the second conducting wire section.
Further, the discontinuous area is provided with an air medium or an insulating glue layer.
Further, the interval of the discontinuous areas is 38-42 μm.
Furthermore, an insulating medium exists between the metal trace and the data line.
Further, the metal trace is connected to the data line through a via hole; the metal routing lines are perpendicular to the data lines.
Further, when the data line is cut, the distance between the coupling energy generated by the data line and the discontinuous region is obtained.
Further, according to Ampere force law, when the coupling energy generated by the data line is inversely proportional to the square of the pitch of the discontinuous regions, the pitch of the discontinuous regions is maximized.
Further, the anti-static structure further comprises: the slotted hole is arranged in the discontinuous area; the slot is used for loading the scraps of the data line when the data line is cut.
In order to achieve the above object, the present invention further provides an anti-static method for an array substrate, including the steps of: arranging at least one metal wire and a data wire in an array substrate; carrying out lighting detection on the array substrate; removing one section of the data wire to enable the data wire to be cut into a first wire section and a second wire section which are arranged oppositely; a discontinuous area is formed between the first conducting wire section and the second conducting wire section.
Further, a section of the data line is removed in a laser cutting mode, so that the data line is cut into a first wire section and a second wire section which are arranged oppositely; a discontinuous area is formed between the first conducting wire section and the second conducting wire section.
The invention has the technical effects that the anti-static structure and the method for the array substrate are provided, the data wire is cut in a laser mode, so that the data wire is cut into a first wire section and a second wire section which are oppositely arranged, and a discontinuous area is formed between the first wire section and the second wire section. When the coupling energy generated by the data line is inversely proportional to the square of the spacing between the discontinuous regions, the spacing between the discontinuous regions is maximized, thereby completely preventing the electrostatic explosion of the chip on film and the driving IC.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an anti-static structure before the data line is cut according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an anti-static structure after the data line is cut according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of an analysis of ampere's law provided by an embodiment of the present application.
The components of the drawings are identified as follows:
100. an anti-static structure; 101. Metal routing;
102. a data line; 103. An insulating glue layer;
1021. a first wire segment; 1022. A second wire segment;
10. a discontinuity region; 20. A slot;
30. a via hole;
201. a display area; 202. A black matrix region;
203. a binding region; 204. A test zone;
205. and an antistatic region.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Fig. 1 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present disclosure; fig. 2 is a schematic structural diagram of an anti-static structure before the data line is cut according to an embodiment of the present disclosure; fig. 3 is a schematic structural diagram of an anti-static structure after the data line is cut according to the embodiment of the present application.
As shown in fig. 1-3, the present embodiment provides a liquid crystal display panel, which includes a display area 201, a black matrix area 202, a bonding area 203, a test area 204, and an anti-static area 205. The black matrix area 202 is arranged on one side of the display area 201, the two binding areas 203 are arranged on one side of the black matrix area 202 far away from the display area 201, the test area 204 is arranged between the two binding areas 203, and the anti-static area 205 is arranged on the test area 204 and one side of the two binding areas 203 far away from the display area 201. The display area 201 includes an array substrate, the bonding area 203 is provided with a chip on film and a driver IC disposed on the chip on film, and the anti-static area 205 is provided with an anti-static structure 100 for the array substrate.
In this embodiment, the anti-static structure 100 includes a metal trace 101 and a data line 102.
Specifically, at least one metal trace 101 is disposed in an array substrate; at least one data line 102 connects the metal trace 101 to an electronic device in the array substrate. An insulating medium exists between the metal trace 101 and the data line 102, the metal trace 101 is connected to the data line 102 through a via 30, and the metal trace 101 and the data line 102 are perpendicular to each other.
The anti-static structure 100 is applied to a box test circuit, so as to detect defects of a panel in three processes of an array substrate (array), a color film substrate (color filter, CF for short) and a box (cell) through a cell test, and take out the defective products. At present, a commonly used method for box test (cell test) is to provide metal traces 101, i.e., Shorting bars (Shorting bars), in a peripheral region of a display panel, connect all data lines 102 in a display region 201 of the display panel with the metal traces 101, and then perform R/G/B/W image quality test through the metal traces 101. Once the image quality detection test is completed, the area of the display panel where the data line 102 is disposed is cut off by using a laser cutting device, so that the next driving circuit module assembly is performed. The data line 102 is cut into a first conducting line segment 1021 and a second conducting line segment 1022 which are oppositely arranged; a discontinuous region 10 is formed between the first lead segment 1021 and the second lead segment 1022.
In this embodiment, when the data line 102 is cut, the coupling energy generated by the data line 102 and the distance between the discontinuity 10 are obtained, so as to effectively discharge external static electricity and prevent the flip chip and the driving IC from being damaged by explosion.
As shown in fig. 4, fig. 4 is an analysis diagram of ampere's law provided by the embodiment of the present application.
According to the Bioho Shaval law, wire l1Magnetic field of in minute line element dl2The positions are:
Figure BDA0003005234930000051
acting on the position dl of the minor line element according to the Lorentz's law2The lorentz force of (a) follows the following equation:
dF=dq(E+v×B)。
here, the electric field is equal to zero, and, therefore,
expressed as an integral:
Figure BDA0003005234930000052
substituting the formula of the magnetic field to obtain
Figure BDA0003005234930000061
Where B is the magnetic induction, I is the current intensity, r is the distance, l is the length of the wire perpendicular to the magnetic induction, v is the velocity, d, q are the small charges, and E is the electric field.
Therefore, as can be seen from fig. 1 to 3, in order to effectively improve the electrostatic discharge effect of the discontinuous regions 10, according to the ampere force law, when the coupling energy generated by the data lines 102 is inversely proportional to the square of the pitch of the discontinuous regions 10, the pitch of the discontinuous regions 10 is maximized. In the present embodiment, the interval of the discontinuous regions 10 is 38 μm to 42 μm, preferably 38.5 μm, 39 μm, 40 μm, 40.5 μm, 41 μm.
In this embodiment, the anti-static structure 100 further includes: and the slotted hole 20 is arranged in the discontinuous area 10. When the data line 102 is cut, the slot 20 is used for loading the debris of the data line 102, preventing the debris from leading external static electricity into the driving IC arranged on the chip on film through the metal wire of the discontinuity 10, so as to prevent the chip on film and the driving IC from being damaged by the static electricity, and improve the product quality.
In this embodiment, an air dielectric or an insulating glue layer 103 may be disposed in the discontinuous region 10. When the discontinuous area 10 is provided with the insulating adhesive layer 103, the insulating adhesive layer 103 is attached to the surface of the discontinuous area 10 and completely fills the slot 20, so that the insulating effect of the discontinuous area 10 can be further improved, and the situation that the line of the discontinuous area 10 is exposed to cause electrostatic explosion to damage the chip on film and the driving IC is prevented. Wherein, the insulating glue layer 103 includes, but is not limited to, tuffy glue.
The embodiment also provides an antistatic method for the array substrate, which includes the following steps S1) -S3).
S1) disposing at least one metal trace and data line on an array substrate.
S2) lighting detection is performed on the array substrate.
S3) removing a segment of the data wire, so that the data wire is cut into a first wire segment and a second wire segment which are oppositely arranged; a discontinuous area is formed between the first conducting wire section and the second conducting wire section.
Specifically, as shown in fig. 2, a segment of the data line is removed by laser cutting, so that the data line 102 is cut into a first conducting line segment 1021 and a second conducting line segment 1022 which are oppositely arranged; a discontinuous region 10 is formed between the first lead segment 1021 and the second lead segment 1022.
In this embodiment, when the data line 102 is cut, the coupling energy generated by the data line 102 and the distance between the discontinuity 10 are obtained, so as to effectively discharge external static electricity and prevent the flip chip and the driving IC from being damaged by explosion. When the coupling energy generated by the data line 102 is inversely proportional to the square of the pitch of the discontinuous regions 10, the pitch of the discontinuous regions 10 is maximized. In the present embodiment, the interval of the discontinuous regions 10 is 38 μm to 42 μm, preferably 38.5 μm, 39 μm, 40 μm, 40.5 μm, 41 μm.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The invention has the technical effects that the anti-static structure and the method for the array substrate are provided, the data wire is cut in a laser mode, so that the data wire is cut into a first wire section and a second wire section which are oppositely arranged, and a discontinuous area is formed between the first wire section and the second wire section. When the coupling energy generated by the data line is inversely proportional to the square of the spacing between the discontinuous regions, the spacing between the discontinuous regions is maximized, thereby completely preventing the electrostatic explosion of the chip on film and the driving IC.
The anti-static structure and the method for the array substrate provided by the embodiment of the present application are introduced in detail, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. An anti-static structure for an array substrate, comprising:
at least one metal wire arranged in an array substrate; and
at least one data line connecting the metal wire to an electronic device in the array substrate;
the data wire is cut into a first wire section and a second wire section which are arranged oppositely; a discontinuous area is formed between the first conducting wire section and the second conducting wire section.
2. The antistatic structure according to claim 1,
and the discontinuous area is provided with an air medium or an insulating glue layer.
3. The antistatic structure according to claim 1,
the interval of the discontinuous areas is 38-42 μm.
4. The antistatic structure according to claim 1,
and an insulating medium is arranged between the metal wire and the data wire.
5. The antistatic structure according to claim 4,
the metal routing is connected to the data line through a via hole;
the metal routing lines are perpendicular to the data lines.
6. The antistatic structure according to claim 1,
and acquiring the distance between the coupling energy generated by the data line and the discontinuous region when the data line is cut.
7. The antistatic structure according to claim 6,
according to Ampere force law, when the coupling energy generated by the data line is inversely proportional to the square of the interval of the discontinuous regions, the interval of the discontinuous regions is maximized.
8. The antistatic structure of claim 1, further comprising:
the slotted hole is arranged in the discontinuous area;
the slot is used for loading the scraps of the data line when the data line is cut.
9. An antistatic method for an array substrate, comprising the steps of:
arranging at least one metal wire and a data wire in an array substrate;
carrying out lighting detection on the array substrate;
removing one section of the data wire to enable the data wire to be cut into a first wire section and a second wire section which are arranged oppositely; a discontinuous area is formed between the first conducting wire section and the second conducting wire section.
10. The antistatic method according to claim 9,
removing a section of the data line in a laser cutting mode, so that the data line is cut into a first conducting wire section and a second conducting wire section which are arranged oppositely; a discontinuous area is formed between the first conducting wire section and the second conducting wire section.
CN202110360189.5A 2021-04-02 2021-04-02 Anti-static structure and method for array substrate Pending CN113138475A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000098425A (en) * 1998-09-22 2000-04-07 Hitachi Ltd Active matrix substrate and liquid crystal display device using this substrate
KR20040040786A (en) * 2002-11-08 2004-05-13 엘지.필립스 엘시디 주식회사 Array substrate and the fabrication method for lcd
CN1576985A (en) * 2003-07-23 2005-02-09 株式会社日立显示器 Display device
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Application publication date: 20210720