CN113133183A

CN113133183A - Flip-chip bonding structure and circuit substrate thereof

Info

Publication number: CN113133183A
Application number: CN202011077836.3A
Authority: CN
Inventors: 马宇珍; 黄信豪; 周文复; 许国贤
Original assignee: Chipbond Technology Corp
Current assignee: Chipbond Technology Corp
Priority date: 2019-12-31
Filing date: 2020-10-10
Publication date: 2021-07-16

Abstract

The invention discloses a flip chip bonding structure and a circuit substrate thereof. The flip chip bonding structure is provided with a circuit substrate, the circuit substrate is provided with a carrier plate, a plurality of inner pins, a T-shaped circuit and a virtual metal pattern, the inner pins, the T-shaped circuit and the virtual metal pattern are positioned in an inner bonding area of the carrier plate, the T-shaped circuit is provided with a main line segment, a connecting segment and a branch line segment, the connecting segment is connected with the main line segment and the branch line segment, the main line segment extends along the transverse axis direction, the branch line segment extends along the longitudinal axis direction, and the virtual metal pattern is positioned between the connecting segment and the inner pins.

Description

Flip-chip bonding structure and circuit substrate thereof

Technical Field

The invention relates to a flip chip bonding structure, wherein a chip is bonded on a circuit substrate with a T-shaped circuit and a dummy metal pattern.

Background

The line etching process etches the metal layer exposed by the patterned photoresist by using an etching solution, transfers the pattern to the metal layer to form a fine line pattern, wherein the etching solution flows among the patterned photoresist to uniformly etch the exposed metal layer, however, when the etching solution flows to the space surrounded by the three-sided photoresist, the fluidity of the etching solution is reduced and the etching solution is accumulated in the space surrounded by the three sides of the photoresist, and the etching solution stays for too long time, which may cause over-etching, so that the fine line is broken and fails.

Disclosure of Invention

The invention aims to provide a flip chip bonding structure and a circuit substrate thereof.A dummy metal pattern is arranged around a T-shaped circuit so as to prevent the T-shaped circuit from being broken due to over etching of an etching solution.

The invention discloses a circuit substrate, which comprises a carrier plate, a plurality of inner pins, at least one T-shaped circuit and at least one virtual metal pattern, wherein the carrier plate is provided with a surface, an inner bonding area is defined on the surface, the inner bonding area is provided with a first area and a second area, the first area is positioned outside the second area, the inner pins are positioned in the first area, the T-shaped circuit is positioned in the second area and is provided with a main line section, a connecting section and a branch line section, the main line section is connected with the connecting section and extends along the direction of a transverse axis, the branch line section is connected with the connecting section and extends towards the first area along the direction of a longitudinal axis, the branch line section is used for bonding a convex block, the virtual metal pattern is positioned between the connecting section and the inner pins, and the virtual metal pattern is not electrically connected with the inner pins and the T-shaped circuit.

Preferably, the main line segment has a first width along the longitudinal axis, and the connecting segment has a second width along the longitudinal axis, the second width being smaller than the first width.

Preferably, the branch line segment has a third width along the transverse axis, and a ratio of the second width to the third width is not less than 0.5.

Preferably, the branch line segment extends along the longitudinal axis toward one of the inner leads.

Preferably, the branch line segment extends along the longitudinal axis direction to between two adjacent inner pins.

Preferably, the branch line segment has a first end and a second end, the first end is connected to the connecting segment, the second end is used for connecting the bump, and the line width of the first end is greater than that of the second end.

Preferably, the branch line section has a first end and a second end, the first end is connected to the connecting section, the second end is used for connecting the bump, and the first end and the second end are perpendicular to each other.

Preferably, the device has two dummy metal patterns, and the dummy metal patterns are respectively located at two sides of the branch line segment.

The invention also discloses a flip chip bonding structure, which comprises the circuit substrate, a wafer and a solder layer, wherein the wafer is arranged in the inner bonding area and is provided with a plurality of first bumps and at least one second bump, and the solder layer is positioned between the circuit substrate and the wafer and is used for bonding the first bumps and the inner pins of the inner pins and bonding the second bumps and the branch sections.

Preferably, the second bump has a fourth width, and a ratio of the second width to the fourth width is smaller than 2.

Preferably, the connecting section has a first length along the transverse axis, the second protrusion has a second length, and a ratio of the first length to the second length is not less than 4.

Preferably, a linear distance exists between the connecting section and the second bump, and a ratio of the linear distance to the second width is not less than 3.

The dummy metal pattern is arranged between the connecting section and the inner pins, so that the dummy metal pattern is positioned in the space surrounded by the connecting section, the branch section and the inner pins, therefore, the etching solution can not be accumulated around the connecting section and the branch section, and the phenomenon that the connecting section and/or the branch section are broken due to the fact that the etching solution excessively etches the T-shaped circuit can be avoided.

Drawings

FIG. 1: according to an embodiment of the invention, a top view of a carrier is provided.

FIG. 2: according to an embodiment of the invention, a top view of a flip chip bonding structure.

FIG. 3: according to an embodiment of the present invention, a partial top view of the inner bonding area of the circuit substrate is provided.

FIG. 4: fig. 3 is a partially enlarged view.

FIG. 5: fig. 3 is a partially enlarged view.

FIG. 6: fig. 3 is a partially enlarged view.

FIG. 7: according to an embodiment of the present invention, a partial top view of the inner bonding area of the circuit substrate is provided.

FIG. 8: according to an embodiment of the present invention, a partial top view of the inner bonding area of the circuit substrate is provided.

FIG. 9: according to an embodiment of the invention, the flip chip bonding structure is a cross-sectional view.

[ description of main element symbols ]

100: circuit substrate 110: carrier board

111: surface 112: outer bonding area

113 inner bonding zone 113a first zone

113b second region 120 line layer

121, outer lead 122, inner lead

130: solder mask layer 140: T-shaped circuit

141 main line segment 142 connecting segment

143 branch line section 143a first end

143b the second end 150 the dummy metal pattern

200 wafer 210 first bump

220 second bump 300 solder layer

400 package colloid I flip chip bonding structure

L1 first length L2 second length

LD straight length W1 first width

W2 second width W3 third width

W4 fourth Width X transverse Direction

Y is the longitudinal axis direction

Detailed Description

Referring to fig. 1 to fig. 3, the present invention discloses a circuit substrate 100, the circuit substrate 100 has a carrier 110 and a circuit layer 120, the circuit layer 120 is disposed on the surface 111 of the carrier 110, the surface 111 defines an outer bonding region 112 and an inner bonding region 113, the circuit layer 120 has a plurality of outer leads 121 and a plurality of inner leads 122, the outer leads 121 are located in the outer bonding region 112, the inner leads 122 are located in the inner bonding region 113, the outer leads 121 and the inner leads 122 are respectively arranged in the outer bonding region 112 and the inner bonding region 113 along the horizontal axis direction X, the inner bonding pad 113 has a first region 113a and a second region 113b, the first region 113a is located outside the second region 113b, and in the embodiment, the inner bonding pad 113 has two first areas 113a, the second area 113b is located between the first areas 113a, and the inner leads 122 are located in the first areas 113 a.

Preferably, the carrier 110 may be made of Polyimide (PI), polyethylene terephthalate (PET), glass, ceramic, metal or other materials, and the material of the circuit layer 120 may be copper, nickel, gold or other metals or alloys.

Referring to fig. 2, preferably, the circuit substrate 100 further has a solder mask layer 130, the solder mask layer 130 covers the circuit layer 120 but does not cover the outer leads 121 and the inner leads 122, the solder mask layer 130 is used to protect the circuit layer 120, and the exposed outer leads 121 and the exposed inner leads 122 are respectively used to bond an electronic device and a chip (not shown).

Referring to fig. 3 and 4, the circuit substrate 100 further includes at least one T-shaped circuit 140 located in the second region 113b of the inner bonding region 113, the T-shaped circuit 140 is used for being grounded or connected to a power source without being electrically connected to the inner lead 122, the T-shaped circuit 140 includes a main line segment 141, a connecting segment 142 and a branch line segment 143, the main line segment 141 connects the connecting segment 142 and extends along the horizontal axis direction X, the branch line segment 143 connects the connecting segment 142 and extends along the vertical axis direction Y toward the first region 113a, the branch line segment 143 is used for being connected to a bump, in the embodiment, the main line segment 141 and the connecting segment 142 connected to each other are linear, and the connecting segment 142 and the branch line segment 143 connected to each other are perpendicular to each other, but the invention is not limited thereto, the main line segment 141 and the connecting segment 142 may be non-linear, and an included angle between the connecting segment 142 and the branch line segment 143 may be larger than, Less than or substantially equal to 90 degrees.

Preferably, the circuit substrate 100 has a plurality of T-shaped circuits 140, the main line segments 141 of the T-shaped circuits 140 extend along the transverse direction X and are connected to each other, and the branch line segments 143 of the T-shaped circuits 140 extend along the longitudinal direction Y toward the first region 113a of the inner bonding region 113 to respectively bond the bumps.

Referring to fig. 3 and 4, the circuit substrate 100 further has at least one dummy metal pattern (dummy pattern)150, the dummy metal pattern 150 is located between the connection segment 142 and the inner lead 122 and is not electrically connected to the T-shaped circuit 140 and the inner lead 122, the shape of the dummy metal pattern 150 is not limited in the present invention, and can be adjusted according to the configuration of the peripheral circuit, the dummy metal pattern 150 is used to protect the T-shaped circuit 140, and particularly to prevent the connection segment 142 and the branch line segment 143 from being broken due to over-etching, preferably, the circuit substrate 100 has two dummy metal patterns 150 respectively located at two sides of the branch line segment 143, and the dummy metal patterns 150 may be the same pattern, symmetrically located at two sides of the branch line segment 143, or different patterns, asymmetrically located at two sides of the branch line segment 143.

In the embodiment, the circuit layer 120, the T-shaped circuit 140 and the dummy metal pattern 150 are formed on the carrier 110 by the same metal etching process, and the dummy metal pattern 150 is located in the space surrounded by the connecting segment 142, the branch segment 143 and the inner leads 122, so that the etching solution can be prevented from accumulating around the connecting segment 142 and the branch segment 143, thereby preventing the connecting segment 142 and the branch segment 143 from being broken due to over-etching.

Fig. 4 to 8 are different versions of the T-shaped wire 140, different from fig. 4, the branch line segment 143 shown in fig. 5 extends along the longitudinal axis direction Y toward one of the inner leads 122, the branch line segment 143 shown in fig. 6 extends along the longitudinal axis direction Y to a position between two adjacent inner leads 122, preferably, the branch line segment 143 and the inner leads 122 have substantially the same line width, the branch line segment 143 shown in fig. 7 has a first end 143a and a second end 143b, the first end 143a is connected to the connecting segment 142, the second end 143b is used for connecting a bump, wherein the line width of the first end 143a is larger than the line width of the second end 143b to prevent the connecting segment 142 and the branch line segment 143 from being broken, and the second end 143b is located between two adjacent inner leads 122, different from fig. 7, the branch line segment 143 shown in fig. 8 is non-linear, the first end 143b and the second end 143b are perpendicular to each other.

Referring to fig. 2 and fig. 9 (fig. 9 is a cross-sectional view of fig. 7), the present invention further discloses a flip chip bonding structure I, which comprises the circuit substrate 100, the chip 200 and the solder layer 300, the chip 200 is disposed in the inner bonding region 113 of the carrier 110 and has a plurality of first bumps 210 and at least one second bump 220, the solder layer 300 is disposed between the circuit substrate 100 and the chip 200 for bonding the first bump 210 and the inner lead 122, and for bonding the second bump 220 and the branch segment 143, preferably, the thickness of the solder layer 300 is not greater than 0.30 μm, and more preferably, the thickness of the solder layer 300 is not greater than 0.20 μm, in the present embodiment, the solder layer 300 is formed on the inner leads 122 and the T-shaped circuit 140 with a thickness of 0.16 ± 0.4 μm, and the wafer 200 is disposed on the inner bonding region 113 and then subjected to a thermocompression bonding process, the solder layer 300 is softened by heating to bond the chip 200 and the circuit substrate 100.

Since the solder layer 300 has fluidity after being softened by heat, when the second bump 220 is bonded to the branch section 143, the solder layer 300 on the T-shaped circuit 140 flows to the branch section 143 from different directions, thereby increasing the overflow rate of the solder layer 300, and thus the design of the T-shaped circuit 140 can be selectively changed to avoid solder overflow and bridge short circuit.

Referring to fig. 4, the main line segment 141 has a first width W1 along the longitudinal direction Y, the connecting segment 142 has a second width W2 along the longitudinal direction Y, preferably, the second width W2 is smaller than the first width W1, the reduction of the width of the connecting segment 142 can effectively reduce the amount of solder flowing from the connecting segment 142 to the branch line segment 143 to avoid overflow of excessive solder flowing to the second bump 220, in addition, the branch line segment 143 has a third width W3 along the transverse direction X, and the ratio of the second width W2 to the third width W3 is greater than or equal to

When the ratio is between 0.5 and 1

Indicating that the second width W2 is less than the third width W3 when the ratio is equal to

Indicating that the second width W2 is equal to the third width W3 when the ratio is greater than

Indicating that the second width W2 is greater than the third width W3.

In addition to limiting the line width ratio among the main line segment 141, the connecting segment 142 and the branch line segment 143, the line width of the connecting segment 142 can be adjusted according to the size of the second bump 220. referring to fig. 5, preferably, the second bump 220 has a fourth width W4 along the horizontal axis direction X, and the ratio of the second width W2 to the fourth width W4 is smaller than

When the ratio is between 1 and 2

Indicating that the second width W2 is greater than the fourth width W4, but less than twice the fourth width W4 when the ratio is equal to

Indicating that the second width W2 is equal to the fourth width W4 when the ratio is less than

Indicating that the second width W2 is less than the fourth width W4.

Referring to fig. 6, the connecting section 142 has a first length L1 along the transverse axis direction X, the second bump 220 has a second length L2 along the longitudinal axis direction Y, and preferably, the length of the connecting section 142 is not less than 4 times the length of the second bump 220, so that the ratio of the first length L1 to the second length L2 is greater than or equal to

The length of the connecting segment 142 that needs to be narrowed can be determined according to the length of the second bump 220, in the embodiment, the branch line 143 is located at the center of the connecting segment 142, the shortest distances from the branch line 143 to the two ends of the connecting segment 142 are substantially the same, but the invention is not limited thereto, and the branch line 143 is selectively biased to one side of the connecting segment 142 according to different wiring design requirements.

Referring to fig. 6, a linear distance LD is provided between the connecting section 142 and the second bump 220, the linear distance LD is a shortest distance between the connecting section 142 and the second bump 220, and a ratio of the linear distance LD to the second width W2

In proportion to the thickness of the solder layer 300, when the second width W2 is constant but the thickness of the solder layer 300 is increased, the linear distance LD needs to be lengthened to avoid excessive solder flowing to the branch sections 143 to cause bridge short circuit, preferably, when the thickness of the solder layer 300 is substantially equal to 0.16 μm, the linear distance LD is greater than or equal to 3 times the second width W2, so that the thickness of the solder layer 300 is substantially equal to 0.16 μm, thereby the linear distance LD is required to be greater than or equal to 3 times the second width W2The ratio of the linear distance LD to the second width W2 is greater than or equal to

When the thickness of the solder layer 300 is substantially equal to 0.18 μm, the linear distance LD is greater than or equal to 4 times the second width W2, so the ratio of the linear distance LD to the second width W2 is greater than or equal to

In the embodiment shown in fig. 4 to 7, the second bump 220 has the fourth width W4 along the horizontal axis direction X, the second length L2 along the vertical axis direction Y, and the dummy metal patterns 150 on both sides of the branch line 143 are the same pattern and are mirror images of each other, unlike in the embodiment shown in fig. 4 to 7, in the embodiment shown in fig. 8, the second bump 220 has the fourth width W4 along the vertical axis direction Y, the second length L2 along the horizontal axis direction X, and the dummy metal patterns 150 on both sides of the branch line 143 are different patterns and are not symmetrical to each other.

Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A circuit substrate, comprising:

the carrier plate is provided with a surface, an inner joint area is defined on the surface, the inner joint area is provided with a first area and a second area, and the first area is positioned outside the second area;

a plurality of inner pins located in the first region;

at least one T-shaped circuit located in the second region, the T-shaped circuit having a main line segment, a connecting segment and a branch line segment, the main line segment connecting the connecting segment and extending along the direction of the transverse axis, the branch line segment connecting the connecting segment and extending along the direction of the longitudinal axis towards the first region, the branch line segment for engaging with the bump; and

at least one dummy metal pattern located between the connection segment and the inner lead, the dummy metal pattern not electrically connecting the inner lead and the T-shaped circuit.

2. The circuit substrate of claim 1, wherein the main line segment has a first width along the longitudinal axis, and the connecting segment has a second width along the longitudinal axis, the second width being smaller than the first width.

3. The circuit substrate of claim 2, wherein the branch segments have a third width along the transverse axis, and a ratio of the second width to the third width is not less than 0.5.

4. The circuit substrate of claim 1, wherein the branch segment extends along the longitudinal axis toward one of the inner leads.

5. The circuit substrate of claim 1, wherein the branch line segment extends along the longitudinal axis to a position between two adjacent inner leads.

6. The circuit substrate of claim 1, wherein the branch segment has a first end and a second end, the first end is connected to the connecting segment, the second end is used for connecting the bump, and the line width of the first end is greater than that of the second end.

7. The circuit substrate of claim 1, wherein the branch segment has a first end and a second end, the first end is connected to the connecting segment, the second end is used for engaging the bump, and the first end and the second end are perpendicular to each other.

8. The circuit substrate of claim 1, wherein there are two dummy metal patterns respectively located at two sides of the branch line segment.

9. A flip chip bonding structure, comprising:

the wiring substrate according to any one of claims 1 to 8;

the chip is arranged in the inner bonding area and provided with a plurality of first bumps and at least one second bump; and

the solder layer is positioned between the circuit substrate and the chip, is used for jointing the first bump and the inner pin, and is used for jointing the second bump and the branch section.

10. The flip-chip bonding structure of claim 9, wherein the second bump has a fourth width, and a ratio of the second width to the fourth width is less than 2.

11. The flip-chip bonding structure of claim 9, wherein the connecting segment has a first length along the transverse axis, the second bump has a second length, and a ratio of the first length to the second length is not less than 4.

12. The flip-chip bonding structure of claim 9, wherein a linear distance is provided between the connecting segment and the second bump, and a ratio of the linear distance to the second width is not less than 3.