JP4088561B2 - Flip chip mounting board - Google Patents

Flip chip mounting board Download PDF

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Publication number
JP4088561B2
JP4088561B2 JP2003172360A JP2003172360A JP4088561B2 JP 4088561 B2 JP4088561 B2 JP 4088561B2 JP 2003172360 A JP2003172360 A JP 2003172360A JP 2003172360 A JP2003172360 A JP 2003172360A JP 4088561 B2 JP4088561 B2 JP 4088561B2
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conductor pattern
connection pad
solder
mounting substrate
connection
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JP2005011902A (en
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聖二 佐藤
隆史 小澤
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はフリップチップ実装用基板に関し、より詳細には半導体素子に設けられた金属バンプと接合される接続パッドを備えたフリップチップ実装用基板に関する。
【０００２】
【従来の技術】
図５は接続電極である金属バンプとして金バンプ１２を備えた半導体素子１０を、フリップチップ接続用の接続パッド２２が形成された実装基板２０に実装する状態を示す説明図である。金バンプ１２と接続パッド２２との接合は金−はんだ接合によるものであり、接続パッド２２の表面にはあらかじめはんだ２３が付着されている。半導体素子１０の金バンプ１２と実装基板２０の接続パッド２２とを位置合わせし、加熱環境下で半導体素子１０を実装基板２０に加圧しながらはんだ２３を溶融し、金バンプ１２と接続パッド２２とを接合することによって半導体素子１０が実装される。
【０００３】
ところで、フリップチップ実装される半導体素子１０には、金属バンプの配置ピッチが１００μｍ以下といったきわめて狭ピッチに形成される製品があり、このような半導体素子１０を搭載する実装基板２０では、金属バンプの配置ピッチに合わせて、接続パッド２２が１００μｍ以下のきわめて狭ピッチに形成される。このように接続パッド２２の配置ピッチが狭くなると、接続パッド２２に供給したはんだによって隣接する接続パッド２２が短絡しやすくなるため、接続パッド２２に供給するはんだの量を制限せざるを得なくなる。その結果、接続パッド２２に付着するはんだの量が減って、金属バンプと接続パッド２２との接合が不確実になるという問題が生じる。
【０００４】
図６は、このような問題を回避するために、実装基板２０の実装面に金バンプ１２の配置ピッチに合わせて接続パッド２２と引き出し線２４からなる細長の導体パターン２５を形成し、接続パッド２２を導体パターン２５の長手方向の中央部に配置するとともに、接続パッド２２を引き出し線２４よりも幅広に形成した従来例である（たとえば、特許文献１参照）。この方法によれば、接続パッド２２と引き出し線２４にはんだを供給して溶融させた際に、はんだの表面張力によって、幅広の接続パッド２２の表面に厚くはんだを集めることができ、接続パッド２２の表面に融着するはんだ２３の量を確保することができる。
【０００５】
【特許文献１】
特開２０００−７７４７１号公報
【０００６】
【発明が解決しようとする課題】
上記のように、導体パターン２５を細長く形成して幅広の接続パッド２２を形成する方法は、導体パターン２５の配置ピッチが比較的広い場合には、導体パターン２５の配置にも余裕があり、接続パッド２２の形状等を所要の幅寸法等に形成することが可能であるが、導体パターン２５の配置ピッチが狭くなってくると、導体パターン２５の設計条件が厳しくなり、接続パッド２２を十分に幅広に形成することができなくなるという問題がある。
【０００７】
とくに、導体パターン２５の配置ピッチが１００μｍ以下といったようにきわめて狭くなると、エッチング等によって導体パターン２５を精度よく形成するための加工条件が厳しくなるから、設計通りに導体パターン２５を仕上げることが困難になり、図７に示すように、導体パターン２５を形成した際に、接続パッド２２の角部がダレたりするといったことがおきる。このように接続パッド２２が所定形状に仕上がらない場合には、接続パッド２２が所要のはんだを融着するに十分な面積を確保することができなくなるといった問題が生じる。
【０００８】
そこで、本発明はこれらの課題を解決すべくなされたものであり、その目的とするところは、フリップチップ実装に使用される実装用基板に設けられる接続パッドの配置ピッチが１００μｍ以下といったようにきわめて狭くなった場合であっても、接続パッドを所定の形状に形成することを可能とし、接続パッドに付着されるはんだの量を確保して、半導体素子を確実に実装することができるフリップチップ実装用基板を提供するにある。
【０００９】
【課題を解決するための手段】
上記課題を解決するため、本発明は次の構成を備える。
すなわち、接続電極として金属バンプを備える半導体素子をフリップチップ実装するフリップチップ実装用基板において、前記半導体素子を実装する実装面に、前記金属バンプの配置ピッチと一致する配置ピッチで、前記金属バンプが接合される接続パッドと該接続パッドに接続して設けられた引き出し線とからなる導体パターンが複数個配列されるとともに、前記各々の導体パターンの長手方向中央部に形成される接続パッドが、各々の導体パターンの一方の側縁から導体パターンの一方の側にのみ接続パッドの側縁を延出させて設けられていることを特徴とする。
【００１０】
また、前記金属バンプの配置ピッチが１００μｍ以下に設定されているフリップチップ実装用基板、また、前記導体パターンに供給したはんだが溶融され、接続パッドを含む導体パターンの表面にはんだが融着されているフリップチップ実装用基板が、接合電極として金属バンプを備えた半導体素子をフリップチップ実装する実装基板として好適に用いられる。
【００１１】
【発明の実施の形態】
以下、本発明の好適な実施の形態について添付図面と共に詳細に説明する。
本実施形態のフリップチップ実装用基板は、図５に示すような、金属バンプとして金バンプ１２を備えた半導体素子１０をフリップチップ実装する実装基板２０であり、実装基板２０の実装面に形成する導体パターン３０の形状を特徴とするものである。
図１に本実施形態のフリップチップ実装用基板に設ける導体パターン３０の平面形状を示す。導体パターン３０は半導体素子１０に形成されている金バンプ１２の配置ピッチに一致する配置で、長手方向を互いに平行にして多数個配列されている。導体パターン３０の長手方向の中央部には接続パッド３２が形成され、接続パッド３２に引き出し線３４が接続されていることは、図６に示す従来のフリップチップ実装基板における導体パターン２５の形態と同様である。
【００１２】
本実施形態のフリップチップ実装用基板において特徴的な構成は、従来の実装用基板においては、図６に示すように、導体パターン２５の長手方向の中央部で、導体パターン２５の両側縁から接続パッド２２の側縁を延出させることによって、引き出し線２４の線幅よりも幅広に接続パッド２２を形成しているのに対して、本実施形態の実装用基板では、導体パターン３０の一方の側縁のみから導体パターン３０の一方の側に向けて接続パッド３２の側縁を延出させるようにした点にある。すなわち、従来の実装用基板においては導体パターン２５の中心線に対して対称に接続パッド２２を形成しているのに対して、本実施形態の実装用基板においては、導体パターン３０の片側のみから接続パッド３２の側縁を延出させるようにしている。
なお、本実施形態において、各導体パターン３０に形成している接続パッド３２は、各々の導体パターン３０の一方の側縁から接続パッド３２の側縁を延出させ、すべて同じ向きに接続パッド３２が張り出すように設計している。
【００１３】
図２(a)、(b)に、本実施形態の実装用基板と従来の実装用基板に設けられている接続パッド２２、３２の平面形状を拡大して示す。Ｗ１が接続パッド３２、２２の幅、Ｗ２が引き出し線３４、２４の幅を示す。また、ΔＷが接続パッドの幅寸法Ｗ１と引き出し線の幅寸法Ｗ２との差（ΔＷ＝Ｗ１−Ｗ２）である。
図のように、本実施形態の実装用基板に設けられる接続パッド３２の幅Ｗ１と、従来の実装用基板に設けられている接続パッド２２の幅Ｗ１とは同一であり、接続パッド３２、２２の長さも同一である。すなわち、接続パッド３２、２２は本実施形態、および従来例ともに平面形状が矩形であり、面積が等しく形成されている。
また、導体パターン３０、２５に形成される引き出し線３４、２４の線幅Ｗ２も、本実施形態と従来例とで同一である。
【００１４】
このように実装用基板に形成される導体パターン３０、２５についてその設計上の条件でみる限り、本実施形態と従来の実装用基板とで接続パッド３２、２２にはんだを厚く集める作用についての作用上の相違はない。すなわち、図１に示す導体パターン３０の形態でも、図６に示す従来の導体パターン２５の形態でも、設計通りに正確に導体パターン３０、２５が形成できる限り、接続パッド３２、２２にはんだ２３を集める作用は同等である。
また、引き出し線３４、２４の線幅も本実施形態と従来例とでまったく同一の条件としているから、導体パターン３０、２５の配置ピッチについても本実施形態では従来例と同一の条件で設計することが可能である。
【００１５】
図２において、本実施形態と従来例の導体パターン３０、２５の側縁から張り出す接続パッド３２、２２の張り出し部３２ａ、２２ａの張り出し量についてみると、本実施形態では張り出し部３２ａの張り出し幅がΔＷとなるのに対して、従来例では張り出し部２２ａの張り出し幅が導体パターン２５の両側で各々ΔＷ／２となる。このように、導体パターン３０、２５の側縁から張り出す接続パッドの張り出し量が異なることは、実装用基板に導体パターン３０、２５を実際に形成する加工技術上においては重要な差となる。
【００１６】
すなわち、実装用基板に導体パターン３０、２５を形成する際には、フォトリソグラフィー法等の導体パターンを形成するための公知の方法が利用される。導体パターン等を所定のパターンに形成する方法には種々の方法があるが、導体パターンが微細なパターンになればなるほど、導体パターンの線幅などの仕上がり精度のばらつきが大きくなる。
図３は、本実施形態の方法（導体パターンの片側に接続パッドの側縁が延出する）と従来方法（導体パターンの両側に接続パッドの側縁が延出する）で実際に実装用基板に導体パターン３０、２５を形成し、導体パターン３０、２５に形成された接続パッド３２、２２の張り出し量のばらつきを実測した結果を示すグラフである。
【００１７】
この実験で実際に作成した実装用基板での導体パターンの設計条件は、導体パターン３０、２５の配置ピッチＬ１＝６５μｍ、接続パッド３２、２２の幅Ｗ１＝３５μｍ、引き出し線３４、２４の線幅Ｗ２＝３０μｍ、接続パッド３２、２２の側縁と隣接する導体パターン３０、２５の側縁との間隔Ｌ２＝３０μｍである。
この条件の場合、本実施形態では、接続パッド３２の張り出し部３２ａの張り出し幅（ΔＷ）は５μｍであり、従来例での張り出し部２２ａの張り出し幅（ΔＷ／２）は２．５μｍとなる。
【００１８】
図３は、従来方法による場合は、接続パッド２２の側縁位置が設計位置から大きくばらつくこと、これに対して、本実施形態の方法によると接続パッド３２の側縁位置のばらつきがより小さく抑えられることを示している。
上記の実験条件のように、導体パターン３０、２５の配置ピッチが６５μｍといったきわめて狭ピッチにパターン形成するような場合には、加工技術上、設計寸法通りに導体パターンを仕上げることが困難であり、とくに従来例のように導体パターン２５の両側に接続パッド２２を張り出す設計の場合には、接続パッド２２の張り出し量（２．５μｍ）がわずかであるために、導体パターン２５をパターン形成する際の解像度が不十分であったりすると、設計通りのパターンに仕上げることが難しいといったことが生じる。
【００１９】
これに対して、本実施形態の場合には、導体パターン３０の側縁からの接続パッド３２の張り出し量は５μｍであり、従来方法にくらべて接続パッド３２をパターン形成する際の困難度が緩和され、同一の加工精度を備えた加工装置を使用した場合であっても、従来方法による場合よりも精度よく導体パターン３０を形成することが可能になる。
すなわち、図２(b)のような従来の導体パターン２５の形態にパターン形成するためには、引き出し線２４と接続パッド２２との接続部における段差部分等を所定精度で仕上げることができる加工精度が求められるのに対して、図２(a)の本実施形態の導体パターン３０の形態にパターン形成する場合には、引き出し線３４と接続パッド３２との接続部の段差部はより大きくなり、図２(b)のパターンを形成する場合にくらべて実質的により広幅のパターンを形成する条件となり、導体パターン３０を形成するための加工精度が緩和されることになる。
【００２０】
このように本実施形態のフリップチップ実装用基板は、接続パッド３２を備える導体パターン３０の形状を変更するという方法を採用するだけで、従来の加工装置では導体パターン２５の配置ピッチがきわめて狭くなったような場合に、所定の精度に接続パッド２２をパターン形成できなかったような場合でも、加工装置の加工精度を上げることなく、所要の精度で導体パターン３０を形成することが可能となる。そして、導体パターン３０を所要の精度で形成できることから、接続パッド３２に所要量のはんだを融着させることができ、半導体素子を確実にフリップチップ実装することができる実装用基板として提供することが可能となる。
【００２１】
図４は、実装用基板の表面に、本実施形態の方法と従来方法とによって、接続パッド３２、２２の幅が異なる導体パターンをいくつか形成し、導体パターン３０、２５の表面にはんだを供給した後、はんだを溶融して各々の導体パターン３０、２５について接続パッド３２、２２の表面に融着したはんだの厚さを測定した結果を示す。なお、導体パターン３０、２５は引き出し線の線幅を３０μｍとし、この引き出し線の側縁からの接続パッドの張り出し量を変えてサンプルとしたものである。
【００２２】
図４で、横軸は接続パッドの幅Ｗ１と引き出し線の幅Ｗ２の差ΔＷを示す。図４は、接続パッドと引き出し線の幅の差ΔＷが５μｍよりも大きい場合には、接続パッドの表面に融着されるはんだの厚さは本実施形態の方法と従来方法とで有意差はなく、接続パッドと引き出し線の幅の差ΔＷが５μｍ以下になってくると、従来方法の場合には接続パッドに融着されるはんだの厚さが大きく減少することを示している。
この結果は、接続パッドと引き出し線の幅の差ΔＷが５μｍよりも大きい場合は、加工装置の加工精度が導体パターンを所定精度に仕上げるに十分な精度を有しており、導体パターンの形成精度に影響があらわれないようになっているのに対して、接続パッドと引き出し線の幅の差ΔＷが５μｍよりも小さくなると、加工装置の加工精度が導体パターンの形成精度に影響を及ぼすようになることを示している。
【００２３】
したがって、本実施形態の方法による場合は、接続パッド３２と引き出し線３４の幅の差ΔＷが５μｍよりも小さくなる場合であっても所定の精度で導体パターン３０を形成することができ、接続パッド３２が所定形状に仕上げられることによって接続パッド３２に所要の厚さにはんだ２３を融着することが可能となる。すなわち、導体パターン３０の配置ピッチがきわめて狭くなった場合でも、本実施形態のような導体パターン３０の形状とすることで、接続パッド３２を所要の精度で形成することができ、接続パッド３２に所要の厚さではんだ２３を融着することができることから、半導体素子を確実にフリップチップ実装することができる実装用基板として提供することが可能になる。
【００２４】
なお、図４では、接続パッドと引き出し線の幅の差ΔＷがある程度以上大きくなると、接続パッドに融着されるはんだの厚さが減少することを示す。接続パッドに融着されるはんだの厚さが厚くなるのは、はんだが溶融した際に、はんだの表面張力によって幅広に形成した接続パッドにはんだが集められる作用による。接続パッドの幅がある程度以上になると、はんだの厚さが減少するのは、接続パッドの面積が大きくなることによって、はんだを厚く形成する範囲が広がり、導体パターンへのはんだの供給量が増加する増加分によってはんだの厚さを厚く維持することができなくなるためである。
【００２５】
【発明の効果】
本発明に係るフリップチップ実装用基板によれば、上述したように、半導体素子を接合する接続パッドを含む導体パターンの配置ピッチがきわめて狭くなった場合でも、実装用基板に所定の精度で接続パッドを含む導体パターンを形成することができ、接続パッドに所要の厚さにはんだを融着することが可能となることから、金属バンプを備えた半導体素子を確実にフリップチップ実装することができる実装用基板として提供することができる等の著効を奏する。
【図面の簡単な説明】
【図１】本発明に係るフリップチップ実装用基板の実装面に形成される導体パターンの平面形状を示す説明図である。
【図２】本実施形態と従来例での導体パターンの形状を拡大して示す説明図である。
【図３】導体パターンに形成される接続パッドの側縁位置のばらつきを測定した結果を示すグラフである。
【図４】接続パッドの表面に融着したはんだの厚さを測定した結果を示すグラフである。
【図５】半導体素子を実装用基板にフリップチップ実装する状態を示す説明図である。
【図６】従来のフリップチップ実装用基板の実装面に形成される導体パターンの平面形状を示す説明図である。
【図７】導体パターンを拡大して示す説明図である。
【符号の説明】
１０ 半導体素子
１２ 金バンプ
２０ 実装基板
２２、３２ 接続パッド
２２ａ、３２ａ 張り出し部
２３ はんだ
２４、３４ 引き出し線
２５、３０ 導体パターン[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flip-chip mounting substrate, and more particularly to a flip-chip mounting substrate having connection pads bonded to metal bumps provided on a semiconductor element.
[0002]
[Prior art]
FIG. 5 is an explanatory diagram showing a state in which the semiconductor element 10 having the gold bumps 12 as the metal bumps as connection electrodes is mounted on the mounting substrate 20 on which the connection pads 22 for flip chip connection are formed. The bonding between the gold bump 12 and the connection pad 22 is by gold-solder bonding, and the solder 23 is attached to the surface of the connection pad 22 in advance. The gold bumps 12 of the semiconductor element 10 and the connection pads 22 of the mounting substrate 20 are aligned, and the solder 23 is melted while pressing the semiconductor element 10 against the mounting substrate 20 in a heating environment. The semiconductor element 10 is mounted by bonding.
[0003]
By the way, there is a product in which the semiconductor chip 10 to be flip-chip mounted is formed with a very narrow pitch such that the arrangement pitch of the metal bumps is 100 μm or less. In the mounting substrate 20 on which such a semiconductor element 10 is mounted, In accordance with the arrangement pitch, the connection pads 22 are formed at a very narrow pitch of 100 μm or less. When the arrangement pitch of the connection pads 22 becomes narrow in this way, the adjacent connection pads 22 are easily short-circuited by the solder supplied to the connection pads 22, so that the amount of solder supplied to the connection pads 22 has to be limited. As a result, the amount of solder adhering to the connection pad 22 is reduced, causing a problem that the bonding between the metal bump and the connection pad 22 becomes uncertain.
[0004]
In FIG. 6, in order to avoid such a problem, an elongated conductor pattern 25 including connection pads 22 and lead lines 24 is formed on the mounting surface of the mounting substrate 20 in accordance with the arrangement pitch of the gold bumps 12, and the connection pads are formed. This is a conventional example in which 22 is arranged at the center in the longitudinal direction of the conductor pattern 25 and the connection pad 22 is formed wider than the lead wire 24 (see, for example, Patent Document 1). According to this method, when the solder is supplied to the connection pad 22 and the lead wire 24 and melted, the solder can be thickly collected on the surface of the wide connection pad 22 by the surface tension of the solder. It is possible to secure the amount of solder 23 to be fused to the surface of the solder.
[0005]
[Patent Document 1]
JP 2000-77471 A [0006]
[Problems to be solved by the invention]
As described above, the method in which the conductor pattern 25 is formed to be long and the wide connection pad 22 is formed has a margin in the arrangement of the conductor pattern 25 when the arrangement pitch of the conductor pattern 25 is relatively wide. The shape of the pad 22 can be formed to a required width dimension or the like. However, when the arrangement pitch of the conductor pattern 25 becomes narrower, the design condition of the conductor pattern 25 becomes severe, and the connection pad 22 is sufficiently formed. There is a problem that it cannot be formed in a wide width.
[0007]
In particular, when the arrangement pitch of the conductor patterns 25 is extremely narrow, such as 100 μm or less, the processing conditions for accurately forming the conductor patterns 25 by etching or the like become severe, so that it is difficult to finish the conductor patterns 25 as designed. Thus, as shown in FIG. 7, when the conductor pattern 25 is formed, the corners of the connection pad 22 may sag. Thus, when the connection pad 22 is not finished in a predetermined shape, there arises a problem that the connection pad 22 cannot secure a sufficient area for fusing required solder.
[0008]
Therefore, the present invention has been made to solve these problems, and the object of the present invention is to make the arrangement pitch of connection pads provided on a mounting substrate used for flip-chip mounting extremely small, such as 100 μm or less. Flip chip mounting that makes it possible to form a connection pad in a predetermined shape even when it becomes narrower, secure the amount of solder attached to the connection pad, and securely mount semiconductor elements Is to provide a substrate.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configuration.
That is, in a flip chip mounting substrate on which a semiconductor element having metal bumps as connection electrodes is flip-chip mounted, the metal bumps are arranged on the mounting surface for mounting the semiconductor elements at an arrangement pitch that matches the arrangement pitch of the metal bumps. A plurality of conductor patterns each composed of a connection pad to be joined and a lead line connected to the connection pad are arranged, and a connection pad formed at a central portion in the longitudinal direction of each conductor pattern, The side edge of the connection pad is provided so as to extend from one side edge of the conductor pattern only to one side of the conductor pattern.
[0010]
Also, the metal bumps flip chip mounting substrate arrangement pitch is set to 100μm following also, the are solder supplied to the conductive pattern molten solder is fused on the surface of the conductive pattern including the connection pads The flip-chip mounting substrate is preferably used as a mounting substrate for flip-chip mounting a semiconductor element having metal bumps as bonding electrodes.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.
The flip chip mounting substrate of this embodiment is a mounting substrate 20 on which a semiconductor element 10 having gold bumps 12 as metal bumps is flip chip mounted as shown in FIG. 5, and is formed on the mounting surface of the mounting substrate 20. The shape of the conductor pattern 30 is a feature.
FIG. 1 shows a planar shape of a conductor pattern 30 provided on the flip chip mounting substrate of this embodiment. A large number of conductor patterns 30 are arranged so as to coincide with the arrangement pitch of the gold bumps 12 formed on the semiconductor element 10 and their longitudinal directions are parallel to each other. The connection pad 32 is formed at the center in the longitudinal direction of the conductor pattern 30 and the lead wire 34 is connected to the connection pad 32. This is because the conductor pattern 25 in the conventional flip chip mounting substrate shown in FIG. It is the same.
[0012]
A characteristic configuration of the flip chip mounting substrate of the present embodiment is that, in the conventional mounting substrate, as shown in FIG. 6, it is connected from both side edges of the conductor pattern 25 at the center in the longitudinal direction of the conductor pattern 25. By extending the side edge of the pad 22, the connection pad 22 is formed wider than the line width of the lead line 24, whereas in the mounting substrate of this embodiment, one of the conductor patterns 30 is formed. The side edge of the connection pad 32 extends from only the side edge toward one side of the conductor pattern 30. That is, in the conventional mounting substrate, the connection pads 22 are formed symmetrically with respect to the center line of the conductor pattern 25, whereas in the mounting substrate of this embodiment, the connection pad 22 is only from one side of the conductor pattern 30. The side edges of the connection pads 32 are extended.
In the present embodiment, the connection pads 32 formed on each conductor pattern 30 have the side edges of the connection pads 32 extending from one side edge of each conductor pattern 30 and are all connected in the same direction. Is designed to overhang.
[0013]
2A and 2B are enlarged views of the planar shapes of the connection pads 22 and 32 provided on the mounting substrate of the present embodiment and the conventional mounting substrate. W1 indicates the width of the connection pads 32 and 22, and W2 indicates the width of the lead lines 34 and 24. ΔW is a difference (ΔW = W1−W2) between the width dimension W1 of the connection pad and the width dimension W2 of the lead line.
As shown in the figure, the width W1 of the connection pad 32 provided on the mounting board of the present embodiment is the same as the width W1 of the connection pad 22 provided on the conventional mounting board. Are the same length. That is, the connection pads 32 and 22 have a rectangular planar shape and the same area in both this embodiment and the conventional example.
Also, the line width W2 of the lead lines 34 and 24 formed in the conductor patterns 30 and 25 is the same in this embodiment and the conventional example.
[0014]
As long as the conductor patterns 30 and 25 formed on the mounting substrate are examined in terms of design conditions, the present embodiment and the conventional mounting substrate have the effect of thickly collecting solder on the connection pads 32 and 22. There is no difference above. That is, in both the form of the conductor pattern 30 shown in FIG. 1 and the form of the conventional conductor pattern 25 shown in FIG. 6, the solder 23 is applied to the connection pads 32 and 22 as long as the conductor patterns 30 and 25 can be accurately formed as designed. The collecting action is equivalent.
In addition, since the line widths of the lead lines 34 and 24 are set to exactly the same conditions in the present embodiment and the conventional example, the arrangement pitch of the conductor patterns 30 and 25 is also designed in the present embodiment under the same conditions as in the conventional example. It is possible.
[0015]
Referring to FIG. 2, the amount of protrusion of the protruding portions 32a and 22a of the connection pads 32 and 22 protruding from the side edges of the conductor patterns 30 and 25 of the present embodiment and the conventional example is as follows. In contrast, in the conventional example, the overhanging width of the overhanging portion 22 a is ΔW / 2 on both sides of the conductor pattern 25. As described above, the difference in the protruding amount of the connection pad protruding from the side edges of the conductor patterns 30 and 25 is an important difference in the processing technique for actually forming the conductor patterns 30 and 25 on the mounting substrate.
[0016]
That is, when forming the conductor patterns 30 and 25 on the mounting substrate, a known method for forming a conductor pattern such as a photolithography method is used. There are various methods for forming a conductor pattern or the like into a predetermined pattern, but the finer the conductor pattern, the greater the variation in finish accuracy such as the line width of the conductor pattern.
FIG. 3 shows an actual mounting substrate using the method of this embodiment (the side edges of the connection pads extend on one side of the conductor pattern) and the conventional method (the side edges of the connection pads extend on both sides of the conductor pattern). 5 is a graph showing the results of actual measurement of the variation in the amount of protrusion of the connection pads 32 and 22 formed on the conductor patterns 30 and 25. FIG.
[0017]
The design conditions of the conductor pattern in the mounting substrate actually created in this experiment are as follows: the arrangement pitch L1 of the conductor patterns 30 and 25 is 65 μm, the width W1 of the connection pads 32 and 22 is 35 μm, and the line widths of the lead lines 34 and 24 W2 = 30 μm, and the distance L2 = 30 μm between the side edges of the connection pads 32 and 22 and the side edges of the adjacent conductor patterns 30 and 25.
Under this condition, in this embodiment, the overhang width (ΔW) of the overhang portion 32a of the connection pad 32 is 5 μm, and the overhang width (ΔW / 2) of the overhang portion 22a in the conventional example is 2.5 μm.
[0018]
FIG. 3 shows that when the conventional method is used, the side edge position of the connection pad 22 varies greatly from the design position. On the other hand, according to the method of this embodiment, the variation in the side edge position of the connection pad 32 is suppressed to a smaller value. It is shown that.
As in the above experimental conditions, in the case of forming a pattern with a very narrow pitch such as the arrangement pitch of the conductor patterns 30 and 25 of 65 μm, it is difficult to finish the conductor pattern according to the design dimension in terms of processing technology. In particular, in the case where the connection pad 22 is projected on both sides of the conductor pattern 25 as in the conventional example, the amount of projection (2.5 μm) of the connection pad 22 is very small. If the resolution is insufficient, it may be difficult to finish the pattern as designed.
[0019]
On the other hand, in the case of the present embodiment, the protruding amount of the connection pad 32 from the side edge of the conductor pattern 30 is 5 μm, and the difficulty in patterning the connection pad 32 is reduced compared to the conventional method. Even when a processing apparatus having the same processing accuracy is used, the conductor pattern 30 can be formed with higher accuracy than in the conventional method.
That is, in order to form a pattern in the form of the conventional conductor pattern 25 as shown in FIG. 2 (b), the processing accuracy that can finish the step portion and the like in the connection portion between the lead line 24 and the connection pad 22 with a predetermined accuracy. 2 is required, when the pattern is formed in the form of the conductor pattern 30 of the present embodiment in FIG. 2A, the stepped portion of the connection portion between the lead line 34 and the connection pad 32 becomes larger. Compared with the case of forming the pattern of FIG. 2B, a condition for forming a substantially wider pattern is obtained, and the processing accuracy for forming the conductor pattern 30 is relaxed.
[0020]
As described above, the flip chip mounting substrate of this embodiment simply adopts the method of changing the shape of the conductor pattern 30 including the connection pads 32, and the arrangement pitch of the conductor pattern 25 becomes extremely narrow in the conventional processing apparatus. In such a case, even when the connection pad 22 cannot be formed with a predetermined accuracy, the conductor pattern 30 can be formed with a required accuracy without increasing the processing accuracy of the processing apparatus. Since the conductor pattern 30 can be formed with a required accuracy, a required amount of solder can be fused to the connection pad 32, and a semiconductor substrate can be provided as a mounting substrate that can be surely flip-chip mounted. It becomes possible.
[0021]
In FIG. 4, several conductor patterns having different widths of the connection pads 32 and 22 are formed on the surface of the mounting substrate by the method of this embodiment and the conventional method, and solder is supplied to the surfaces of the conductor patterns 30 and 25. Then, the results of measuring the thickness of the solder melted on the surfaces of the connection pads 32 and 22 for the respective conductor patterns 30 and 25 by melting the solder are shown. The conductor patterns 30 and 25 are samples in which the width of the lead line is 30 μm and the amount of extension of the connection pad from the side edge of the lead line is changed.
[0022]
In FIG. 4, the horizontal axis indicates the difference ΔW between the width W1 of the connection pad and the width W2 of the lead line. FIG. 4 shows that when the width difference ΔW between the connection pad and the lead wire is larger than 5 μm, the thickness of the solder fused to the surface of the connection pad is not significantly different between the method of this embodiment and the conventional method. When the difference ΔW between the connection pad and the lead wire is 5 μm or less, the thickness of solder fused to the connection pad is greatly reduced in the case of the conventional method.
As a result, when the difference ΔW between the width of the connection pad and the lead wire is larger than 5 μm, the processing accuracy of the processing apparatus has sufficient accuracy to finish the conductor pattern to a predetermined accuracy, and the formation accuracy of the conductor pattern On the other hand, if the difference ΔW between the width of the connection pad and the lead wire is smaller than 5 μm, the processing accuracy of the processing device affects the formation accuracy of the conductor pattern. It is shown that.
[0023]
Therefore, according to the method of the present embodiment, the conductor pattern 30 can be formed with a predetermined accuracy even when the width difference ΔW between the connection pad 32 and the lead line 34 is smaller than 5 μm. By finishing 32 into a predetermined shape, the solder 23 can be fused to the connection pad 32 to a required thickness. That is, even when the arrangement pitch of the conductor pattern 30 is extremely narrow, the connection pad 32 can be formed with a required accuracy by using the shape of the conductor pattern 30 as in the present embodiment. Since the solder 23 can be fused with a required thickness, it is possible to provide a mounting substrate that can be surely flip-chip mounted on a semiconductor element.
[0024]
FIG. 4 shows that the thickness of the solder fused to the connection pad decreases when the width difference ΔW between the connection pad and the lead line increases to a certain extent. The thickness of the solder fused to the connection pad is increased due to the action of collecting the solder on the connection pad formed wide by the surface tension of the solder when the solder is melted. When the width of the connection pad exceeds a certain level, the solder thickness decreases because the area of the connection pad increases, the range in which the solder is formed thicker, and the amount of solder supplied to the conductor pattern increases. This is because the thickness of the solder cannot be increased due to the increase.
[0025]
【The invention's effect】
According to the flip-chip mounting substrate according to the present invention, as described above, even when the arrangement pitch of the conductor pattern including the connection pads for joining the semiconductor elements is extremely narrow, the connection pads are attached to the mounting substrate with a predetermined accuracy. As a result, it is possible to form a conductor pattern including solder, and solder can be fused to the connection pad to a required thickness. It can be provided as a substrate for use.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a planar shape of a conductor pattern formed on a mounting surface of a flip chip mounting substrate according to the present invention.
FIG. 2 is an explanatory diagram showing an enlarged shape of a conductor pattern in the present embodiment and a conventional example.
FIG. 3 is a graph showing a result of measuring variations in side edge positions of connection pads formed in a conductor pattern.
FIG. 4 is a graph showing the results of measuring the thickness of solder fused to the surface of a connection pad.
FIG. 5 is an explanatory view showing a state in which a semiconductor element is flip-chip mounted on a mounting substrate.
FIG. 6 is an explanatory view showing a planar shape of a conductor pattern formed on a mounting surface of a conventional flip chip mounting substrate.
FIG. 7 is an explanatory diagram showing an enlarged conductor pattern.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor element 12 Gold bump 20 Mounting board 22, 32 Connection pad 22a, 32a Overhang | projection part 23 Solder 24, 34 Lead line 25, 30 Conductor pattern

Claims (3)

接続電極として金属バンプを備える半導体素子をフリップチップ実装するフリップチップ実装用基板において、
前記半導体素子を実装する実装面に、前記金属バンプの配置ピッチと一致する配置ピッチで、前記金属バンプが接合される接続パッドと該接続パッドに接続して設けられた引き出し線とからなる導体パターンが複数個配列されるとともに、
前記各々の導体パターンの長手方向中央部に形成される接続パッドが、各々の導体パターンの一方の側縁から導体パターンの一方の側にのみ接続パッドの側縁を延出させて設けられていることを特徴とするフリップチップ実装用基板。In a flip chip mounting substrate for flip chip mounting a semiconductor element having metal bumps as connection electrodes,
A conductor pattern comprising connection pads to which the metal bumps are bonded and lead lines connected to the connection pads on the mounting surface on which the semiconductor element is mounted at an arrangement pitch that matches the arrangement pitch of the metal bumps. Are arranged, and
The connection pad formed at the center in the longitudinal direction of each conductor pattern is provided with the side edge of the connection pad extending from one side edge of each conductor pattern only to one side of the conductor pattern. A flip-chip mounting board characterized by the above. 前記金属バンプの配置ピッチが１００μｍ以下に設定されていることを特徴とする請求項１記載のフリップチップ実装用基板。2. The flip chip mounting substrate according to claim 1, wherein an arrangement pitch of the metal bumps is set to 100 [mu] m or less . 前記導体パターンに供給したはんだが溶融され、接続パッドを含む導体パターンの表面にはんだが融着されていることを特徴とする請求項１または２記載のフリップチップ実装用基板。3. The flip chip mounting substrate according to claim 1, wherein the solder supplied to the conductor pattern is melted and the solder is fused to the surface of the conductor pattern including the connection pads .
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