CN113132038A - Simulation test system of large-scale MIMO system - Google Patents
Simulation test system of large-scale MIMO system Download PDFInfo
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- CN113132038A CN113132038A CN202110376432.2A CN202110376432A CN113132038A CN 113132038 A CN113132038 A CN 113132038A CN 202110376432 A CN202110376432 A CN 202110376432A CN 113132038 A CN113132038 A CN 113132038A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/30—Monitoring; Testing of propagation channels
- H04B17/391—Modelling the propagation channel
- H04B17/3912—Simulation models, e.g. distribution of spectral power density or received signal strength indicator [RSSI] for a given geographic region
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/0413—MIMO systems
Abstract
The application discloses simulation test system of large-scale MIMO system, this system includes general software radio peripheral equipment USRP, high-speed serial computer expansion bus standard PCIe machine case and high performance general processor, wherein: the PCIe chassis comprises a plurality of main PCIe chassis and a plurality of sub-PCIe chassis, wherein one main PCIe chassis is connected with the plurality of sub-PCIe chassis, and one sub-PCIe chassis is connected with the plurality of USRPs; the USRP is used for acquiring antenna data and sending the acquired antenna data to a sub PCIe chassis connected with the USRP; the sub PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the main PCIe chassis connected with the sub PCIe chassis; the main PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to a high-performance general processor connected with the main PCIe chassis, so that the high-performance general processor processes the received antenna data to obtain a processed baseband signal.
Description
Technical Field
The application relates to the technical field of wireless communication, in particular to a simulation test system of a large-scale MIMO system.
Background
Currently, there is much research devoted to constructing a test evaluation platform for Multiple Input Multiple Output (MIMO) and massive MIMO systems. Sun et al have set up MIMO system under the millimeter wave environment, have analyzed the channel characteristic of the millimeter wave environment, have carried on the detailed assessment to the frequency spectrum efficiency of cell and user. Ove Edford et al developed a massive MIMO system LuMaMi based on the National Instruments (NI) hardware platform. Shepard C et al developed a prototype validation system Arogs for massive MIMO beamforming.
However, the above platform is not open in software level for large-scale MIMO research, and the hardware device is expensive, has a higher threshold, and has poor scalability. Based on this, the french Eurecom organization has launched an open source Software project Open Air Interface (OAI), and a complete 3GPP protocol stack is implemented by a Software simulation method, and the OAI is one of the most perfect open source Software Defined Radio (SDR) platforms at present. Yang et al developed an Open 5G universal platform based on OAI, and realized MIMO parallel channel and air interface tests.
However, the above platforms are all simulation tests for MIMO systems, and no corresponding simulation test method is yet provided for simulation tests for large-scale MIMO systems.
Disclosure of Invention
The embodiment of the invention provides a simulation test system of a large-scale MIMO system, which is used for solving the problem that the simulation test system in the prior art is lack of simulation test of the large-scale MIMO system because the simulation test system aims at the simulation test of the MIMO system.
The embodiment of the invention adopts the following technical scheme:
the simulation test system of the large-scale MIMO system comprises a universal software radio peripheral equipment USRP, a high-speed serial computer expansion bus standard PCIe case and a high-performance universal processor, wherein the simulation test system comprises:
the PCIe chassis comprises a plurality of main PCIe chassis and a plurality of sub-PCIe chassis, wherein one main PCIe chassis is connected with the plurality of sub-PCIe chassis, and one sub-PCIe chassis is connected with the plurality of USRPs;
the USRP is used for acquiring antenna data and sending the acquired antenna data to a sub PCIe chassis connected with the USRP;
the sub PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the main PCIe chassis connected with the sub PCIe chassis;
the main PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to a high-performance general processor connected with the main PCIe chassis, so that the high-performance general processor processes the received antenna data to obtain a processed baseband signal.
Optionally, the USRP is configured to:
and sending the acquired antenna data to a sub PCIe case connected with the USRP through a common public radio interface CPRI protocol.
Optionally, the sub-PCIe chassis is configured to:
and sending the collected antenna data to a main PCIe chassis connected with the antenna data through a CPRI protocol.
Optionally, the primary PCIe chassis is configured to:
and sending the collected antenna data to a high-performance general-purpose processor connected with the antenna data through a CPRI protocol.
Optionally, an open air interface OAI platform is set up in the high-performance general processor, and the OAI platform is configured to process the received antenna data to obtain a processed baseband signal.
Optionally, the PCIe chassis includes a plurality of main PCIe chassis and a plurality of sub PCIe chassis, one main PCIe chassis is connected to the 4 sub PCIe chassis, and one sub PCIe chassis is connected to at most 16 USRPs.
Optionally, the number of sub-PCIe chassis connected to the plurality of main PCIe chassis is consistent; or
The number of sub-PCIe chassis connected to the plurality of main PCIe chassis is not consistent.
Optionally, the high-performance general-purpose processor is connected to the plurality of main PCIe chassis through PCIe standard interfaces.
Optionally, one sub-PCIe chassis is connected to a maximum of 16 USRPs via optical fibers.
The embodiment of the invention adopts at least one technical scheme which can achieve the following beneficial effects:
the simulation test system of the large-scale MIMO system provided by the embodiment of the invention comprises a universal software radio peripheral equipment USRP, a high-speed serial computer expansion bus standard PCIe chassis and a high-performance universal processor, wherein: the PCIe chassis comprises a plurality of main PCIe chassis and a plurality of sub-PCIe chassis, one main PCIe chassis is connected with the plurality of sub-PCIe chassis, and one sub-PCIe chassis is connected with the plurality of USRPs; the USRP is used for acquiring antenna data and sending the acquired antenna data to a sub PCIe chassis connected with the USRP; the sub PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the main PCIe chassis connected with the sub PCIe chassis; the main PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the high-performance general processor connected with the main PCIe chassis, so that the high-performance general processor processes the received antenna data to obtain a processed baseband signal. Because the sub PCIe chassis can be connected with the USRPs and the main PCIe chassis is connected with the sub PCIe chassis, the connection of the USRPs is expanded, and the problem of the connection of the large-scale USRPs aiming at the large-scale MIMO system is solved. In addition, a large amount of gathered antenna data is processed through the high-performance general processor, and the data processing efficiency of the system is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic structural diagram of a simulation test system of a large-scale MIMO system according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a data processing flow of an uplink in a simulation test system of a massive MIMO system according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a data processing flow of a downlink in a simulation test system of a massive MIMO system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The technical solutions provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
The embodiment of the application provides a simulation test system of a large-scale MIMO system, and the simulation test system can be connected with a plurality of Universal Software Radio Peripheral equipment (USRP) through one sub PCIe chassis and connected with a plurality of sub PCIe chassis through one main PCIe chassis, so that the connection of the USRP is expanded, and the connection problem of the large-scale USRP of the large-scale MIMO system is solved. In addition, a large amount of gathered antenna data is processed through the high-performance general processor, and the data processing efficiency of the system is improved.
Specifically, a schematic structural diagram of a simulation test system of a massive MIMO system provided in one or more embodiments of the present specification is shown in fig. 1, and includes a universal software radio peripheral USRP 130, a high-speed serial computer expansion bus standard PCIe chassis 120, and a high-performance general-purpose processor 110, where:
the PCIe chassis 120 includes a plurality of main PCIe chassis and a plurality of sub PCIe chassis, one main PCIe chassis is connected to the plurality of sub PCIe chassis, and one sub PCIe chassis is connected to the plurality of USRPs;
the USRP 130 is used for collecting antenna data and sending the collected antenna data to a sub PCIe chassis connected with the USRP;
the sub PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the main PCIe chassis connected with the sub PCIe chassis;
the main PCIe chassis is configured to collect received antenna data and send the collected antenna data to the high-performance general processor 110 connected thereto, so that the high-performance general processor 110 processes the received antenna data to obtain a processed baseband signal.
It should be understood that in a massive MIMO system, since the number of transmitting and receiving antennas is significantly increased compared to 4G, and the antenna and channel parameter model is also more complex, the amount of computation is greatly increased compared to the TU channel commonly used in 4G. For example, only by analyzing the number of FFT computations for converting a time domain channel into a frequency domain channel, the number of FFT computations for a 3D channel of a cell is about M × Nt × Nr (the number of OFDM symbols is M, the number of receiving antennas is Nr, and the number of base station antennas is Nt), and when the antenna size is 256 × 15 downlink, the computation amount will increase linearly with the product of the number of transmitting antennas and the number of receiving antennas compared to the existing antenna size.
In order to solve this problem, the embodiment of the present invention uses the high performance general processor 110 to process the received antenna data, so as to obtain a processed baseband signal. Under the condition of given simulation parameters, because the wireless link channel coefficient is irrelevant to behaviors such as system adjustment and the like, the channel calculation can be completed by the high-performance general processor in advance, the calculation result is stored in a hard disk of the high-performance general processor, and the channel matrix stored in the hard disk can be directly read and stored in the memory when the simulation system is initialized. In the running process of the simulation program, a channel matrix does not need to be calculated, and a pre-calculated result is directly used, so that the channel calculation time is saved, if the memory is large enough, the actual time overhead only depends on the time for reading the memory, and the channel calculation time can be ignored.
Because the precoding of the transmitting end mainly involves multiplication and inversion calculation of a large matrix, the calculation can fully utilize the multi-core calculation capability of a CPU and a GPU in a high-performance general processor to perform parallel calculation at a subcarrier level. Firstly, parallel processing is carried out on subcarrier granularity by utilizing the parallel computing capability of a CPU in a high-performance general processor, precoding computing work of different subcarriers is distributed to different CPU board cards (such as the CPU 1-CPU 4 in the high-performance general processor in the figure 1) to carry out parallel computing, each GPU completes matrix inverse-co-multiplication computing, and due to the adoption of the joint parallel computing of the CPU and the GPU and the parallel computing on the subcarrier granularity, the maximum parallel C multiplied by Nc (cell in the system is C, subcarrier number NC) paths can be realized.
For the signal-to-interference-and-noise ratio calculation of a large-scale MIMO system, vector multiplication is mainly used, the calculation amount is much smaller than that of a channel calculation module and a transmitting terminal precoding module, and therefore a CPU in a high-performance general processor can be adopted for acceleration, and a good effect can be obtained.
Optionally, the USRP 130 is configured to:
and sending the acquired antenna data to a sub PCIe chassis connected with the USRP through a Common Public Radio Interface (CPRI) protocol.
Optionally, the sub-PCIe chassis is configured to:
and sending the collected antenna data to a main PCIe chassis connected with the antenna data through a CPRI protocol.
Optionally, the primary PCIe chassis is configured to:
and sending the collected antenna data to a high-performance general-purpose processor connected with the antenna data through a CPRI protocol.
The main PCIe chassis is connected with the high-performance general-purpose processor through a PCIe slot provided by the high-performance general-purpose processor.
Optionally, an Open Air Interface (OAI) platform is built in the high-performance general processor 110, and the OAI platform is configured to process the received antenna data to obtain a processed baseband signal.
Among them, the OAI platform is an open source software project initiated by the french Eurecom organization, which provides the first protocol stack in the world for implementing the complete 3GPP in software, and is also one of the more perfect open source software defined radio communication methods at present. The OAI platform can completely realize the functions of a core network, a base station and a user of an LTE protocol, and can realize the simulation test of a large-scale MIMO system by combining a high-performance general processor and a USRP.
Optionally, the PCIe chassis 120 includes a plurality of main PCIe chassis and a plurality of sub PCIe chassis, one main PCIe chassis is connected to the 4 sub PCIe chassis, and one sub PCIe chassis is connected to at most 16 USRPs.
As shown in fig. 1, the PCIe chassis may include 2 main PCIe chassis and 8 sub PCIe chassis, one main PCIe chassis may be connected to 4 sub PCIe chassis, one sub PCIe chassis may be connected to 16 USRPs, and one USRP may include two antenna arrays. The main PCIe1 case and the main PCIe2 case are connected with the high-performance general-purpose processor through PCIe slots provided by the high-performance general-purpose processor. The main PCIe1 chassis is connected with the sub PCIe1 chassis to the sub PCIe4 chassis, and the main PCIe2 chassis is connected with the sub PCIe5 chassis to the sub PCIe8 chassis. The sub PCIe1 chassis is connected to USRP 2X 2(1) -USRP 2X 2(16), … …, and the sub PCIe8 chassis is connected to USRP 2X 2(113) -USRP 2X 2 (128). Each USRP includes two antenna arrays.
Optionally, in practical applications, the number of sub PCIe chassis connected to the plurality of main PCIe chassis is consistent; alternatively, the first and second electrodes may be,
the number of sub-PCIe chassis connected to the plurality of main PCIe chassis is not consistent.
Optionally, the high-performance general-purpose processor is connected to the plurality of main PCIe chassis through PCIe standard interfaces.
Optionally, one sub-PCIe chassis is connected to a maximum of 16 USRPs via optical fibers.
In the data transmission process of a Time Division Duplex (TDD) massive MIMO system, first, a user transmits a pilot sequence and data information on an uplink; then, the base station performs uplink channel estimation and demodulates uplink data by using the received pilot information and the locally stored pilot sequence, and performs downlink pilot transmission and data transmission by using the calculated downlink precoding matrix.
Fig. 2 is a schematic diagram of a data processing flow of an uplink in a simulation test system of a massive MIMO system according to an embodiment of the present invention. In fig. 2, for an uplink, received data is firstly converged to an antenna combining module, and then the received data is transmitted to a bandwidth splitting module by the antenna combining module to split the data, specifically, a bandwidth of the received data may be allocated to a subsystem corresponding to the bandwidth of the received data, a channel estimation module of each subsystem performs channel estimation according to the received data from the bandwidth splitting module, and transmits estimated channel information to an MIMO detection module for user data detection.
At a transmitting end, if a pilot symbol is currently transmitted, a user can generate a pilot by using a locally generated pilot sequence, insert the pilot into a time-frequency resource grid according to a determined pilot insertion mode, change a baseband signal into a radio-frequency signal by using modules such as OFDM modulation, up-conversion, DAC and the like, and finally transmit the radio-frequency signal to a wireless channel through an antenna. If the current transmitted data symbol is a data symbol, the information bit stream which needs to be transmitted by the user is firstly modulated by an M-QAM modulation module, then subjected to resource mapping, OFDM modulation, up-conversion and DAC, and finally transmitted into a channel through a radio frequency antenna.
At a receiving end, a base station firstly acquires radio frequency signals through an ADC (analog to digital converter), performs digital down-conversion and OFDM (orthogonal frequency division multiplexing) demodulation on the acquired radio frequency signals, then selects a corresponding channel estimation algorithm to perform channel estimation, and detects transmitted data through a channel equalization module and QAM (quadrature amplitude modulation) demodulation.
Fig. 3 is a schematic diagram of a data processing flow of a downlink in a simulation test system of a massive MIMO system according to an embodiment of the present invention. In fig. 3, for a downlink, data to be transmitted is first transmitted to the MIMO precoding module by the controller, the MIMO precoding module precodes the data according to information of the channel estimation module and the radio frequency channel calibration module, and then transmits the precoded data to the bandwidth combining module to combine bandwidth data processed by other subsystems to form whole bandwidth data, and finally the whole bandwidth data is transmitted to the antenna splitting module to realize that the data to be transmitted is allocated to each actual physical antenna to be transmitted.
At a sending end, data bit streams generated by a base station and used for being sent to a plurality of users are firstly modulated by a QAM modulation module, then modulated symbols are pre-coded according to an estimated uplink channel and channel reciprocity, then OFDM modulation and radio frequency channel calibration are carried out on the pre-coded symbols, the corrected data are sent to each radio frequency channel for up-conversion, and finally the data are sent out through an antenna.
At a receiving end, a user converts acquired radio frequency signals into baseband signals through ADC and down conversion, OFDM demodulation is carried out on the acquired baseband signals, then a received pilot signal and a locally stored pilot sequence are utilized to estimate a downlink channel, and finally, a current user carries out equalization and interference elimination on data based on the acquired downlink channel information (due to the fact that a space division multiple access mode is adopted, the transmission of downlink data faces to multiple users, and the multiple users share the same time-frequency resource, signals of other users can cause interference on the signals of the current user) to restore data signals sent by a base station end.
The simulation test system of the large-scale MIMO system provided by the embodiment of the invention comprises a universal software radio peripheral equipment USRP, a high-speed serial computer expansion bus standard PCIe chassis and a high-performance universal processor, wherein: the PCIe chassis comprises a plurality of main PCIe chassis and a plurality of sub-PCIe chassis, one main PCIe chassis is connected with the plurality of sub-PCIe chassis, and one sub-PCIe chassis is connected with the plurality of USRPs; the USRP is used for acquiring antenna data and sending the acquired antenna data to a sub PCIe chassis connected with the USRP; the sub PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the main PCIe chassis connected with the sub PCIe chassis; the main PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the high-performance general processor connected with the main PCIe chassis, so that the high-performance general processor processes the received antenna data to obtain a processed baseband signal. Because the sub PCIe chassis can be connected with the USRPs and the main PCIe chassis is connected with the sub PCIe chassis, the connection of the USRPs is expanded, and the problem of the connection of the large-scale USRPs aiming at the large-scale MIMO system is solved. In addition, a large amount of gathered antenna data is processed through the high-performance general processor, and the data processing efficiency of the system is improved.
In short, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
Claims (9)
1. A simulation test system of a large-scale MIMO system is characterized by comprising a Universal Software Radio Peripheral (USRP), a high-speed serial computer expansion bus standard PCIe cabinet and a high-performance general processor, wherein:
the PCIe chassis comprises a plurality of main PCIe chassis and a plurality of sub-PCIe chassis, wherein one main PCIe chassis is connected with the plurality of sub-PCIe chassis, and one sub-PCIe chassis is connected with the plurality of USRPs;
the USRP is used for acquiring antenna data and sending the acquired antenna data to a sub PCIe chassis connected with the USRP;
the sub PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to the main PCIe chassis connected with the sub PCIe chassis;
the main PCIe chassis is used for collecting the received antenna data and sending the collected antenna data to a high-performance general processor connected with the main PCIe chassis, so that the high-performance general processor processes the received antenna data to obtain a processed baseband signal.
2. The system of claim 1, wherein the USRP is to:
and sending the acquired antenna data to a sub PCIe case connected with the USRP through a common public radio interface CPRI protocol.
3. The system of claim 1, wherein the child PCIe chassis is to:
and sending the collected antenna data to a main PCIe chassis connected with the antenna data through a CPRI protocol.
4. The system of claim 1, wherein the primary PCIe chassis is to:
and sending the collected antenna data to a high-performance general-purpose processor connected with the antenna data through a CPRI protocol.
5. The system of claim 1, wherein the high performance general purpose processor has built therein an open air interface OAI platform for processing the received antenna data to obtain processed baseband signals.
6. The system of claim 1, wherein the PCIe chassis comprises a plurality of main PCIe chassis and a plurality of sub PCIe chassis, one main PCIe chassis connected to 4 sub PCIe chassis and one sub PCIe chassis connected to up to 16 USRPs.
7. The system of claim 6, wherein a number of sub-PCIe chassis connected to the plurality of main PCIe chassis is consistent; or
The number of sub-PCIe chassis connected to the plurality of main PCIe chassis is not consistent.
8. The system of claim 6, wherein the high-performance general purpose processor and the plurality of host PCIe chassis are connected through a PCIe standard interface.
9. The system of claim 6, wherein one sub-PCIe chassis is fiber connected with up to 16 USRPs.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2021/116660 WO2022213539A1 (en) | 2021-03-30 | 2021-09-06 | Simulation test system of large-scale mimo system |
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| CN202110339752 | 2021-03-30 | ||
| CN2021103397520 | 2021-03-30 |
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| WO2022213539A1 (en) * | 2021-03-30 | 2022-10-13 | 清华大学 | Simulation test system of large-scale mimo system |
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