CN113131901A

CN113131901A - Relaxation oscillator

Info

Publication number: CN113131901A
Application number: CN201911415382.3A
Authority: CN
Inventors: 刘菁
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2021-07-16
Anticipated expiration: 2039-12-31
Also published as: CN113131901B

Abstract

The invention discloses a relaxation oscillator, which comprises a ramp voltage generating circuit, a comparison circuit and a logic circuit, wherein the comparison circuit comprises a first input branch, a second input branch, a third input branch, a fourth input branch, a fifth input branch, a sixth input branch and a sixth input branch, the first input branch, the second input branch and the third input branch are respectively used for receiving a first ramp voltage, a second ramp voltage and a reference voltage, the first input branch and the second input branch jump based on a ramp voltage switching signal, a transient overlapping region between the ramp voltage switching signals does not influence the frequency and the phase, compared with the prior art, the relaxation oscillator provided by the embodiment of the invention can provide a clock signal which is relatively stable relative to temperature and time, and has the advantages of quick start, high power supply rejection, low power consumption or low noise/jitter and the like.

Description

Relaxation oscillator

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a relaxation oscillator.

Background

Relaxation oscillators are a common circuit in modern electronic systems, which are widely used in electronic systems such as radio, telecommunications, computers, etc. for generating a frequency-stable clock signal, which is then divided and supplied to other synchronous circuits. Relaxation oscillators typically include a resistance-capacitance (RC) circuit through which a capacitor is charged and discharged to generate a clock signal, the frequency of which is changed by changing the time constant of the RC circuit.

Fig. 1 shows a circuit schematic of a conventional relaxation oscillator 100. As shown in fig. 1, relaxation oscillator 100 includes a ramp voltage generation circuit 110, a comparator 120, and a logic circuit 130.

The ramp voltage generating circuit 110 includes

current sources

111 and 112, capacitors C1 and C2, and switches SW1 to SW 6. The current source 111, the switch SW3, and the capacitor C1 are sequentially connected in series between the power supply voltage and ground, the switch SW4 has a first terminal connected to the intermediate node between the capacitor C1 and the switch SW3, and a second terminal connected to ground. When the switch SW3 is closed and the switch SW4 is opened, the current source 111 charges the capacitor C1, and the first ramp voltage VL1 starts to increase. When the switch SW3 is turned off and the switch SW4 is turned on, the capacitor C1 discharges to the ground, and the first ramp voltage VL1 gradually decreases.

The current source 112, the switch SW5, and the capacitor C2 are sequentially connected in series between the power supply voltage and ground, the switch SW6 has a first terminal connected to the intermediate node between the capacitor C2 and the switch SW5, and a second terminal connected to ground. When the switch SW5 is closed and the switch SW6 is opened, the current source 112 charges the capacitor C2, and the second ramp voltage VL2 starts to increase. When the switch SW5 is turned off and the switch SW6 is turned on, the capacitor C2 discharges to the ground, and the second ramp voltage VL2 gradually decreases.

First terminals of the switch SW1 and the switch SW2 are connected to an inverting input terminal of the comparator 120, a second terminal of the switch SW1 is connected to an intermediate node of the switch SW3 and the capacitor C1, and a second terminal of the switch SW2 is connected to an intermediate node of the switch SW5 and the capacitor C2. The switch SW1 and the switch SW2 supply the first ramp voltage VL1 and the second ramp voltage VL2, respectively, to the inverting input terminal of the comparator 120 when closed.

The non-inverting input terminal of the comparator 120 is configured to receive a reference voltage Vref, the output terminal of the comparator 120 is connected to the input terminal of the logic circuit 130, the output terminal of the logic circuit 130 is configured to output the clock signal CLK and the first and second switching signals S1 and S2, the first switching signal S1 is configured to control the switches SW1, SW3 and SW6 in the ramp voltage generating circuit 110, and the second switching signal S2 is configured to control the switches SW2, SW4 and SW5 in the ramp voltage generating circuit 110.

The prior art relaxation oscillator has the following problems: in order to ensure the output stability of the circuit, the switch SW1 and the switch SW2 in the ramp voltage generation circuit 110 must not be turned on simultaneously, so the first switching signal S1 and the second switching signal S2 must be non-overlapping signals, and a non-overlapping region must exist between the first switching signal S1 and the second switching signal S2, and the non-overlapping region may change with the change of process corner, temperature, power supply voltage, etc., and then affect the frequency of the output clock signal, which is particularly obvious in a high frequency circuit.

Another problem with existing relaxation oscillators is that: the switches SW1 and SW2 in the ramp voltage generation circuit 110 may have a problem of charge leakage when being closed, and the leaked charge may enter the capacitor C1 and the capacitor C2, thereby affecting the values of the first ramp voltage VL1 and the second ramp voltage VL2, and affecting the accuracy of the output clock signal.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a relaxation oscillator that can eliminate an offset error caused by an overlap between switching signals and provide a high frequency clock signal that is stable with respect to temperature and time.

According to an embodiment of the present invention, there is provided a relaxation oscillator including: a ramp voltage generating circuit for generating a first ramp voltage and/or a second ramp voltage according to a ramp voltage switching signal; and a comparison circuit including a first input branch for receiving the first ramp voltage, a second input branch for receiving the second ramp voltage, and a third input branch for receiving a reference voltage, the comparison circuit for comparing the first ramp voltage or the second ramp voltage with a reference voltage to generate a comparison signal, the first input branch and the second input branch jumping based on the ramp voltage switching signal; the logic circuit is coupled to the output end of the comparison circuit and is used for generating the ramp voltage switching signal and a clock signal according to the comparison signal, wherein the ramp voltage switching signal comprises a first switching signal and a second switching signal which are opposite phase signals allowing overlapping.

Preferably, the comparison circuit further comprises: a first resistor coupled to the first input branch and the second input branch for generating a first input voltage based on a first on-current provided by the first input branch and/or a second on-current provided by the second input branch; a second resistor coupled to the third input branch for generating a second input voltage based on a third on-current provided by the third input branch; and a comparator having an inverting input coupled to the first resistor to receive the first input voltage, a non-inverting input coupled to the second resistor to receive the second input voltage, and an output for outputting the comparison signal.

Preferably, the comparison circuit further comprises: a reference current source coupled to the first through third input branches for providing a reference current to the first through third input branches.

Preferably, the ramp voltage generation circuit includes: a first current branch providing the first ramp voltage in response to a first logic state of the first switching signal and a second logic state of the second switching signal; a second current branch providing the second ramp voltage in response to a second logic state of the first switching signal and a first logic state of the second switching signal.

Preferably, the relaxation oscillator further comprises: the reference circuit is used for generating a reference voltage; and an error integration circuit for generating the reference voltage from the first ramp voltage and the reference voltage, or generating the reference voltage from the second ramp voltage and the reference voltage.

Preferably, the first current branch includes: a first current source; a first switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to the first current source, and a second terminal; a first capacitor having a first plate coupled to a second terminal of the first switch and a second plate coupled to ground; a second switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to ground, wherein an intermediate node of the first capacitor and the first switch is used to provide the first ramp voltage.

Preferably, the second current branch comprises: a second current source; a third switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to the second current source, and a second terminal; a second capacitor having a first plate coupled to the second terminal of the third switch and a second plate coupled to ground; a fourth switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to the second terminal of the third switch, and a second terminal coupled to ground, wherein the second capacitance and an intermediate node of the third switch are used to provide the second ramp voltage.

Preferably, the first input branch comprises: a first transistor having a control terminal coupled to the first output terminal to receive the first ramp voltage, a first terminal coupled to the reference current source, and a second terminal; and a fifth switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first terminal of the first resistance.

Preferably, the second input branch comprises: a second transistor having a control terminal coupled to the second output terminal to receive the second ramp voltage, a first terminal coupled to the reference current source, and a second terminal; and a sixth switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to the second terminal of the second transistor, and a second terminal coupled to the first terminal of the first resistor.

Preferably, the third input branch comprises: a third transistor having a control terminal coupled to receive the reference voltage, a first terminal coupled to the reference current source, and a second terminal coupled to the second resistance.

The relaxation oscillator of the embodiment of the invention comprises a ramp voltage generating circuit and a switching control circuit, wherein the switching control circuit comprises a comparison circuit and a logic circuit, the comparison circuit comprises a first input branch, a second input branch, a third input branch, a reference branch and a logic circuit, the first input branch, the second input branch and the reference branch are respectively used for receiving a first ramp voltage, a second ramp voltage and a reference voltage, the comparison circuit is used for comparing the first ramp voltage or the second ramp voltage with the reference voltage to generate a comparison signal, the logic circuit is used for generating a ramp voltage switching signal and a clock signal according to the comparison signal, and the first input branch and the second input branch jump based on the ramp voltage switching signal. In the embodiment of the present invention, the short overlapping region between the ramp voltage switching signals does not affect the frequency and the phase of the clock signal, so the ramp voltage switching signals in the relaxation oscillator of the embodiment of the present invention do not need to be non-overlapping clocks, and there is no overlapping offset error. Compared with the prior art, the relaxation oscillator provided by the embodiment of the invention can provide a clock signal which is relatively stable relative to temperature and time, and has the advantages of quick start, high power supply rejection, low power consumption or low noise/jitter and the like.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 shows a circuit schematic of a conventional relaxation oscillator;

FIG. 2 shows a circuit schematic of a relaxation oscillator according to a first embodiment of the invention;

FIG. 3 shows a circuit schematic of the comparison circuit of FIG. 2;

FIG. 4 shows a circuit schematic of a relaxation oscillator according to a second embodiment of the invention;

fig. 5 shows an operation timing chart of the relaxation oscillator according to the first embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected" or "coupled" to another element, or being "connected" or "coupled" between two nodes, it may be directly coupled or connected to the other element or intervening elements may also be present, and the connection or coupling between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Fig. 2 shows a circuit schematic of a relaxation oscillator according to a first embodiment of the invention. As shown in fig. 2, relaxation oscillator 200 includes a ramp voltage generation circuit 210 and a switching control circuit 220.

The ramp voltage generating circuit 210 includes a first output terminal 211 and a second output terminal 212. The ramp voltage generating circuit 210 is configured to output the first ramp voltage VL1 from the first output terminal 211 in response to a first logic state of the first switching signal S1 and a second logic state of the second switching signal S2. The ramp voltage generating circuit 210 is further configured to output the second ramp voltage VL2 from the second output terminal 212 in response to the second logic state of the first switching signal S1 and the first logic state of the second switching signal S2.

In the present embodiment, the ramp voltage generating circuit 210 includes a first current branch coupled to the first output terminal 211. The first current branch is coupled to the first output terminal 211, the first current branch being coupled to receive the first switching signal S1 and the second switching signal S2. In response to the first logic state of the first switching signal S1 and the second logic state of the second switching signal S2, the first current branch generates the first ramp voltage VL1 according to the first current I1, and the voltage value of the first ramp voltage VL1 increases with time. When the logic state of the first switching signal S1 switches from the first logic state to the second logic state and the logic state of the second switching signal S2 switches from the second logic state to the first logic state, the first current branch discharges the first ramp voltage VL 1.

In this embodiment, the first current branch includes a current source 213, a switch SW1, a switch SW2, and a capacitor C1. The current source 213 is for generating the first current I1, and the switch SW1 has a control terminal coupled (or connected) to receive the first switching signal S1, a first terminal coupled to the current source 213, and a second terminal. The switch SW2 has a control terminal coupled (or connected) to receive the second switching signal S2, a first terminal coupled to the second terminal of the first switch SW1, and a second terminal coupled to ground. A capacitor C1 has a first plate coupled to the second terminal of switch SW1 and a second plate coupled to ground, and the intermediate node of capacitor C1 and switch SW1 is coupled to the first output terminal 211.

The ramp voltage generating circuit 210 further includes a second current branch coupled to the second output terminal 212, the second current branch being coupled to receive the first switching signal S1 and the second switching signal S2. In response to the second logic state of the first switching signal S1 and the first logic state of the second switching signal S2, the second current branch generates the second ramp voltage VL2 according to the second current I2, and the voltage value of the second ramp voltage VL2 increases with time. When the logic state of the first switching signal S1 is switched from the second logic state to the first logic state and the logic state of the second switching signal S2 is switched from the first logic state to the second logic state, the second current branch discharges the second ramp voltage VL 2.

In this embodiment, the second current branch includes a current source 214, a switch SW3, a switch SW4, and a capacitor C2. The current source 214 is used for generating a second current I2, and the switch SW3 has a control terminal coupled (or connected) to receive the second switching signal S2, a first terminal coupled to the current source 214, and a second terminal. The switch SW4 has a control terminal coupled (or connected) to receive the first switching signal S1, a first terminal coupled to the second terminal of the third switch SW3, and a second terminal coupled to ground. A capacitor C2 has a first plate coupled to the second terminal of switch SW3 and a second plate coupled to ground, the intermediate node of capacitor C2 and switch SW3 being coupled to the second output 212.

The switching control circuit 220 is coupled to the first output terminal 211 and the second output terminal 212 of the ramp voltage generating circuit 210. The switching control circuit 220 is used for receiving a plurality of voltages and generating a first switching signal S1, a second switching signal S2 and a clock signal CLK in response to the plurality of voltages. The plurality of voltages includes a first ramp voltage VL1, a second ramp voltage VL2, and a reference voltage Vref. In this embodiment, the reference voltage Vref may be used to set target values to which the capacitor C1 and the capacitor C2 are charged.

The switching control circuit 220 is configured to compare the first ramp voltage VL1 with the reference voltage Vref in the first logic state of the first switching signal S1 and the second logic state of the second switching signal S2, and to change the logic states of the first switching signal S1 and the second switching signal S2 when the first ramp voltage VL1 exceeds the reference voltage Vref as time increases.

Next, the switching control circuit 220 compares the second ramp voltage VL2 with the reference voltage Vref, and changes the logic states of the first switching signal S1 and the second switching signal S2 when the second ramp voltage VL2 exceeds the reference voltage Vref with an increase in time.

In this embodiment, the switching control circuit 220 includes a comparison circuit 221 and a logic circuit 223. The comparing circuit 221 is configured to compare the first ramp voltage VL1 or the second ramp voltage VL2 with the reference voltage Vref to generate a comparison signal V1. The logic circuit is used for generating the first switching signal S1, the second switching signal S2 and the clock signal CLK according to the comparison signal V1.

In this embodiment, both capacitance C1 and capacitance C2 may comprise composite capacitors that may include or consist of capacitors or sub-capacitors having different temperature coefficients, such as composite capacitors where the temperature coefficients may cancel each other to provide a more stable capacitance value, or a more temperature stable resistor-capacitor product.

Fig. 3 shows a circuit schematic of the comparison circuit of fig. 2. As shown in fig. 3, the comparison circuit 221 includes a reference current source 2211, a first input branch 2212, a second input branch 2213, a third input branch 2214, resistors R1 and R2, and a comparator 2215. The reference current source 2211 is used to generate a reference current. The first input branch 2212 is coupled to the reference current source 2211 for providing a first on-current Ip1 in response to the first ramp voltage VL1 and a first logic state of the first switching signal S1. The second input branch 2213 is coupled to the reference current source 2211 for providing a second on-current Ip2 in response to the second ramp voltage VL2 and the first logic state of the second switching signal S2. The third input branch 2214 is coupled to the reference current source 2211 for providing a third on-current Ip3 in response to the reference voltage Vref. The resistor R1 is coupled to the first and

second input branches

2212 and 2213 for generating the first input voltage Von according to the first and/or second on-currents Ip1 and Ip 2. The resistor R2 is coupled to the second input branch 2214 for generating the second input voltage Vop according to the third on-current Ip 3. The comparator 2215 has an inverting input coupled to the first terminal of the resistor R1 to receive the first input voltage Von, a non-inverting input coupled to the first terminal of the resistor R2 to receive the second input voltage Vop, and an output for outputting the comparison signal V1.

First input branch 2212, second input branch 2213, and third input branch 2214 may be implemented in a number of different ways to generate corresponding currents in response to the voltages shown in fig. 2.

In this embodiment, the first input branch 2212 includes a transistor M1 and a switch SW 5. The transistor M1 has a control terminal coupled to the first output terminal 211 of the ramp voltage generating circuit 210 to receive the first ramp voltage VL1, a first terminal coupled to the reference current source 2211, and a second terminal. The switch SW5 has a control terminal coupled to receive the first switching signal S1, a first terminal coupled to the second terminal of the transistor M1, and a second terminal coupled to a first terminal of a resistor R1, the second terminal of the resistor R1 being coupled to ground.

The second input branch 2213 includes a transistor M2 and a switch SW 6. The transistor M2 has a control terminal coupled to the second output terminal 212 of the ramp voltage generating circuit 210 to receive the second ramp voltage VL2, a first terminal coupled to the current source 2211, and a second terminal. The switch SW6 has a control terminal coupled to receive the second switching signal S2, a first terminal coupled to the second terminal of the transistor M2, and a second terminal coupled to the first terminal of the resistor R1.

The third input branch 2214 includes a transistor M3, a transistor M3 having a control terminal coupled to receive a reference voltage Vref, a first terminal coupled to a current source 2211, and a second terminal coupled to a first terminal of a resistor R2, a second terminal of the resistor R2 being coupled to ground.

In the present embodiment, the switches SW1-SW6 may be implemented in several ways. In one embodiment, switches SW1-SW6 may be implemented as transistors, such as NMOS transistors. When an NMOS transistor is used, the control terminal is a gate, the first terminal is a drain, and the second terminal is a source. In addition, the transistors M1 and M2 may also be implemented in several ways. In one embodiment, the transistors M1 and M21 may be implemented as transistors, such as PMOS transistors. When a PMOS transistor is used, the control terminal is a gate, the first terminal is a source, and the second terminal is a drain.

In addition, the "resistance" mentioned in the above embodiments may be a single physical resistor or a resistance element, or may be a combination of a plurality of physical resistors or resistance elements. In other words, the relaxation oscillator shown in the present invention is applicable to various types of impedance elements, each impedance element having an impedance corresponding to a required resistance. Thus, reference herein to "resistance" is further to any number of different types of resistive elements according to circuit layout, such as precision thin film resistors formed of SiCr or other material, or in the case of integrated circuits, polysilicon (doped p-or n-). It will also be appreciated that a "resistor" as described herein may include any circuit element (e.g., an NMOS transistor, etc.) that may generate a voltage across its terminals that is proportional to the current through it.

Fig. 4 shows a circuit schematic of a relaxation oscillator according to a second embodiment of the invention. The relaxation oscillator 300 of the present embodiment differs from the relaxation oscillator 200 of the first embodiment only in that: relaxation oscillator 300 also includes a reference circuit 330 and an error integration circuit 340. Except for this, the ramp voltage generation circuit 310 and the switching control circuit 320 in the relaxation oscillator 300 are identical to the ramp voltage generation circuit 210 and the switching control circuit 220 in the relaxation oscillator 200 of the first embodiment, and are not described again here.

As shown in fig. 4, the reference circuit 330 is configured to generate a reference voltage Vbg, and the error integration circuit 340 is configured to generate the reference voltage Vref according to the first ramp voltage VL1 or the second ramp voltage VL2 and the reference voltage Vbg, and adjust the reference voltage Vref according to an error between the first ramp voltage VL1 or the second ramp voltage VL2 and the reference voltage Vbg, and feed the adjusted reference voltage Vref to an inverting input terminal of the comparison circuit in the switching control circuit 320.

The error integration circuit 340 is to reduce the influence of input offset in the comparison circuit and the influence of delay in the comparison circuit and/or the logic circuit, and to improve the output accuracy of the switching control circuit.

Fig. 5 shows an operation timing chart of the relaxation oscillator 200 according to the first embodiment of the present invention. The operation of the relaxation oscillator 200 according to the first embodiment of the present invention will be described in detail with reference to fig. 2, 3 and 5.

A timing chart of voltages of the first ramp voltage VL1 and the second ramp voltage VL2, a timing chart of the first switching signal S1 and the second switching signal S2, and a timing chart of the comparison signal V1 are shown in fig. 5.

As shown in fig. 5, the second switching signal S2 is an inverted signal (or inverse signal) of the first switching signal S1. The first switching signal S1 has a falling edge substantially synchronized with the first falling edge of the comparison signal V1 and a rising edge substantially synchronized with the second falling edge of the comparison signal V1.

In further illustration of fig. 5, at time t0, the switching control circuit 220 outputs a first switching signal S1 having a logic high and a second switching signal S2 having a logic low.

In the relaxation oscillator 200 and the comparison circuit 221 of fig. 2 and 3, when the first switching signal S1 has a logic high state and the second switching signal S2 has a logic low state, the switches SW1, SW4 and SW5 are closed, and the switches SW2, SW3 and SW6 are opened.

In this state, the capacitor C2 is discharged through the switch SW4 while the first current I1 from the current source 213 flows through the switch SW1 to the capacitor C1, wherein the first current I1 is used to charge the capacitor C1 to generate the first ramp voltage VL 1. As shown in fig. 4, the voltage of the first ramp voltage VL1 gradually increases over a time period t0-t 1. Meanwhile, the reference current from the reference current source 2211 flows to the resistor R1 through the transistor M1 and the switch SW5, the first on-current Ip1 is provided at the first terminal of the resistor R1, and the resistor R1 generates the first input voltage Von according to the first on-current Ip 1. As the first ramp voltage VL1 increases, the on-resistance of the transistor M1 gradually increases, the first on-current Ip1 gradually decreases, and the first input voltage Von gradually decreases. At time t1, the first ramp voltage VL1 exceeds the reference voltage Vref, and the first input voltage Von is less than the second input voltage Vop, and the comparator 2215 outputs a pulse signal.

At time t2, the logic circuit 223 is, for example, falling edge triggered, switches the logic states of the first switching signal S1 and the second switching signal S2 according to the falling edge of the pulse signal output by the comparator 2215, changes the logic state of the first switching signal S1 from logic high to logic low, and changes the logic state of the second switching signal S2 from logic low to logic high.

To ensure the smoothness of the logic states of the first switching signal S1 and the second switching signal S2 (i.e., the comparator 2215 does not generate a transition of the output signal due to noise), the comparator 2215 of the present embodiment may select a hysteresis comparator. An ideal comparator will oscillate between high and low levels if the voltages at the two inputs are equal. The hysteresis comparator can avoid the output oscillation of the comparator under the condition, and the hysteresis comparator maintains the original state under the condition that the voltages of the two input ends are equal, and the output of the comparator can not be overturned until the voltages of the two input ends are different by delta V.

With continued reference to fig. 2 and 3, when the first switching signal S1 has a logic low state and the second switching signal S2 has a logic high state, the switches SW1, SW4 and SW5 are open and the switches SW2, SW3 and SW6 are closed.

In this state, the capacitor C1 is discharged through the switch SW2 while the second current I2 from the current source 214 flows through the switch SW3 to the capacitor C2, wherein the second current I2 is used to charge the capacitor C2 to generate the second ramp voltage VL 2. As shown in fig. 4, the voltage of the second ramp voltage VL2 gradually increases over the time period t2-t 3. Meanwhile, the reference current from the reference current source 2211 flows to the resistor R1 through the transistor M2 and the switch SW6, the second on-current Ip2 is provided at the first terminal of the resistor R1, and the resistor R1 generates the first input voltage Von according to the second on-current Ip 2. As the second ramp voltage VL2 increases, the on-resistance of the transistor M2 gradually increases, the second on-current Ip2 gradually decreases, and the first input voltage Von gradually decreases.

Further, the first switching signal S1 and the second switching signal S2 in this embodiment are mutually opposite signals (e.g., the second switching signal S2 is directly obtained from the first switching signal S1 through an inverter), and there is no need to intentionally process the two signals into non-overlapping signals, so that an overlapping region of the first switching signal S1 and the second switching signal S2 is necessarily present in the time period t2-t3 (e.g., the first switching signal S1 and the second switching signal S2 are both logic high in a time period after the time t2, which is not shown in fig. 4). Switch SW6 is closed in the overlap region and switch SW5 is not fully open. As can be seen from the foregoing, the first ramp voltage VL1 is greater than the reference voltage Vref, and the second ramp voltage VL2 is much smaller than the reference voltage Vref, so that the first ramp voltage VL1 is much larger than the second ramp voltage VL 2. Since the transistors M1 and M2 are PMOS transistors, the second on-current Ip2 is greater than the first on-current Ip1, and the first input voltage Von is mainly determined by the second on-current Ip2, the comparison signal V1 outputted by the comparator 2215 maintains the previous low state, and then the comparison signal V1 continues to maintain the low state when the switch SW5 is completely turned off. Therefore, in the present embodiment, the short overlapping region between the first switching signal S1 and the second switching signal S2 does not have any influence on the waveform of the comparison signal V1 outputted by the comparator 2215.

In summary, all control signals of the relaxation oscillator according to the embodiment of the present invention do not need non-overlap clocks, so that there is no overlap offset error, and therefore, a clock signal relatively stable with respect to temperature and process angle can be provided, and the relaxation oscillator has the advantages of fast start, high power supply rejection, low power consumption, or low noise/jitter.

In addition, the relaxation oscillator of the embodiment does not need to be provided with a switch between the ramp voltage generation circuit and the comparison circuit, solves the problem of charge leakage caused by the switch closure, improves the precision of the clock signal, and can provide an accurate and stable high-frequency clock signal for the crystal oscillation circuit in wide application.

Referring again to fig. 4, at time t3, the second ramp voltage VL2 exceeds the reference voltage Vref, and the first input voltage Von again exceeds the second input voltage Vop, and the comparator 2215 also outputs a pulse signal.

At time t4, the logic circuit 223 switches the logic states of the first switching signal S1 and the second switching signal S2 in accordance with the falling edge of the pulse signal output by the comparator 2215, changes the logic state of the second switching signal S2 from logic high to logic low, and changes the logic state of the first switching signal S1 from logic low to logic high, and the above-described process is repeated.

In the present embodiment, the structure of the logic circuit is conventional in the art, and can be implemented in several different ways to generate the first switching signal S1 and the second switching signal S2 and the clock signal CLK, which are opposite in phase, in response to the comparison signal V1. For example, in one embodiment, the logic circuit may include an RS flip-flop, an inverter, a frequency divider, and so on.

In summary, the relaxation oscillator according to the embodiment of the present invention includes a ramp voltage generation circuit and a switching control circuit, where the switching control circuit includes a comparison circuit and a logic circuit, the comparison circuit includes first to third input branches respectively receiving a first ramp voltage, a second ramp voltage and a reference voltage, the comparison circuit is configured to compare the first ramp voltage or the second ramp voltage with the reference voltage to generate a comparison signal, the logic circuit is configured to generate a ramp voltage switching signal and a clock signal according to the comparison signal, and the first input branch and the second input branch jump based on the ramp voltage switching signal. In the embodiment of the present invention, the short overlapping region between the ramp voltage switching signals does not affect the frequency and the phase of the clock signal, so the ramp voltage switching signals in the relaxation oscillator of the embodiment of the present invention do not need to be non-overlapping clocks, and there is no overlapping offset error. Compared with the prior art, the relaxation oscillator provided by the embodiment of the invention can provide a clock signal which is relatively stable relative to temperature and time, and has the advantages of quick start, high power supply rejection, low power consumption or low noise/jitter and the like.

Furthermore, the relaxation oscillator of the embodiment of the invention further comprises a reference circuit and an error integrating circuit, so that the influence of input offset in the comparison circuit and the influence of delay in the comparison circuit and/or the logic circuit can be supplemented and reduced, and the output precision of the switching control circuit can be improved.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A relaxation oscillator comprising:

a ramp voltage generating circuit for generating a first ramp voltage and/or a second ramp voltage according to a ramp voltage switching signal; and

a comparison circuit including a first input branch for receiving the first ramp voltage, a second input branch for receiving the second ramp voltage, and a third input branch for receiving a reference voltage,

the comparison circuit is used for comparing the first ramp voltage or the second ramp voltage with a reference voltage to generate a comparison signal, and the first input branch and the second input branch jump based on the ramp voltage switching signal;

a logic circuit coupled to an output of the comparison circuit for generating the ramp voltage switching signal and a clock signal according to the comparison signal,

the ramp voltage switching signal comprises a first switching signal and a second switching signal which are inverted signals allowing overlapping.

2. The relaxation oscillator of claim 1 wherein the comparison circuit further comprises:

a first resistor coupled to the first input branch and the second input branch for generating a first input voltage based on a first on-current provided by the first input branch and/or a second on-current provided by the second input branch;

a second resistor coupled to the third input branch for generating a second input voltage based on a third on-current provided by the third input branch; and

a comparator having an inverting input coupled to the first resistor to receive the first input voltage, a non-inverting input coupled to the second resistor to receive the second input voltage, and an output for outputting the comparison signal.

3. The relaxation oscillator of claim 2 wherein the comparison circuit further comprises:

a reference current source coupled to the first through third input branches for providing a reference current to the first through third input branches.

4. The relaxation oscillator of claim 1 wherein the ramp voltage generation circuit comprises:

a first current branch providing the first ramp voltage in response to a first logic state of the first switching signal and a second logic state of the second switching signal;

a second current branch providing the second ramp voltage in response to a second logic state of the first switching signal and a first logic state of the second switching signal.

5. The relaxation oscillator of claim 1 further comprising:

the reference circuit is used for generating a reference voltage; and

an error integration circuit for generating the reference voltage from the first ramp voltage and the reference voltage, or generating the reference voltage from the second ramp voltage and the reference voltage.

6. The relaxation oscillator of claim 4 wherein the first current branch comprises:

a first current source;

a first switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to the first current source, and a second terminal;

a first capacitor having a first plate coupled to a second terminal of the first switch and a second plate coupled to ground;

a second switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to ground,

wherein an intermediate node between the first capacitor and the first switch is used to provide the first ramp voltage.

7. The relaxation oscillator of claim 4 wherein the second current branch comprises:

a second current source;

a third switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to the second current source, and a second terminal;

a second capacitor having a first plate coupled to the second terminal of the third switch and a second plate coupled to ground;

a fourth switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to a second terminal of the third switch, and a second terminal coupled to ground,

wherein an intermediate node of the third switch and the second capacitor is configured to provide the second ramp voltage.

8. The relaxation oscillator of claim 3 wherein the first input branch comprises:

a first transistor having a control terminal coupled to the first output terminal to receive the first ramp voltage, a first terminal coupled to the reference current source, and a second terminal; and

a fifth switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to a second terminal of the first transistor, and a second terminal coupled to a first terminal of the first resistance.

9. The relaxation oscillator of claim 8 wherein the second input branch comprises:

a second transistor having a control terminal coupled to the second output terminal to receive the second ramp voltage, a first terminal coupled to the reference current source, and a second terminal; and

a sixth switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to a second terminal of the second transistor, and a second terminal coupled to a first terminal of the first resistor.

10. The relaxation oscillator of claim 8 wherein the third input branch comprises:

a third transistor having a control terminal coupled to receive the reference voltage, a first terminal coupled to the reference current source, and a second terminal coupled to the second resistance.