CN113131873A - Self-adaptive feedforward linear power amplifier - Google Patents

Self-adaptive feedforward linear power amplifier Download PDF

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CN113131873A
CN113131873A CN202110269151.7A CN202110269151A CN113131873A CN 113131873 A CN113131873 A CN 113131873A CN 202110269151 A CN202110269151 A CN 202110269151A CN 113131873 A CN113131873 A CN 113131873A
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input end
signal
directional coupler
loop
input
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CN113131873B (en
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潘云龙
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NANJING GUOBO ELECTRONICS CO Ltd
Nanjing Guomicroelectronics Co Ltd
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NANJING GUOBO ELECTRONICS CO Ltd
Nanjing Guomicroelectronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Abstract

The application relates to a self-adaptive feedforward linear power amplifier device. The device includes: the self-adaptive error detection loop based on the simulation minimum mean method and the self-adaptive error cancellation loop based on the simulation minimum mean method; the self-adaptive error detection loop based on the analog minimum mean method and the self-adaptive error cancellation loop based on the analog minimum mean method are used, the self-adaptive state adjusting function of the feed-forward power amplifier can be achieved, the circuit scheme is simple, and the circuit complexity of the power amplifying device is high.

Description

Self-adaptive feedforward linear power amplifier
Technical Field
The application relates to the technical field of integrated circuits, in particular to a self-adaptive feedforward linear power amplifier device.
Background
The radio frequency power amplifier is a core component of a wireless transceiving system. Wireless communication applications typically require that the output signal of the power amplifier has less distortion, i.e. the power amplification system has a higher linearity. To improve the additional efficiency, the linearity of the radio frequency power amplifier is generally poor. Therefore, a plurality of power amplifier linearization techniques are adopted in the wireless communication system, and typical linearization techniques are as follows: predistortion techniques, negative feedback techniques, feed forward techniques, and the like.
Compared with other linearization techniques, the feedforward technique has better performance. The basic principle of the feedforward linearized power amplifier is summarized as follows: firstly, comparing an undistorted signal input by a power amplifier with an output distorted signal by a proper method, and extracting a sample of an error signal generated by a main power amplifier; then, the error signal sample is properly adjusted and then mutually offset with the distortion signal, so as to achieve the effect of eliminating distortion. Therefore, the error signal sample extraction and the error signal cancellation are two most core functional modules of the feedforward power amplifier, and the accuracy of the two functions directly determines the linearity of the feedforward power amplifier.
Generally, when the feed-forward power amplifier works, the working states of the error sample extraction module and the error signal cancellation module need to be adjusted in real time or regularly, so that the effect of error cancellation cannot be influenced by time, temperature change, component parameter drift, emission signal spectrum change and other factors. In order to realize this function, the prior art generally applies some control methods based on digital adaptive algorithm, these control systems often include relatively complex digital control systems, and some auxiliary signals, such as pilot, are introduced, so the circuit complexity of the power amplifying device is high.
Disclosure of Invention
In view of the above, it is desirable to provide an adaptive feedforward linear power amplifier device capable of reducing the circuit complexity of a power amplification system.
An adaptive feedforward linearized power amplifier apparatus, the apparatus comprising: the self-adaptive error detection loop based on the simulation minimum mean method and the self-adaptive error cancellation loop based on the simulation minimum mean method;
the first input end of the self-adaptive error detection loop is connected with the input end of a main power amplifier, the output end of the main power amplifier is respectively connected with the second input end of the self-adaptive error detection loop and the second input end of the self-adaptive error cancellation loop, the output end of the self-adaptive error detection loop is connected with the first input end of the self-adaptive error cancellation loop, and the output end of the self-adaptive error cancellation loop outputs a signal;
the adaptive error detection loop is used for extracting an undistorted signal from the input end of the main power amplifier, extracting a first distorted signal from the output end of the main power amplifier, processing the undistorted signal and the first distorted signal, and outputting an error sample signal to the first input end of the adaptive error cancellation loop;
the self-adaptive error cancellation loop is used for taking the error sample signal and the first distortion signal output by the output end of the main power amplifier as input signals, processing the error sample signal and the first distortion signal, and outputting the error signal after adaptively canceling an error signal component in the first distortion signal.
In one embodiment, the apparatus further comprises: a first delay line;
the first delay line is connected between the output end of the main power amplifier and the second input end of the self-adaptive error cancellation loop.
In one embodiment, the adaptive error detection loop comprises: the first directional coupler, the second directional coupler, the third directional coupler, the first modulator, the first demodulator and the first loop filter bank;
an input end of the first directional coupler is used as a first input end of the adaptive error detection loop, a coupling output end of the first directional coupler is connected with a first input end of the first modulator, a through output end of the first directional coupler is connected with a first input end of the first demodulator, an output end of the first demodulator is connected with an input end of the first loop filter bank, an output end of the first loop filter bank is connected with a second input end of the first modulator, an output end of the first modulator is connected with a first input end of the second directional coupler, a second input end of the second directional coupler is used as a second input end of the adaptive error detection loop and is connected with an output end of the main power amplifier, and an output end of the second directional coupler is connected with an input end of the third directional coupler, and the coupling output end of the third directional coupler is connected with the second input end of the first demodulator, and the through output end of the third directional coupler is used as the output end of the self-adaptive error detection loop.
In one embodiment, the adaptive error detection loop further comprises: a second delay line;
one end of the second delay line is connected with the through output end of the first directional coupler, and the other end of the second delay line is connected with the first input end of the first demodulator.
In one embodiment, the first modulator is formed by at least one quadrature multiplication unit.
In one embodiment, the first demodulator is formed by at least one quadrature multiplication unit.
In one embodiment, the adaptive error cancellation loop comprises: a second demodulator, a second loop filter bank, a second modulator, a linear power amplifier, a fourth directional coupler, a fifth directional coupler, and a sixth directional coupler;
an input end of the fourth directional coupler is used as a first input end of the adaptive error cancellation loop, a coupling output end of the fourth directional coupler is connected with a first input end of the second modulator, an output end of the second modulator is connected with an input end of the linear power amplifier, an output end of the linear power amplifier is connected with a first input end of the fifth directional coupler, a second input end of the fifth directional coupler is used as a second input end of the adaptive error cancellation loop, an output end of the fifth directional coupler is connected with an input end of the sixth directional coupler, a through output end of the sixth directional coupler is used as an output end of the adaptive error cancellation loop, a coupling output end of the sixth directional coupler is connected with a second input end of the second demodulator, and a through output end of the fourth directional coupler is connected with a first input end of the second demodulator, the output of the second demodulator is connected to the input of the second loop filter bank, and the output of the second loop filter bank is connected to the second input of the second modulator.
In one embodiment, the adaptive error cancellation loop further comprises: a fifth delay line;
one end of the fifth delay line is connected with the through output end of the fourth directional coupler, and the other end of the fifth delay line is connected with the first input end of the second demodulator.
In one embodiment, the second modulator is formed by at least one quadrature multiplication unit.
In one embodiment, the second demodulator is formed by at least one quadrature multiplication unit.
The self-adaptive feedforward linear power amplifier device is connected to the input end of a main power amplifier through the first input end of a self-adaptive error detection loop, the output end of the main power amplifier is respectively connected to the second input end of the self-adaptive error detection loop and the second input end of a self-adaptive error cancellation loop, the output end of the self-adaptive error detection loop is connected with the first input end of the self-adaptive error cancellation loop, and the output end of the self-adaptive error cancellation loop outputs a signal; the self-adaptive error detection loop is used for extracting a distortion-free signal from the input end of the main power amplifier, extracting a first distortion signal from the output end of the main power amplifier, processing the distortion-free signal and the first distortion signal, and outputting an error sample signal to the first input end of the self-adaptive error cancellation loop; the self-adaptive error compensation loop is used for processing an error sample signal and a first distortion signal output by the output end of the main power amplifier as input signals, outputting the error sample signal and the first distortion signal after adaptively compensating error signal components in the first distortion signal, and using a self-adaptive error detection loop based on a simulation minimum mean method and a self-adaptive error compensation loop based on the simulation minimum mean method, so that the self-adaptive state adjustment function of the feed-forward power amplifier can be realized, the circuit scheme is simple, and the circuit complexity of the power amplifier is higher.
Drawings
Fig. 1 is a schematic structural diagram of an adaptive feedforward linear power amplifier in an embodiment;
FIG. 2 is a schematic diagram of an adaptive feedforward linear power amplifier according to another embodiment;
FIG. 3 is a schematic diagram of an adaptive feedforward linear power amplifier according to another embodiment;
FIG. 4 is a schematic diagram of an adaptive feedforward linear power amplifier according to another embodiment;
FIG. 5 is a schematic diagram of an adaptive feedforward linear power amplifier in another embodiment;
fig. 6 is a schematic structural diagram of an adaptive feedforward linear power amplifier in another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, there is provided an adaptive feedforward linearized power amplifier apparatus, including: a self-adaptive error detection loop 2 based on a simulation minimum mean method and a self-adaptive error cancellation loop 3 based on the simulation minimum mean method; the first input end of the self-adaptive error detection loop 2 is connected with the input end of the main power amplifier 1, the output end of the main power amplifier 1 is respectively connected with the second input end of the self-adaptive error detection loop 2 and the second input end of the self-adaptive error cancellation loop 3, the output end of the self-adaptive error detection loop 2 is connected with the first input end of the self-adaptive error cancellation loop 3, and the self-adaptive error cancellation loop 3 outputs a signal at the output end.
The self-adaptive error detection loop 2 is used for extracting a distortion-free signal from the input end of the main power amplifier 1, extracting a first distortion signal from the output end of the main power amplifier 1, processing the distortion-free signal and the first distortion signal, and outputting an error sample signal to the first input end of the self-adaptive error cancellation loop 3; the adaptive error cancellation loop 3 is configured to use the error sample signal and the first distortion signal output by the output end of the main power amplifier 1 as input signals, process the error sample signal and the first distortion signal, and adaptively cancel an error signal component in the first distortion signal and output the error signal component.
The main power amplifier 1 is a radio frequency power amplifier which needs to be linearized, a radio frequency input signal of the feed-forward power amplifier is amplified through the main power amplifier 1, and a nonlinear error signal generated by the main power amplifier 1 is superposed on a linear signal due to nonlinearity of the main power amplifier 1 to obtain a distorted output signal (namely, a first distorted signal). The self-adaptive error detection loop 2 is a self-adaptive feedback loop based on an analog least mean square method and is used for adaptively extracting a distortion-free signal which is not amplified by the main power amplifier 1 at an input port of the main power amplifier 1 and extracting a first amplified distorted signal at an output port of the main power amplifier 1, and the self-adaptive error detection loop 2 compares the distortion-free signal with the first distorted signal and adaptively outputs an error sample signal. The adaptive error cancellation loop 3 is an adaptive feedback loop based on an analog least mean square method, and is used for adaptively canceling an error signal in a distortion signal output by the main power amplifier 1, an error sample signal output by the adaptive error detection loop 2 and a first distortion signal output by the main power amplifier 1 are used as input signals of the adaptive error cancellation loop 3, and after the adaptive error cancellation loop 3 processes the error sample signal and the first distortion signal, an error signal component in the first distortion signal is adaptively canceled, so that a linearized radio frequency output signal is obtained. Thereby improving the linearity of the feed-forward power amplifier.
As shown in fig. 2, in one embodiment, an adaptive feedforward linear power amplifier further includes a first delay line 4; the first delay line 4 is connected between the output end of the main power amplifier 1 and the second input end of the adaptive error cancellation loop 3.
As shown in fig. 3, in one embodiment, adaptive error detection loop 2 includes: a first directional coupler 27, a second directional coupler 26, a third directional coupler 25, a first modulator 21, a first demodulator 22 and a first loop filter bank 23.
An input terminal of the first directional coupler 27 serves as a first input terminal of the adaptive error detection loop 2, a coupling output terminal of the first directional coupler 27 is connected to a first input terminal of the first modulator 21, a through output terminal of the first directional coupler 27 is connected to a first input terminal of the first demodulator 22, an output terminal of the first demodulator 22 is connected to an input terminal of the first loop filter bank 23, an output terminal of the first loop filter bank 23 is connected to a second input terminal of the first modulator 21, an output terminal of the first modulator 21 is connected to a first input terminal of the second directional coupler 26, a second input terminal of the second directional coupler 26 serves as a second input terminal of the adaptive error detection loop 2 and is connected to an output terminal of the main power amplifier 1, an output terminal of the second directional coupler 26 is connected to an input terminal of the third directional coupler 25, a coupling output terminal of the third directional coupler 25 is connected to a second input terminal of the first demodulator 22, the through output of the third directional coupler 25 serves as the output of the adaptive error detection loop 2.
In the adaptive error detection loop 2, a plurality of undistorted signals after different delays form a first reference signal vector group, and the first reference signal vector group is subjected to inner product with the conjugate of a complex weight value vector in the first modulator 21 to obtain a transformed undistorted signal after amplitude-phase transformation. The transformed undistorted signal and the first distorted signal are mutually cancelled to obtain an error sample signal. The first set of reference signal vectors and the conjugate of the error sample signal are multiplied by the complex signal in the first demodulator 22, and the output set of complex vectors are low-pass filtered by the first loop filter bank 23 to obtain the complex weight vector of the first modulator 21, thereby forming an adaptive cancellation loop based on the analog least mean square method.
As shown in fig. 4, in one embodiment, adaptive error detection loop 2 further includes: a second delay line 24; one end of second delay line 24 is connected to the through output of first directional coupler 27 and the other end of second delay line 24 is connected to the first input of first demodulator 22.
In the adaptive error detection loop 2, before the distortion-free signal is input to the first demodulator 22, the bandwidth of the first loop filter bank 23 during stable operation can be increased through the second delay line 24, so as to improve the reliability of the first loop filter bank 23 during normal operation.
In one embodiment, the first modulator 21 is constituted by at least one quadrature multiplication unit.
The orthogonal multiplication unit is used to implement complex signal conjugate multiplication in the first modulator 21, and the more orthogonal multiplication units are used, the better the bandwidth and accuracy of cancellation are.
In one embodiment, when first modulator 21 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit serves as the first input of first modulator 21, the output of the quadrature multiplication unit serves as the output of first modulator 21, and the second input of the quadrature multiplication unit serves as the second input of first modulator 21; when the first modulator 21 is composed of two or more orthogonal multiplying units, it is connected to other devices in the adaptive error detection loop 2 through a power divider.
Specifically, for example, in the case where the first modulator 21 is configured by two orthogonal multiplication units, as shown in fig. 4, the first modulator 21 includes: a first power divider 214, a first quadrature multiplication unit 211, a third delay line 213, a second quadrature multiplication unit 212, and a second power divider 215.
A combined port of the first power divider 214 is used as a first input end of the first modulator 21, two power dividing ports of the first power divider 314 are respectively connected to a first input end of the first orthogonal multiplication unit 211 and one end of the third delay line 213, the other end of the third delay line 213 is connected to a first input end of the second orthogonal multiplication unit 212, output ends of the first orthogonal multiplication unit 211 and the second orthogonal multiplication unit 212 are respectively connected to two power dividing ports of the second power divider 215, a combined end of the second power divider 215 is used as an output end of the first modulator 21, and second input ends of the first orthogonal multiplication unit 211 and the second orthogonal multiplication unit 212 are used as a second input end of the first modulator 21.
The first orthogonal multiplication unit 211 includes: a first quadrature coupler 2113, a first multiplying unit 2111, a second multiplying unit 2112 and a first in-phase power divider 2114; an input end of the first quadrature coupler 2113 serves as a first input end of the first quadrature multiplication unit 211, an in-phase output end of the first quadrature coupler 2113 is connected to a first signal input end of the first multiplication unit 2111, an orthogonal output end of the first quadrature coupler 2113 is connected to a first signal input end of the second multiplication unit 2112, signal output ends of the first multiplication unit 2111 and the second multiplication unit 2112 are respectively connected to two power division ports of the first in-phase power divider 2114, a combining end of the first in-phase power divider 2114 serves as an output end of the first quadrature multiplication unit 211, and second signal input ends of the first multiplication unit 2111 and the second multiplication unit 2112 serve as a second input end of the first quadrature multiplication unit 211.
The second orthogonal multiplication unit 212 includes: a second quadrature coupler 2123, a third multiplying unit 2121, a fourth multiplying unit 2122, and a second in-phase power divider 2124; an input end of the second quadrature coupler 2123 serves as a first input end of the second quadrature multiplication unit 212, an in-phase output end of the second quadrature coupler 2123 is connected to a first signal input end of the third multiplication unit 2121, a quadrature output end of the second quadrature coupler 2123 is connected to a first signal input end of the fourth multiplication unit 2122, signal output ends of the third multiplication unit 2121 and the fourth multiplication unit 2122 are respectively connected to two power division ports of the second in-phase power divider 2124, a combining end of the second in-phase power divider 2124 serves as an output end of the second quadrature multiplication unit 212, and second signal input ends of the third multiplication unit 2121 and the fourth multiplication unit 2122 serve as a second input end of the second quadrature multiplication unit 212.
In one embodiment, first demodulator 22 is comprised of at least one quadrature multiplication unit.
The orthogonal multiplication unit is used to implement complex signal conjugate multiplication in the first demodulator 22, and the more orthogonal multiplication units are used, the better the bandwidth and accuracy of cancellation are.
In one embodiment, when first demodulator 22 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit serves as the first input of first demodulator 22, the output of the quadrature multiplication unit serves as the output of first demodulator 22, and the second input of the quadrature multiplication unit serves as the second input of first demodulator 22; when the first demodulator 22 is composed of two or more orthogonal multiplying units, it is connected to other devices in the adaptive error detection loop 2 through a power divider.
Specifically, for example, the first demodulator 22 is composed of two orthogonal multiplication units, as shown in fig. 4, in one embodiment, the first demodulator 22 includes: a third power divider 224, a fourth delay line 223, a third quadrature multiplication unit 221, a fourth quadrature multiplication unit 222, and a fourth power divider 225.
A combining end of the third power divider 224 serves as a first input end of the first demodulator 22, two power dividing ports of the third power divider 224 are respectively connected to a first input end of the third orthogonal multiplication unit 221 and one end of the fourth delay line 223, the other end of the fourth delay line 223 is connected to a first input end of the fourth orthogonal multiplication unit 222, second input ends of the third orthogonal multiplication unit 221 and the fourth orthogonal multiplication unit 222 are respectively connected to two power dividing ports of the fourth power divider 225, the combining end of the fourth power divider 225 serves as a second input end of the first demodulator 22, and output ends of the third orthogonal multiplication unit 221 and the fourth orthogonal multiplication unit 222 serve as output ends of the first demodulator 22.
Wherein the third orthogonal multiplication unit 221 includes: a third quadrature coupler 2213, a fifth multiplying unit 2211, a sixth multiplying unit 2212 and a third in-phase power divider 2214; an input end of the third quadrature coupler 2213 is used as a first input end of the third quadrature multiplication unit 221, an in-phase output end of the third quadrature coupler 2213 is connected to a first signal input end of the fifth multiplication unit 2211, a quadrature output end of the third quadrature coupler 2213 is connected to a first signal input end of the sixth multiplication unit 2212, second signal input ends of the fifth multiplication unit 2211 and the sixth multiplication unit 2212 are respectively connected to two power division ports of the third in-phase power divider 2214, a combining end of the third in-phase power divider 2214 is used as a second input end of the third quadrature multiplication unit 221, and signal output ends of the fifth multiplication unit 2211 and the sixth multiplication unit 2212 are used as output ends of the third quadrature multiplication unit 221.
The fourth orthogonal multiplication unit 222 includes: a fourth quadrature coupler 2223, a seventh multiplication unit 2221, an eighth multiplication unit 2222, and a fourth in-phase power divider 2224, where an input end of the fourth quadrature coupler 2223 serves as a first input end of the fourth quadrature multiplication unit 222, an in-phase output end of the fourth quadrature coupler 2223 is connected to a first signal input end of the seventh multiplication unit 2221, a quadrature output end of the fourth quadrature coupler 2223 is connected to a first signal input end of the eighth multiplication unit 2222, second signal input ends of the seventh multiplication unit 2221 and the eighth multiplication unit 2222 are respectively connected to two power division ports of the fourth in-phase power divider 2224, a combined end of the fourth in-phase power divider 2224 serves as a second input end of the fourth quadrature multiplication unit 222, and signal output ends of the seventh multiplication unit 2221 and the eighth multiplication unit 2222 serve as output ends of the fourth quadrature multiplication unit 222.
Wherein the third delay line 213 and the fourth delay line 223 have the same delay amount.
In one embodiment, the first loop filter bank 23 is composed of four loop filters, respectively: a first loop filter 231, a second loop filter 232, a third loop filter 233 and a fourth loop filter 234, wherein a signal input terminal of the first loop filter 231 is connected to a signal output terminal of the fifth multiplying unit 2211, and a signal output terminal of the first loop filter 231 is connected to a second signal input terminal of the first multiplying unit 2111; a signal input terminal of the second loop filter 232 is connected to a signal output terminal of the sixth multiplying unit 2212, and a signal output terminal of the second loop filter 232 is connected to a second signal input terminal of the second multiplying unit 2112; a signal input terminal of the third loop filter 233 is connected to a signal output terminal of the seventh multiplying unit 2221, and a signal output terminal of the third loop filter 233 is connected to a second signal input terminal of the third multiplying unit 2121; a signal input of the fourth loop filter 234 is connected to a signal output of the eighth multiplying unit 2222, and a signal output of the fourth loop filter 234 is connected to a second signal input of the third multiplying unit 2121.
As shown in fig. 5, in one embodiment, the adaptive error cancellation loop 3 includes: a second demodulator 32, a second loop filter bank 33, a second modulator 31, a linear power amplifier 34, a fourth directional coupler 38, a fifth directional coupler 36, and a sixth directional coupler 37;
an input of the fourth directional coupler 38 serves as a first input of the adaptive error cancellation loop 3, a coupled output of the fourth directional coupler 38 is connected to a first input of the second modulator 31, an output of the second modulator 31 is connected to an input of the linear power amplifier 34, an output of the linear power amplifier 34 is connected to a first input of the fifth directional coupler 36, a second input of the fifth directional coupler 36 serves as a second input of the adaptive error cancellation loop 3, an output of the fifth directional coupler 36 is connected to an input of the sixth directional coupler 37, a through output of the sixth directional coupler 37 serves as an output of the adaptive error cancellation loop 3, a coupled output of the sixth directional coupler 37 is connected to a second input of the second demodulator 32, a through output of the fourth directional coupler 38 is connected to a first input of the second demodulator 32, the output of the second demodulator 32 is connected to an input of a second loop filter bank 33, and the output of the second loop filter bank 33 is connected to a second input of the second modulator 31.
In the adaptive error cancellation loop 3, a plurality of error sample signals with different delays form a second reference signal vector group, the second reference signal vector group is inner-multiplied with the conjugate of a complex weight value vector in the second modulator 31, and amplified by the linear power amplifier 34 to obtain a converted error signal after amplitude-phase conversion, the converted error signal and the first distortion signal are mutually offset to eliminate the error component in the first distortion signal to obtain the radio frequency output signal of feedforward power amplification linearization, the conjugation of the second reference signal vector group and the linear output signal, in the second demodulator 32, the complex signals are multiplied, and the output complex vectors are low-pass filtered by the second loop filter bank 33, the vector of complex weights of the second modulator 31 is obtained, thus forming an adaptive cancellation loop based on the analog least mean squares method.
As shown in fig. 6, in one embodiment, the adaptive error cancellation loop 3 further includes: a fifth delay line 35; one end of a fifth delay line 35 is connected to the through output of the fourth directional coupler 38 and the other end of the fifth delay line 35 is connected to the first input of the second demodulator 32.
In the adaptive error cancellation loop 3, before the error signal is input to the demodulator 32, a delay circuit 35 is used to increase the bandwidth of the second loop filter bank 33 for stable operation, so as to improve the reliability of the second loop filter bank 33 for normal operation.
In one embodiment, the second modulator 31 is constituted by at least one quadrature multiplying unit.
The orthogonal multiplication unit is used to implement complex signal conjugate multiplication in the second modulator 31, and the more orthogonal multiplication units are used, the better the bandwidth and accuracy of cancellation are.
In one embodiment, when second modulator 31 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit serves as the first input of second modulator 31, the output of the quadrature multiplication unit serves as the output of second modulator 31, and the second input of the quadrature multiplication unit serves as the second input of second modulator 31; when the second modulator 31 is composed of more than two orthogonal multiplication units, it is connected to other devices in the adaptive error cancellation loop 3 through a power divider.
Specifically, for example, the second modulator 31 is composed of two orthogonal multiplication units, as shown in fig. 6, in one embodiment, the second modulator 31 includes: a fifth power divider 314, a sixth delay line 313, a fifth orthogonal multiplication unit 311, a sixth orthogonal multiplication unit 312, and a sixth power divider 315; a combined port of the fifth power divider 314 serves as a first input end of the second modulator 31, two power dividing ports of the fifth power divider 314 are respectively connected to a first input end of the fifth orthogonal multiplication unit 311 and one end of the sixth delay line 313, the other end of the sixth delay line 313 is connected to a first input end of the sixth orthogonal multiplication unit 312, output ends of the fifth orthogonal multiplication unit 311 and the sixth orthogonal multiplication unit 312 are respectively connected to two power dividing ports of the sixth power divider 315, a combined end of the sixth power divider 315 serves as an output end of the second modulator 31, and second input ends of the fifth orthogonal multiplication unit 311 and the sixth orthogonal multiplication unit 312 serve as second input ends of the second modulator 31.
Wherein the fifth orthogonal multiplication unit 311 includes: a fifth quadrature coupler 3113, a ninth multiplying unit 3111, a tenth multiplying unit 3112, and a fifth in-phase power divider 3114; an input end of the fifth quadrature coupler 3113 is used as a first input end of the fifth quadrature multiplication unit 311, an in-phase output end of the fifth quadrature coupler 3113 is connected to a first signal input end of the ninth multiplication unit 3111, a quadrature output end of the fifth quadrature coupler 3113 is connected to a first signal input end of the tenth multiplication unit 3112, signal output ends of the ninth multiplication unit 3111 and the tenth multiplication unit 3112 are respectively connected to two power division ports of the fifth in-phase power divider 3114, a combining end of the fifth in-phase power divider 3114 is used as an output end of the fifth quadrature multiplication unit 311, and second signal input ends of the ninth multiplication unit 3111 and the tenth multiplication unit 3112 are used as a second input end of the fifth quadrature multiplication unit 311.
The sixth orthogonal multiplication unit 312 includes: a sixth quadrature coupler 3123, an eleventh multiplying unit 3121, a twelfth multiplying unit 3122, and a sixth in-phase power divider 3124; an input end of the sixth quadrature coupler 3123 serves as a first input end of the sixth quadrature multiplication unit 312, an in-phase output end of the sixth quadrature coupler 3123 is connected to a first signal input end of the eleventh multiplication unit 3121, a quadrature output end of the sixth quadrature coupler 3123 is connected to a first signal input end of the twelfth multiplication unit 3122, signal output ends of the eleventh multiplication unit 3121 and the twelfth multiplication unit 3122 are respectively connected to two power division ports of the sixth in-phase power divider 3124, a combining end of the sixth in-phase power divider 3124 serves as an output end of the sixth quadrature multiplication unit 312, and second signal input ends of the eleventh multiplication unit 3121 and the twelfth multiplication unit 3122 serve as a second input end of the sixth quadrature multiplication unit 312.
In one embodiment, second demodulator 32 is comprised of at least one quadrature multiplication unit.
The orthogonal multiplication unit is used to implement complex signal conjugate multiplication in the second demodulator 32, and the more orthogonal multiplication units are used, the better the bandwidth and precision of cancellation are.
In one embodiment, when second demodulator 32 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit serves as the first input of second demodulator 32, the output of the quadrature multiplication unit serves as the output of second demodulator 32, and the second input of the quadrature multiplication unit serves as the second input of second demodulator 32; when the second demodulator 32 is composed of more than two orthogonal multiplication units, it is connected to other devices in the adaptive error cancellation loop 3 through a power divider.
Specifically, for example, the second demodulator 32 is composed of two orthogonal multiplication units, as shown in fig. 6, in one embodiment, the second demodulator 32 includes: a seventh power divider 324, a seventh delay line 323, a seventh orthogonal multiplication unit 321, an eighth orthogonal multiplication unit 322, and an eighth power divider 325; a combining end of the seventh power divider 324 serves as a first input end of the second demodulator 32, two power dividing ports of the seventh power divider 324 are respectively connected to a first input end of the seventh orthogonal multiplication unit 321 and one end of the seventh delay line 323, the other end of the seventh delay line 323 is connected to a first input end of the eighth orthogonal multiplication unit 322, second input ends of the seventh orthogonal multiplication unit 321 and the eighth orthogonal multiplication unit 322 are respectively connected to two power dividing ports of the eighth power divider 325, the combining end of the eighth power divider 325 serves as a second input end of the second demodulator 32, and output ends of the seventh orthogonal multiplication unit 321 and the eighth orthogonal multiplication unit 322 serve as output ends of the second demodulator 32.
Wherein, the seventh orthogonal multiplication unit 321 includes: a seventh quadrature coupler 3213, a thirteenth multiplying unit 3211, a fourteenth multiplying unit 3212, and a seventh in-phase power splitter 3214; an input end of the seventh quadrature coupler 3213 serves as a first input end of the seventh quadrature multiplying unit 321, an in-phase output end of the seventh quadrature coupler 3213 is connected to a first signal input end of the thirteenth multiplying unit 3211, an orthogonal output end of the seventh quadrature coupler 3212 is connected to a first signal input end of the fourteenth multiplying unit 3212, second signal input ends of the thirteenth multiplying unit 3211 and the fourteenth multiplying unit 3212 are respectively connected to two power dividing ports of the seventh in-phase power divider 3214, a combining end of the seventh in-phase power divider 3214 serves as a second input end of the seventh quadrature multiplying unit 321, and signal output ends of the thirteenth multiplying unit 3211 and the fourteenth multiplying unit 3212 serve as output ends of the seventh quadrature multiplying unit 321.
The eighth orthogonal multiplication unit 322 includes: an eighth quadrature coupler 3223, a fifteenth multiplication unit 3221, a sixteenth multiplication unit 3222, and an eighth in-phase power divider 3224; an input end of the eighth quadrature coupler 3223 is used as a first signal input end of the eighth quadrature multiplication unit 322, an in-phase output end of the eighth quadrature coupler 3223 is connected to a first signal input end of the fifteenth multiplication unit 3221, a quadrature output end of the eighth quadrature coupler 3223 is connected to a first signal input end of the sixteenth multiplication unit 3222, second signal input ends of the fifteenth multiplication unit 3221 and the sixteenth multiplication unit 3222 are respectively connected to two power division ports of the eighth in-phase power divider 3224, a combining end of the eighth in-phase power divider 3224 is used as a second signal input end of the eighth quadrature multiplication unit 322, and signal output ends of the fifteenth multiplication unit 3221 and the sixteenth multiplication unit 3222 are used as output ends of the eighth quadrature multiplication unit 322.
In one embodiment, the second loop filter bank 33 is composed of four loop filters, respectively: signal inputs of the fifth loop filter 311, the sixth loop filter 332, the seventh loop filter 333, and the eighth loop filter 334 serve as inputs of the second loop filter bank 33, and signal outputs of the fifth loop filter 311, the sixth loop filter 332, the seventh loop filter 333, and the eighth loop filter 334 serve as outputs of the second loop filter bank 33.
A signal input end of the fifth loop filter 331 is connected to a signal output end of the thirteenth multiplying unit 3211, and a signal output end of the fifth loop filter 331 is connected to a second signal input end of the ninth multiplying unit 3111; a signal input terminal of the sixth loop filter 332 is connected to a signal output terminal of the fourteenth multiplying unit 3212, and a signal output terminal of the sixth loop filter 332 is connected to a second signal input terminal of the tenth multiplying unit 3112; a signal input end of the seventh loop filter 333 is connected to a signal output end of the fifteenth multiplying unit 3221, and a signal output end of the seventh loop filter 333 is connected to a second signal input end of the eleventh multiplying unit 3121; a signal input terminal of the eighth loop filter 334 is connected to a signal output terminal of the sixteenth multiplying unit 3222, and a signal output terminal of the eighth loop filter 334 is connected to a second signal input terminal of the twelfth multiplying unit 3122.
Wherein the sixth delay line 313 and the seventh delay line 323 have the same delay amount.
The first in-phase power divider 2114, the second in-phase power divider 2124, the third in-phase power divider 2214, the fourth in-phase power divider 2224, the fifth in-phase power divider 3114, the sixth in-phase power divider 3124, the seventh in-phase power divider 3214, and the eighth in-phase power divider 3224 function to divide one signal into two signals with equal amplitude and in phase, and the first quadrature coupler 2113, the second quadrature coupler 2123, the third quadrature coupler 2213, the fourth quadrature coupler 2223, the fifth quadrature coupler 3113, the sixth quadrature coupler 3123, the seventh quadrature coupler 3213, and the eighth quadrature coupler 3223 function to divide one signal into two signals with equal amplitude and 90 ° phase difference.
As shown in fig. 4, the signal flow in the adaptive error detection loop 2 is illustrated as follows:
for convenience of description, the transmission losses of the power splitters and the quadrature couplers are ignored in the following analysis.
The undistorted input reference signal (i.e., the undistorted signal) is denoted as r. The undistorted signal r is divided into two paths in the first modulator 21, and after different delays, the two paths are input to the first orthogonal multiplication unit 211 and the second orthogonal multiplication unit 212, and are recorded as a vector r ═ r1，r2](ii) a Similarly, the undistorted signal is divided into two paths in the first demodulator 22 after passing through the delay line 24, and after passing through different delays, the two paths are input into the third orthogonal multiplication unit 221 and the fourth orthogonal multiplication unit 222, which are denoted as vector r' ═ r1’r2’]The signal output by the first modulator 21 and the first distortion signal are cancelled to obtain an error sample signal, which is fed back to the first modulatorIn the demodulator 22, denoted as e. The error sample signal e is multiplied by the vector r' in the third and fourth orthogonal multiplication units 221 and 222 in the first demodulator 22.
Taking the third orthogonal multiplication unit 221 as an example, r1' after being divided into two orthogonal signals by the third orthogonal coupler 2213, the two orthogonal signals are multiplied by the error sample signal e in the fifth and sixth multiplying units 2211 and 2212, and the two product signals obtained are low-pass components, which are actually real parts Re { r } of the conjugate multiplication products of the two complex signals1' e x and imaginary part Im { r }1' e }. These two signals are low-pass filtered by the first loop filter 231 and the second loop filter 232 as complex weights w1Is input into a first quadrature multiplication unit 211 in the first modulator 21. Similarly, two output signals Re { r of the fourth quadrature multiplication unit 2222' e x and imaginary part Im { r }2' e } is low pass filtered by the third loop filter 233 and the fourth loop filter 234 as a complex weight w2Is input into the second quadrature multiplication unit 212 in the first modulator 21. Weight w1And w2Form weight vector w ═ w1 w2]。
In the first orthogonal multiplication unit 211, r1After being divided into two orthogonal signals by the first orthogonal coupler 2113, the two orthogonal signals are multiplied by a complex weight w in the first multiplying unit 2111 and the second multiplying unit 21121Are multiplied by the real and imaginary parts of the signal, the products are combined by the first in-phase power divider 2114 as an output signal, r, neglecting the transmission loss of the first in-phase power divider 21141w1*. Similarly, the output of the second quadrature multiplication unit 212 may be denoted as r2w2*. It follows that the first demodulator 22 performs the function of multiplying the vector r' with the conjugate of the error sample signal e; the first modulator 21 performs the function of inner product the vector r with the conjugate of the weight vector w, whereby the adaptive error detection loop 2 is an adaptive loop based on the analog least mean squares method.
The signal flow in the adaptive error cancellation loop 3 is illustrated as follows:
for convenience of description, the transmission losses of the power splitters and the quadrature couplers are ignored in the following analysis.
The error sample signal is used as a reference input signal and is recorded as re. Error sample signal reThe second modulator 31 is divided into two paths, and after different delays, the two paths are input into a fifth orthogonal multiplication unit 311 and a sixth orthogonal multiplication unit 312, which are recorded as a vector re＝[re1，re2](ii) a Similarly, the error sample signal reAfter passing through the fifth delay line 35, the signal is divided into two paths in the second demodulator 32, and after different delays, the two paths are input into the seventh orthogonal multiplication unit 321 and the eighth orthogonal multiplication unit 322, and are recorded as a vector re’＝[re1’，re2’]. The signal output by the second modulator 31 is amplified by the linear power amplifier 34, and then cancelled by the first distortion signal in the sixth directional coupler 37, so that the resulting error signal-cancelled linearized rf output signal is fed back to the second demodulator 32, which is denoted as the linearized rf output signal Slin. Linearized radio frequency output signal SlinThe vector r is multiplied in the seventh orthogonal multiplication unit 321 and the eighth orthogonal multiplication unit 322 in the second demodulator 32e' multiplication.
Taking the seventh orthogonal multiplying unit 321 as an example, re1' after being divided into two orthogonal signals by a seventh orthogonal coupler 3213, the two orthogonal signals are combined with the linearized rf output signal S in a thirteenth and fourteenth multiplying units 3211 and 3212linMultiplication is carried out, and the obtained two product signals take low-pass components and are actually real parts Re { r } of conjugate multiplication products of the two complex signalse1’，SlinX and imaginary component Im { r }e1’，Slin*}. These two signals are low-pass filtered by the fifth loop filter 311 and the sixth loop filter 332 and then used as complex weights v1The real part and the imaginary part of (a) are input into a fifth quadrature multiplication unit 311 in the second modulator 31. Similarly, two output signals Re { r of the eighth orthogonal multiplication unit 322e2’，SlinX and Im { r }e2’，SlinIs low-pass filtered by a seventh loop filter 333 and an eighth loop filter 334 to be used as a complex weight v2The real part and the imaginary part of (a) are input to a sixth quadrature multiplication unit 312 in the second modulator 31. Complex weight v1And v2Form weight vector v ═ v1，v2]。
In the fifth orthogonal multiplication unit 311, re1After being divided into two orthogonal signals by the fifth orthogonal coupler 3113, the two orthogonal signals are multiplied by a complex weight v in a ninth multiplier 3111 and a tenth multiplier 31121Are multiplied by the real and imaginary components of the signal, the products are combined by the fifth in-phase power divider 3114 as an output signal, which is denoted as r, ignoring the transmission loss of the fifth in-phase power divider 3114e1v1*. Similarly, the output of the sixth quadrature multiplication unit 312 may be denoted as re2v2*. It follows that the second demodulator 32 implements the vector re' AND linearized RF output signal SlinThe function of conjugate multiplication of (a); the second modulator 31 implements the vector reThe function of inner product with the conjugate of the weight vector v, whereby the adaptive error detection loop 2 is an adaptive loop based on the analog least mean method.
To sum up, the application provides a self-adaptive feedforward linear power amplifier device, used the self-adaptive error detection loop based on the simulation minimum equalization method and the self-adaptive error cancellation loop based on the simulation minimum equalization method, the self-adaptive state adjustment function of the feedforward power amplifier, the circuit scheme is simple, the error cancellation state can be adjusted in a self-adaptive manner, the device is not affected by the environment and the drift of the main power discharge parameters, and the like, and no pilot frequency and other auxiliary signals are introduced. Therefore, the method is suitable for realizing broadband and high-linearity power amplification.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. An adaptive feedforward linear power amplifier device, comprising: the self-adaptive error detection loop based on the simulation minimum mean method and the self-adaptive error cancellation loop based on the simulation minimum mean method;
the first input end of the self-adaptive error detection loop is connected with the input end of a main power amplifier, the output end of the main power amplifier is respectively connected with the second input end of the self-adaptive error detection loop and the second input end of the self-adaptive error cancellation loop, the output end of the self-adaptive error detection loop is connected with the first input end of the self-adaptive error cancellation loop, and the output end of the self-adaptive error cancellation loop outputs a signal;
the adaptive error detection loop is used for extracting an undistorted signal from the input end of the main power amplifier, extracting a first distorted signal from the output end of the main power amplifier, processing the undistorted signal and the first distorted signal, and outputting an error sample signal to the first input end of the adaptive error cancellation loop;
the self-adaptive error cancellation loop is used for taking the error sample signal and the first distortion signal output by the output end of the main power amplifier as input signals, processing the error sample signal and the first distortion signal, and outputting the error signal after adaptively canceling an error signal component in the first distortion signal.
2. The apparatus of claim 1, further comprising: a first delay line;
the first delay line is connected between the output end of the main power amplifier and the second input end of the self-adaptive error cancellation loop.
3. The apparatus of claim 1, wherein the adaptive error detection loop comprises: the first directional coupler, the second directional coupler, the third directional coupler, the first modulator, the first demodulator and the first loop filter bank;
an input end of the first directional coupler is used as a first input end of the adaptive error detection loop, a coupling output end of the first directional coupler is connected with a first input end of the first modulator, a through output end of the first directional coupler is connected with a first input end of the first demodulator, an output end of the first demodulator is connected with an input end of the first loop filter bank, an output end of the first loop filter bank is connected with a second input end of the first modulator, an output end of the first modulator is connected with a first input end of the second directional coupler, a second input end of the second directional coupler is used as a second input end of the adaptive error detection loop and is connected with an output end of the main power amplifier, and an output end of the second directional coupler is connected with an input end of the third directional coupler, and the coupling output end of the third directional coupler is connected with the second input end of the first demodulator, and the through output end of the third directional coupler is used as the output end of the self-adaptive error detection loop.
4. The apparatus of claim 3, wherein the adaptive error detection loop further comprises: a second delay line;
one end of the second delay line is connected with the through output end of the first directional coupler, and the other end of the second delay line is connected with the first input end of the first demodulator.
5. The apparatus of claim 3, wherein the first modulator is comprised of at least one quadrature multiplication unit.
6. The apparatus of claim 3, wherein the first demodulator is comprised of at least one quadrature multiplication unit.
7. The apparatus of claim 1, wherein the adaptive error cancellation loop comprises: a second demodulator, a second loop filter bank, a second modulator, a linear power amplifier, a fourth directional coupler, a fifth directional coupler, and a sixth directional coupler;
an input end of the fourth directional coupler is used as a first input end of the adaptive error cancellation loop, a coupling output end of the fourth directional coupler is connected with a first input end of the second modulator, an output end of the second modulator is connected with an input end of the linear power amplifier, an output end of the linear power amplifier is connected with a first input end of the fifth directional coupler, a second input end of the fifth directional coupler is used as a second input end of the adaptive error cancellation loop, an output end of the fifth directional coupler is connected with an input end of the sixth directional coupler, a through output end of the sixth directional coupler is used as an output end of the adaptive error cancellation loop, a coupling output end of the sixth directional coupler is connected with a second input end of the second demodulator, and a through output end of the fourth directional coupler is connected with a first input end of the second demodulator, the output of the second demodulator is connected to the input of the second loop filter bank, and the output of the second loop filter bank is connected to the second input of the second modulator.
8. The apparatus of claim 7, wherein the adaptive error cancellation loop further comprises: a fifth delay line;
one end of the fifth delay line is connected with the through output end of the fourth directional coupler, and the other end of the fifth delay line is connected with the first input end of the second demodulator.
9. The apparatus of claim 7, wherein the second modulator is comprised of at least one quadrature multiplication unit.
10. The apparatus of claim 7, wherein the second demodulator is comprised of at least one quadrature multiplication unit.
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CN103475315A (en) * 2013-09-12 2013-12-25 电子科技大学 Method and device for improving linearity of radio frequency power amplifier
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CN1390063A (en) * 2001-05-31 2003-01-08 深圳市中兴通讯股份有限公司上海第二研究所 Linear power amplification method and power amplifier unit based on feedforward technique
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