CN113131733A - Power output buffer circuit and control method thereof - Google Patents
Power output buffer circuit and control method thereof Download PDFInfo
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- CN113131733A CN113131733A CN202110448072.2A CN202110448072A CN113131733A CN 113131733 A CN113131733 A CN 113131733A CN 202110448072 A CN202110448072 A CN 202110448072A CN 113131733 A CN113131733 A CN 113131733A
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- 230000003139 buffering effect Effects 0.000 abstract description 2
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- 238000010586 diagram Methods 0.000 description 2
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- 239000000463 material Substances 0.000 description 2
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- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
Abstract
The invention discloses a power output buffer circuit and a control method thereof, belonging to the field of current buffering; when the first power switch device and the second power switch device are disconnected, the third power switch device is firstly closed through the control circuit of the buffer circuit, and then the fourth power switch device is closed after time delay. And finally, the second power supply loop is conducted, and the power supply supplies power to the load. When the third power switch device is closed, the second power supply loop is in an off state, and the third power switch device is closed at the moment and cannot generate impact current; and when the fourth power switch device is closed, the third power switch device is already closed at the moment, which is equivalent to a conducting wire, and the third power switch device cannot be impacted. The requirements on the third power switch are therefore lower; meanwhile, because the first resistor and the second resistor exist in the second power supply circuit, the impact on the fourth power switch device is small. The cost of the buffer circuit can be greatly reduced.
Description
Technical Field
The present invention relates to current buffering technologies, and in particular, to a power output buffer circuit and a control method thereof.
Background
During power applications, the load characteristics due to the power connection are capacitive or inductive. When the power supply outputs instantly or the power switch device is switched on to supply power, capacitive load is charged instantly or inductive load is started instantly, and the power supply needs to output a large current which exceeds rated output by ten times or hundred times instantly. The large impact current is easy to damage the internal devices of the power supply, and the service life of the power supply is influenced; the power switch device at the output end of the power supply is overloaded seriously, and the contact is adhered; meanwhile, the input waveform of the power supply is distorted, and the power grid pollution is caused.
The existing solutions are therefore: a current surge circuit is added at the output end of the power supply, however, the circuit also needs a power switch device which can resist high voltage and high current surge, and the cost of the circuit is increased.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a power output buffer circuit and a control method thereof, which are used for solving the problem that when a buffer circuit is added at a power output end, a power switch device resistant to high voltage and high current impact is needed, so that the circuit cost and the volume are increased.
The technical scheme adopted by the invention for solving the technical problems is as follows:
on the one hand, the method comprises the following steps of,
a power output buffer circuit comprises a power supply loop and a buffer loop, wherein the power supply loop comprises a power supply, a first power switch device, a load and a second power switch device; the first power switch device and the second power switch device are respectively positioned between the load and the anode and the cathode of the power supply;
the buffer loop comprises a first resistor, a third power switch device, a fourth power switch device, a second resistor and a control circuit, and the first resistor, the third power switch device, the fourth power switch device, the second resistor, a power supply and a load form a second power supply loop;
when the first power switch device and the second power switch device disconnect the load from the anode and the cathode of the power supply respectively, the control circuit controls the third power switch device to be closed firstly, and controls the fourth power switch device to be closed after the preset time delay, so that the power supply supplies power to the load through the second power supply loop.
Further, in the second power supply loop:
the first resistor is connected in series with a contact part of a third power switch device and then connected in parallel with the first power switch device;
and the second resistor is connected with the contact part of the fourth power switch device in series and then connected with the second power switch device in parallel.
Further, the control circuit comprises a control chip, a first relay, a delay circuit and a second relay;
the control signal sent by the control chip is directly sent to the first relay;
the control signal sent by the control chip is sent to the second relay after passing through the delay circuit;
the first relay is connected with a control part of the third power switch device, and controls a contact part of the third power switch device to be opened or closed after receiving a control signal;
and the second relay is connected with the control part of the fourth power switch device and controls the contact part of the fourth power switch device to be opened or closed after receiving the control signal.
Furthermore, the control chip is connected with a first relay, the first relay is respectively connected with a control part of the third power switch device and a delay circuit, and the delay circuit is connected with a second relay.
Further, the first relay adopts a photoelectric relay.
Further, the delay circuit adopts an RC delay circuit.
Further, the first power switch device, the second power switch device, the third power switch device and the fourth power switch device adopt any one of the following:
a relay;
a thyristor;
a transistor.
On the other hand, in the case of a liquid,
a control method of a power output buffer circuit, the circuit of the above technical scheme of the buffer circuit comprises the following steps:
controlling the first power switch device to disconnect the load from the positive pole of the power source and controlling the second power switch device to disconnect the load from the negative pole of the power source;
and the controller for controlling the buffer loop sends a control signal to enable the third power switch device to be closed before the fourth power switch device, so that the second power supply loop supplies power to the load.
Further, still include: and after the first power switch device and the second power switch device are closed, controlling the third power switch device and the fourth power switch device to be switched off.
This application adopts above technical scheme, possesses following beneficial effect at least:
the technical scheme of the application provides a power output buffer circuit and a control method thereof, and the power output buffer circuit comprises a power supply, a first power switch device, a load and a second power switch device which form a power supply loop; the power supply, the first resistor, the third power switch device, the fourth power switch device, the second resistor and the load form a second power supply loop. When the first power switch device and the second power switch device are disconnected, the third power switch device is firstly closed through the control circuit of the buffer circuit, and then the fourth power switch device is closed after time delay. And finally, the second power supply loop is conducted, and the power supply supplies power to the load. When the third power switch device is closed, the second power supply loop is in an off state, and the third power switch device is closed at the moment and cannot generate impact current; and when the fourth power switch device is closed, the third power switch device is already closed at the moment, which is equivalent to a conducting wire, and the third power switch device cannot be impacted. The requirements on the third power switch are therefore lower; meanwhile, because the first resistor and the second resistor exist in the second power supply circuit, the impact on the fourth power switch device is small. The cost of the buffer circuit can be greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a block diagram of a power output buffer circuit according to an embodiment of the present invention;
FIG. 2 is a detailed schematic diagram of a power output buffer circuit according to an embodiment of the invention;
fig. 3 is a flowchart of a method for controlling a power output buffer circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following detailed description of the technical solutions of the present invention is provided with reference to the accompanying drawings and examples. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without making any creative effort, shall fall within the protection scope of the present application.
First, the power switching device is divided into a contact portion and a control portion according to functions, and the contact portion is connected or disconnected after the control portion is energized. With specific reference to relays, the control portion corresponds to a coil and a spring portion, and the contact portions are a fixed contact and a movable contact.
Referring to fig. 1, an embodiment of the present invention provides a power output buffer circuit, which includes a power supply loop and a buffer loop, where the power supply loop includes a power supply 11, a first power switch device 12, a load 14, and a second power switch device 13; the first power switch 12 and the second power switch 13 are respectively located between the load 14 and the positive and negative electrodes of the power source 11;
the snubber circuit comprises a first resistor 15, a third power switch device 16, a fourth power switch device 17, a second resistor 18 and a control circuit 19, wherein the first resistor 15, the third power switch device 16, the fourth power switch device 17, the second resistor 18, the power supply 11 and the load 14 form a second power supply circuit;
when the first power switch device 12 and the second power switch device 13 disconnect the load 14 from the positive electrode and the negative electrode of the power supply 11, the control circuit 19 controls the third power switch device 16 to be closed first, and controls the fourth power switch device 17 to be closed after a preset time delay, so that the power supply 11 supplies power to the load 14 through the second power supply loop.
According to the power output buffer circuit provided by the embodiment of the invention, firstly, a power supply, a first power switch device, a load and a second power switch device form a power supply loop; the power supply, the first resistor, the third power switch device, the fourth power switch device, the second resistor and the load form a second power supply loop. When the first power switch device and the second power switch device are disconnected, the third power switch device is firstly closed through the control circuit of the buffer circuit, and then the fourth power switch device is closed after time delay. And finally, the second power supply loop is conducted, and the power supply supplies power to the load. When the third power switch device is closed, the second power supply loop is in an off state, and the third power switch device is closed at the moment and cannot generate impact current; and when the fourth power switch device is closed, the third power switch device is already closed at the moment, which is equivalent to a conducting wire, and the third power switch device cannot be impacted. The requirements on the third power switch are therefore lower; meanwhile, because the first resistor and the second resistor exist in the second power supply circuit, the impact on the fourth power switch device is small. The cost of the buffer circuit can be greatly reduced.
As a further description of the above embodiments, the embodiments of the present invention provide an implementation manner. As shown in fig. 2.
The first resistor R1 is connected in series with the contact part of the third power switch device G and then is connected in parallel with the first power switch device A;
the second resistor R2 is connected in series with the contact point of the fourth power switch C and then connected in parallel with the second power switch B.
The first power switch device A, the second power switch device B, the third power switch device G and the fourth power switch device C all adopt relays.
The control circuit comprises a control chip X1, a first relay N1, a time delay circuit and a second relay N2;
the control signal sent by the control chip X1 is directly sent to the first relay N1;
a control signal sent by the control chip X1 is sent to the second relay N2 after passing through the delay circuit;
the first relay N1 is connected with the control part of the third power switch device G, and controls the contact part of the third power switch device G to be opened or closed after receiving the control signal;
the second relay N2 is connected to a control portion of the fourth power switching device C, and controls the contact portion of the fourth power switching device C to open or close after receiving the control signal.
Specifically, the control chip X1 is connected to the first relay N1, the first relay N1 is connected to the control part of the third power switch G and the delay circuit, respectively, and the delay circuit is connected to the second relay N2.
The first relay N1 is a photo relay. The photoelectric relay works to drive the current to be small (2mA), and the output can directly drive the mechanical relay, and meanwhile, the control chip X1 can be isolated from the controlled circuit. The delay circuit adopts an RC delay circuit. Particularly, the circuit comprises a third resistor R3 and a capacitor C2, and is simple in structure and low in cost.
As an alternative implementation manner of the embodiment of the present invention, the first power switch device a, the second power switch device B, the third power switch device G, and the fourth power switch device C may take a form including, but not limited to: relays, thyristors and transistors.
The working principle is as follows: the first power switch device A and the second power switch device B are connected to the positive and negative output ends of the power supply to control whether the power supply supplies power to the load or not. A current first resistor R1 and a second resistor R2 are connected across the contacts of the first power switch A and the second power switch B. Before the first power switch device a and the second power switch device B are closed, the first resistor R1 and the second resistor R2 are connected to the power supply loop to supply power to the load in advance. And then the first power switch device A and the second power switch device B are closed, and because the load is supplied with power, larger current impact cannot be generated, and the current impact on the first power switch device A and the second power switch device B is reduced at the moment.
When the control chip X1 sends a control signal, the first relay N1 is driven to be turned on, and the third power switch G is turned on accordingly. At this time, the third power switch G is closed, and the first resistor R1 is connected to the power supply circuit, but since the control signal is delayed by the delay circuit, the fourth power switch C is not closed, the load is not connected to the negative electrode of the power supply, that is, the second power supply circuit is in an open state, and no current passes through the first resistor R1, no impact is generated when the third power switch G is closed. After the third power switch device G is conducted, the second relay N2 is conducted after time delay of the time delay circuit, the fourth power switch device C is closed after the second relay N2 is conducted, the power supply supplies power for the load through the second power supply loop, and because the fourth power switch device C is closed instantly, the first resistor R1 and the second resistor R2 of the second power supply loop enable the impact borne by the fourth power switch device C to be reduced, and the third power switch device G is closed at the moment and is equivalent to a lead, so that the impact cannot be borne.
When the first power switch device A and the second power switch device B are closed, the second power supply loop is disconnected, but at the moment, power is supplied to the load, so that large impact cannot be generated on the first power switch and the second power switch. In the conventional snubber circuit, the third power switch G and the fourth power switch C both need to withstand high voltage and high current. In the embodiment of the invention, only the fourth power switch C is required to be resistant to high voltage and high current, the requirements on the high voltage resistance and high current performance of the third power switch G are not high, and the requirements on the high voltage resistance and high current performance of the fourth power switch C can be reduced due to the existence of the first resistor R1 and the second resistor R2.
In an embodiment, an embodiment of the present invention provides a method for controlling a power output buffer circuit, where the buffer circuit provided in the embodiment of the present invention includes, as shown in fig. 3, the following steps:
controlling the first power switch device to disconnect the load from the positive pole of the power source and controlling the second power switch device to disconnect the load from the negative pole of the power source;
and the controller for controlling the buffer loop sends a control signal to enable the third power switch device to be closed before the fourth power switch device, so that the second power supply loop supplies power to the load.
As an optional implementation manner of the embodiment of the present invention, after the first power switch device and the second power switch device are closed, the third power switch device and the fourth power switch device are controlled to be turned off. So that the third power switch device and the fourth power switch device can be controlled to be closed again when the power switch is used next time.
According to the control method of the power output buffer circuit provided by the embodiment of the invention, when the power supply does not supply power to the load, the third power switch device is controlled to be closed firstly, and the fourth power switch device is controlled to be closed after time delay, so that the power supply supplies power to the load in advance. After time delay, the third power switch device is equivalent to a lead, impact cannot be generated, and the fourth power switch device can reduce impact due to the existence of resistance; thus, when the first power switch device and the second power switch device are closed, the load is supplied with power, and the impact on the first power switch device and the second power switch device is small. By adopting the control method, the buffer circuit only adopts one power switch device with high voltage resistance and high current performance, thereby greatly reducing the cost.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware associated with program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (9)
1. A power output buffer circuit comprises a power supply loop and a buffer loop, wherein the power supply loop comprises a power supply, a first power switch device, a load and a second power switch device; the first power switch device and the second power switch device are respectively positioned between the load and the anode and the cathode of the power supply; the method is characterized in that:
the buffer loop comprises a first resistor, a third power switch device, a fourth power switch device, a second resistor and a control circuit, and the first resistor, the third power switch device, the fourth power switch device, the second resistor, a power supply and a load form a second power supply loop;
when the first power switch device and the second power switch device disconnect the load from the anode and the cathode of the power supply respectively, the control circuit controls the third power switch device to be closed firstly, and controls the fourth power switch device to be closed after the preset time delay, so that the power supply supplies power to the load through the second power supply loop.
2. The circuit of claim 1, wherein: in the second power supply loop:
the first resistor is connected in series with a contact part of a third power switch device and then connected in parallel with the first power switch device;
and the second resistor is connected with the contact part of the fourth power switch device in series and then connected with the second power switch device in parallel.
3. The circuit of claim 1, wherein: the control circuit comprises a control chip, a first relay, a delay circuit and a second relay;
the control signal sent by the control chip is directly sent to the first relay;
the control signal sent by the control chip is sent to the second relay after passing through the delay circuit;
the first relay is connected with a control part of the third power switch device, and controls a contact part of the third power switch device to be opened or closed after receiving a control signal;
and the second relay is connected with the control part of the fourth power switch device and controls the contact part of the fourth power switch device to be opened or closed after receiving the control signal.
4. The circuit of claim 3, wherein: the control chip is connected with a first relay, the first relay is respectively connected with a control part of the third power switch device and a delay circuit, and the delay circuit is connected with a second relay.
5. The circuit of claim 3 or 4, wherein: the first relay adopts a photoelectric relay.
6. The circuit of claim 3 or 4, wherein: the delay circuit adopts an RC delay circuit.
7. The circuit of claim 1, wherein: the first power switch device, the second power switch device, the third power switch device and the fourth power switch device adopt any one of the following:
a relay;
a thyristor;
a transistor.
8. A control method of a power output buffer circuit is characterized in that: the buffer circuit is the circuit of any one of claims 1-7, comprising the steps of:
controlling the first power switch device to disconnect the load from the positive pole of the power source and controlling the second power switch device to disconnect the load from the negative pole of the power source;
and the controller for controlling the buffer loop sends a control signal to enable the third power switch device to be closed before the fourth power switch device, so that the second power supply loop supplies power to the load.
9. The method of claim 8, further comprising: and after the first power switch device and the second power switch device are closed, controlling the third power switch device and the fourth power switch device to be switched off.
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| CN202110448072.2A CN113131733A (en) | 2021-04-25 | 2021-04-25 | Power output buffer circuit and control method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110448072.2A CN113131733A (en) | 2021-04-25 | 2021-04-25 | Power output buffer circuit and control method thereof |
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| US20090212627A1 (en) * | 2008-02-21 | 2009-08-27 | Hideki Sakata | Car power source apparatus |
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| WO2017063561A1 (en) * | 2015-10-12 | 2017-04-20 | 北京新能源汽车股份有限公司 | Electric vehicle, and high voltage system, detection method, and pre-charging circuit thereof |
| CN109017315A (en) * | 2018-08-23 | 2018-12-18 | 北京理工大学 | A kind of power supply Self-Protection Subsystem of hybrid vehicle and method |
| CN210380690U (en) * | 2019-05-31 | 2020-04-21 | 青岛钜洋信息工程有限公司 | Improved high-power high-precision bidirectional power supply |
-
2021
- 2021-04-25 CN CN202110448072.2A patent/CN113131733A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090212627A1 (en) * | 2008-02-21 | 2009-08-27 | Hideki Sakata | Car power source apparatus |
| US20150219720A1 (en) * | 2012-08-21 | 2015-08-06 | Sk Innovation Co., Ltd. | Relay Control System and Method for Controlling Same |
| CN104597396A (en) * | 2014-12-11 | 2015-05-06 | 北京新能源汽车股份有限公司 | Method for performing high-voltage electrifying detection on electric vehicle |
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Address after: 102600 building 7, yard 25, Jinghai 4th Road, Beijing Economic and Technological Development Zone, Daxing District, Beijing Applicant after: Beijing Jiajie Hengxin Energy Technology Co.,Ltd. Address before: 100176 building 7, yard 25, Jinghai 4th Road, Beijing Economic and Technological Development Zone, Daxing District, Beijing Applicant before: BEIJING CETPOWER CO.,LTD. |
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Application publication date: 20210716 |