CN113130402A - Manufacturing method of single diffusion region cutting structure in FinFET - Google Patents
Manufacturing method of single diffusion region cutting structure in FinFET Download PDFInfo
- Publication number
- CN113130402A CN113130402A CN202110291474.6A CN202110291474A CN113130402A CN 113130402 A CN113130402 A CN 113130402A CN 202110291474 A CN202110291474 A CN 202110291474A CN 113130402 A CN113130402 A CN 113130402A
- Authority
- CN
- China
- Prior art keywords
- layer
- finfet
- forming
- gate structure
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
The invention discloses a manufacturing method of a single diffusion region cutting structure in a FinFET, which comprises the following steps: step one, forming a plurality of fin bodies; step two, forming a pseudo grid structure; step three, forming an embedded epitaxial layer; step four, forming a zeroth interlayer film; step five, forming a process of the single diffusion region cutting structure, comprising the following steps of: step 51, defining a forming area of a single diffusion area cutting structure by photoetching; step 52, etching the pseudo gate structure and the fin body in the forming region of the single diffusion region cutting structure to form a first groove; step 53, filling a first dielectric material layer with stress in the first groove; step 54, etching back the first dielectric material layer; step 55, filling a second polysilicon layer in the top sub-groove; and sixthly, performing a metal gate replacement process. The invention can avoid the defect that the embedded epitaxial layer delays to form a small plane and keep the stress of the embedded epitaxial layer, and the process control is easier.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a single diffusion cut-off structure in a fin field effect transistor (FinFET transistor).
Background
In a FinFET, a Double Diffusion Break (DDB) structure and a Single Diffusion Break (SDB) structure are generally used to implement isolation of a source region, and a width of an active region of a device unit, such as a Standard Logic Cell (Logic Standard Cell), is calculated according to a polysilicon gate step (CPP), where the DDB structure at least includes two dummy gate structures, and the SDB structure only needs to occupy a width of one dummy gate structure, so that the DDB needs to additionally increase a CPP width, and the SDB can set the width of the active region to a minimum, so that the SDB process has a higher device density and a smaller device area, and the SDB process technology is generally used in a process node below 14 nm.
As shown in fig. 1, the layout structure of the FinFET corresponds to the manufacturing method of the single diffusion region cut-off structure in the conventional FinFET; fig. 2A to 2C are cross-sectional views of steps of a method for manufacturing a single-diffusion-region cut-off structure in a conventional FinFET, taken along a dashed line BB1 in fig. 4; the manufacturing method of the single diffusion region cutting structure in the prior FinFET comprises the following steps:
in step one, as shown in fig. 2A, a plurality of fins 101 are formed on a semiconductor substrate 101 a.
Step two, as shown in fig. 2A, the fin body 101 in the formation region of the single diffusion region cutting structure shown by the dotted line frame 103 is etched to form a groove. Also shown in fig. 1 is a dashed box 103 corresponding to the formation region of the single diffusion region cutoff structure.
Step three, as shown in fig. 2A, a Flow Chemical Vapor Deposition (FCVD) process is used to simultaneously form an isolation oxide layer 105 in the spaced region of the fin 101 and fill an oxide layer 106 in the recess of the SDB formation region. After the FCVD process is completed, an annealing process is also included to cure the isolation oxide layer 105.
The spaced-apart region between the fins 101 is filled with an isolation oxide layer 105, and a top surface of the isolation oxide layer 105 is lower than a top surface of the fins 101. The oxide layer 106 is also etched back.
Step four, as shown in fig. 2A, forming a dummy gate structure, wherein in the gate forming region, the dummy gate structure covers the side surface and the top surface of the fin body 101; the dummy gate structure is formed by overlapping a first gate dielectric layer and a first polysilicon gate 102. Only the first polysilicon gate 102 is shown in fig. 1 and 2A, and the first gate dielectric layer is not shown.
In the FCVD process and the annealing process in the second step, the fin 101 may be lost, and the size of the groove may become smaller, and at this time, the width of the dummy gate structure in the SDB formation region may be smaller than the width of the groove, which may adversely affect the subsequent epitaxial growth of the embedded epitaxial layer.
When the width of the recess is reduced, it is avoided that the width of the dummy gate structure in the SDB formation region is smaller than the width of the recess, which is an ideal state, and corresponds to the ideal state in fig. 2A. Therefore, the existing method can generate adverse effects on the forming process of the dummy gate structure and the embedded epitaxial layer, and is not beneficial to process control.
As shown in fig. 1, in a top view, the dummy gate structure has a stripe structure, and the stripe structure of the dummy gate structure is perpendicular to the stripe structure of the fin 101.
After the dummy gate structure is formed, a step of forming a side wall 104 on the side surface of the dummy gate structure is further included.
And fifthly, forming an embedded epitaxial layer in the fin body 101 at two sides of the pseudo gate structure.
As shown in fig. 2A, step five includes the following sub-steps:
second grooves are formed in the fin body 101 on two sides of the dummy gate structure.
And carrying out epitaxial filling in the second grooves at two sides of the pseudo gate structure to form the embedded epitaxial layer.
The method also comprises the following steps after the embedded epitaxial layer is formed:
and performing source-drain injection to form a source region and a drain region in the embedded epitaxial layer on two sides of the pseudo gate structure respectively.
The FinFET comprises an N-type FinFET and a P-type FinFET; the embedded epitaxial layer of the N-type FinFET is made of SiP, which corresponds to the embedded SiP epitaxial layer 108 in fig. 2A; the embedded epitaxial layer of the P-type FinFET is SiGe, which corresponds to embedded SiGe epitaxial layer 107 in fig. 2G 2.
Sixthly, as shown in fig. 2A, forming a zero interlayer film 109, and performing a planarization process to make the top surface of the zero interlayer film 109 flush with the top surface of the dummy gate structure.
And seventhly, performing a metal gate replacement process to replace each pseudo gate structure with a metal gate structure.
The sub-steps of the metal gate replacement include:
as shown in fig. 2B, the dummy gate structure is removed.
As can be seen from the arrow line corresponding to the mark 110 in fig. 2B, after the dummy gate structure is removed, the stress of the embedded epitaxial layer on both sides of the SDB formation region is released, so that the stress change of the embedded epitaxial layer on the channel region is also reduced, thereby reducing the carrier mobility of the channel region and reducing the device performance.
As shown in fig. 2C, a second gate dielectric layer (not shown) and a metal gate 102a are sequentially formed on the inner side surface of the removed region of each of the dummy gate structures.
As can be seen from the arrow line corresponding to the mark 111 in fig. 2B, the metal gate 102a itself has stress, so the metal gate 102a changes the stress of the embedded epitaxial layer, but the change of the stress of the embedded epitaxial layer caused by the metal gate 102a may be beneficial to increasing the carrier mobility of the channel region, and finally, the uniformity of the improvement on the performance of the device is poor, and the process control is difficult.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of a single diffusion region cutting structure in a FinFET, which can prevent the single diffusion region cutting structure from generating adverse effects on the epitaxial growth of an embedded epitaxial layer so as to avoid the facet defect of the embedded epitaxial layer, and can prevent the single diffusion region cutting structure from generating adverse effects on the stress of the embedded epitaxial layer so as to keep the stress of the embedded epitaxial layer.
In order to solve the above technical problem, the method for manufacturing a single diffusion region cut-off structure in a FinFET provided in the present invention includes the following steps:
the method comprises the steps of firstly, forming a plurality of fin bodies on a semiconductor substrate, wherein an isolation medium layer is filled in a spacing area between the fin bodies, and the top surfaces of the isolation medium layers are lower than the top surfaces of the fin bodies.
Forming a pseudo gate structure, wherein the pseudo gate structure covers the side surface and the top surface of the fin body in a gate forming region; the pseudo gate structure is formed by overlapping a first gate dielectric layer and a first polysilicon gate.
And step three, forming an embedded epitaxial layer in the fin bodies on two sides of the pseudo gate structure.
And fourthly, forming a zero-layer interlayer film, and performing a planarization process to enable the top surface of the zero-layer interlayer film to be level with the top surface of the pseudo gate structure.
Step five, forming a process of the single diffusion region cutting structure, comprising the following sub-steps:
and 51, defining a forming area of the single diffusion area cutting structure by photoetching.
And 52, etching the dummy gate structure in the forming region of the single diffusion region cutting structure and the semiconductor substrate material of the fin body at the bottom of the dummy gate structure to form a first groove.
And 53, filling a first dielectric material layer in the first groove, wherein the first dielectric material layer has stress, and the stress of the embedded epitaxial layer is kept by the interaction between the stress energy of the first dielectric material layer and the adjacent embedded epitaxial layers at two sides.
And 54, etching back the first dielectric material layer to lower the top surface of the first dielectric material layer and form a top sub-groove of the first groove on the first dielectric material layer. The bottom surface of the top sub-groove is equal to or higher than the top surface of the fin body, and the single diffusion region cutting structure is formed by the first medium material layer after back etching.
And step 55, filling a second polysilicon layer in the top sub-groove of the first groove.
And sixthly, performing a metal gate replacement process to replace each pseudo gate structure with a metal gate structure and replace the second polycrystalline silicon layer with a second metal gate structure.
In a further improvement, the semiconductor substrate comprises a silicon substrate or an SOI substrate.
The further improvement is that in the first step, the isolation medium layer is an oxide layer and is formed by deposition by adopting an FCVD (plasma chemical vapor deposition) process; after the isolation medium layer is deposited, the isolation medium layer is chemically ground and etched, so that the top surface of the isolation medium layer is etched back to be lower than the top surface of the fin body.
In a further improvement, in the first step, the fin body is formed by performing patterned etching on the semiconductor substrate.
In a further improvement, each fin body is in a strip structure.
In a further improvement, the first gate dielectric layer comprises a gate oxide layer.
In a further improvement, in the second step, a first hard mask layer is further formed on the top surface of the first polysilicon gate; the forming process of the dummy gate structure comprises the following sub-steps:
and sequentially forming the first gate dielectric layer, the first polysilicon gate and the first hard mask layer.
And carrying out graphical etching on the first hard mask layer to remove the first hard mask layer in the gate forming region and retain the first hard mask layer outside the gate forming region.
And etching the first polysilicon gate and the first gate dielectric layer by taking the first hard mask layer as a mask to form the pseudo gate structure.
In a further improvement, on a plane of view, the dummy gate structure is a strip structure, and the strip structure of the dummy gate structure is perpendicular to the strip structure of the fin body.
In a further improvement, in the second step, after the formation of the dummy gate structure, a step of forming a side wall on a side surface of the dummy gate structure is further included.
The further improvement is that the third step comprises the following sub-steps:
and forming second grooves in the fin bodies on two sides of the pseudo gate structure.
And carrying out epitaxial filling in the second grooves at two sides of the pseudo gate structure to form the embedded epitaxial layer.
In a further improvement, in step three, after forming the embedded epitaxial layer, the method further comprises the steps of:
and performing source-drain injection to form a source region and a drain region in the embedded epitaxial layer on two sides of the pseudo gate structure respectively.
The further improvement is that, in the fourth step, the planarization process of the zero-layer interlayer film comprises a chemical mechanical polishing process and a back etching process; and after the planarization process, the top surface of the zero layer interlayer film is flush with the top surface of the first hard mask layer on the top of the pseudo gate structure.
The method further comprises a step of forming a contact etching stop layer before forming the zero interlayer film, wherein the top surface of the contact etching stop layer after the planarization process in the step four is flush with the top surface of the first hard mask layer on the top of the dummy gate structure.
In a further refinement, the finfets include N-type finfets and P-type finfets.
The material of the embedded epitaxial layer of the N-type FinFET comprises SiP.
The material of the embedded epitaxial layer of the P-type FinFET comprises SiGe.
In a further improvement, in step 53, the material of the first dielectric material layer is SiC or SiN.
In a further improvement, in step 54, the depth of the top sub-groove of the first groove is 30nm to 50 nm.
Compared with the prior art that the SDB first etching (cut first SDB) process is adopted, the invention adopts the SDB last etching (cut last SDB) process, namely the SDB etching process, namely the etching process of the step 52, is placed after the pseudo gate structure is formed, so that the embedded epitaxial layer can be formed before the SDB etching process, and the single diffusion region cutting structure can be prevented from generating adverse influence on the epitaxial growth of the embedded epitaxial layer so as to avoid the facet defect of the embedded epitaxial layer.
In addition, the first dielectric material layer with stress is arranged in the first groove after the etching process of the SDB, the stress of the first dielectric material layer is selected to be capable of keeping the stress of the embedded epitaxial layer under the interaction with the embedded epitaxial layers adjacent to the two sides, the carrier mobility of the channel region can be improved due to the stress of the embedded epitaxial layer, and the performance of the device can be improved after the stress of the embedded epitaxial layer is kept.
In addition, after the first dielectric material layer is filled in the first groove, the steps of back etching the first dielectric material layer and filling the second polycrystalline silicon layer are added, and the metal gate replacement can be carried out on the second polycrystalline silicon layer while carrying out metal gate replacement on the pseudo gate structure in the subsequent metal gate replacement process, so that when the metal gate is mechanically ground, polished and flattened, an SDB (standard deviation) area is the same as a normal device, the flattening effect is better, the defects are fewer, and the process is easier to control, so that the method has the characteristics of simple process control and low process cost.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a layout structure of a FinFET corresponding to a method for manufacturing a single diffusion region cut-off structure in an existing FinFET;
fig. 2A-2C are cross-sectional views of a single-diffusion cutoff structure in a conventional FinFET taken along dashed line BB1 in fig. 1 at various steps in a method of fabricating the same;
FIG. 3 is a flow chart of a method of fabricating a single diffusion cutoff structure in a FinFET in accordance with an embodiment of the present invention;
fig. 4 is a layout structure of a FinFET corresponding to the method for manufacturing a single diffusion area cut-off structure in a FinFET according to the embodiment of the present invention;
fig. 5a 1-5L 1 are cross-sectional views taken along dashed line AA2 in fig. 4 at various steps in a method of fabricating a single-diffusion cutoff structure in a FinFET in accordance with an embodiment of the present invention;
fig. 5a 2-5L 2 are cross-sectional views of the single-diffused-region severing structure in the FinFET of the present invention at various steps along the dashed line BB2 in fig. 4;
Detailed Description
Fig. 3 is a flow chart illustrating a method of fabricating a single-diffusion cutoff structure in a FinFET in accordance with an embodiment of the present invention; as shown in fig. 4, the layout structure of the FinFET corresponds to the method for manufacturing the single diffusion region cut-off structure in the FinFET of the present invention; fig. 5a 1-5L 1 show cross-sectional views along the dashed line AA2 in fig. 4 at steps of a method for fabricating a single-diffused-region severing structure in a FinFET in accordance with an embodiment of the present invention; fig. 5a2 to 5L2 show cross-sectional views of the single-diffused-region cut-off structure in the FinFET of the present invention at the steps along the dashed line BB2 in fig. 4; the manufacturing method of the single diffusion region cutting structure in the FinFET comprises the following steps:
firstly, a plurality of fins 201 are formed on a semiconductor substrate 201a, an isolation dielectric layer 204 is filled in a spaced area between the fins 201, and the top surface of the isolation dielectric layer 204 is lower than the top surface of the fins 201.
In the embodiment of the present invention, the semiconductor substrate 201a includes a silicon substrate or an SOI substrate.
The fin body 201 is formed by performing patterned etching on the semiconductor substrate 201 a. As shown in fig. 4, each of the fins 201 has a strip structure.
The isolation medium layer 204 is an oxide layer and is formed by deposition through an FCVD (plasma chemical vapor deposition) process; after the isolation dielectric layer 204 is deposited, the method further includes chemically grinding and etching the isolation dielectric layer 204, so that the top surface of the isolation dielectric layer 204 is etched back to be lower than the top surface of the fin 201.
Preferably, the forming process of the fin 201 includes the following sub-steps:
as shown in fig. 5a1 and 5a2, a hard mask layer 301 is formed on the surface of the semiconductor substrate 201a, the hard mask layer 301 being formed by stacking an oxide layer 301a, a nitride film 301b, and an oxide film 301 c.
Patterning the hard mask layer 301, wherein after patterning, the interval region of the fin body 201 is opened, and the hard mask layer 301 in the formation region of the fin body 201 is reserved; the open area of the hard mask layer 301 is defined by a photolithography process.
And then, etching the semiconductor substrate 201a by taking the hard mask layer 301 as a mask to form the fin body 201.
As shown in fig. 5B1 and fig. 5B2, the isolation dielectric layer 4 is formed by deposition through an FCVD process; a step of forming a linear oxide (liner oxide) may also be included before the formation of the isolation dielectric layer 4.
As shown in fig. 5C1 and fig. 5C2, a chemical mechanical polishing process is performed with the nitride film 301b as a stop layer, and after the chemical mechanical polishing process is completed, the top surface of the isolation dielectric layer 4 is flush with the top surface of the nitride film 301 b.
As shown in fig. 5D1 and 5D2, the nitride film 301b is removed.
As shown in fig. 5E1 and 5E2, etching back the isolation dielectric layer 204 etches back the top surface of the isolation dielectric layer 204 below the top surface of the fin 201. The oxide film 301a on the top surface of the fin 201 is also removed.
Step two, as shown in fig. 5F1 and fig. 5F2, forming a dummy gate structure, wherein in the gate formation region, the dummy gate structure covers the side surfaces and the top surface of the fin body 201; the dummy gate structure is formed by overlapping a first gate dielectric layer and a first polysilicon gate 202. Only the first polysilicon gate 202 is shown in fig. 4, 5F1, and 5F2, and the first gate dielectric layer is not shown.
The first gate dielectric layer comprises a gate oxide layer.
A first hard mask layer 302 is further formed on the top surface of the first polysilicon gate 202; the forming process of the dummy gate structure comprises the following sub-steps:
the first gate dielectric layer, the first polysilicon gate 202, and the first hard mask layer 302 are sequentially formed.
The first hard mask layer 302 is patterned, so that the first hard mask layer 302 in the gate formation region is removed and the first hard mask layer 302 outside the gate formation region remains.
And etching the first polysilicon gate 202 and the first gate dielectric layer by using the first hard mask layer 302 as a mask to form the dummy gate structure.
As shown in fig. 4, in a top view, the dummy gate structure has a stripe structure, and the stripe structure of the dummy gate structure is perpendicular to the stripe structure of the fin 201.
After the dummy gate structure is formed, a step of forming a side wall 205 on the side surface of the dummy gate structure is further included.
And step three, forming an embedded epitaxial layer in the fin body 201 on two sides of the pseudo gate structure.
As shown in fig. 5G1 and 5G2, step three includes the following sub-steps:
second grooves are formed in the fin body 201 on two sides of the dummy gate structure.
And carrying out epitaxial filling in the second grooves at two sides of the pseudo gate structure to form the embedded epitaxial layer.
The method also comprises the following steps after the embedded epitaxial layer is formed:
and performing source-drain injection to form a source region and a drain region in the embedded epitaxial layer on two sides of the pseudo gate structure respectively.
The embedded epitaxial layer is not visible on the corresponding cross-sectional structure of fig. 5G 1; the embedded epitaxial layer is shown only on the corresponding cross-sectional structure of fig. 5G 2.
The FinFET comprises an N-type FinFET and a P-type FinFET; the embedded epitaxial layer of the N-type FinFET is made of SiP, which corresponds to embedded SiP epitaxial layer 207 in fig. 5G 2; the embedded epitaxial layer of the P-type FinFET is SiGe, which corresponds to embedded SiGe epitaxial layer 206 in fig. 5G 2.
Step four, as shown in fig. 5G1 and fig. 5G2, a zero interlayer film 208 is formed, and a planarization process is performed to make the top surface of the zero interlayer film 208 and the top surface of the dummy gate structure even.
In the fourth step, the planarization process of the zero-layer interlayer film 208 includes a chemical mechanical polishing process and a back etching process; the top surface of the zero interlayer film 208 after the planarization process is flush with the top surface of the first hard mask layer 302 at the top of the dummy gate structure.
Before the formation of the zero interlayer film 208, a step of forming a contact etching stop layer is further included, and the top surface of the contact etching stop layer after the planarization process of the step four is flush with the top surface of the first hard mask layer 302 on the top of the dummy gate structure.
Step five, forming a process of the single diffusion region cutting structure, comprising the following sub-steps:
and 51, defining a forming area of the single diffusion area cutting structure by photoetching. As shown in fig. 4 and 5H2, the formation region of the single diffusion region cutting structure is shown by a dashed box 203. The formation region of the single diffusion region cutoff structure is not referred to in fig. 5H 1.
Step 52, as shown in fig. 5H2, etching the dummy gate structure in the formation region of the single diffusion region cutting structure and the material of the semiconductor substrate 201a of the fin body 201 at the bottom of the dummy gate structure to form a first groove.
Step 53, as shown in fig. 5I2, filling a first dielectric material layer 209 in the first groove, where the first dielectric material layer 209 has a stress and the stress of the embedded epitaxial layer is maintained by interaction between the stress energy of the first dielectric material layer 209 and the embedded epitaxial layer adjacent to both sides. The formation region of the single diffusion region cutoff structure is not referred to in fig. 5I 1.
Preferably, the material of the first dielectric material layer 209 is SiC or SiN.
Step 54, as shown in fig. 5I2, etching back the first dielectric material layer 209 to lower the top surface of the first dielectric material layer 209 and form a top sub-groove of the first groove above the first dielectric material layer 209. The bottom surface of the top sub-groove is equal to or higher than the top surface of the fin body 201, and the single diffusion region cutting structure is formed by the first dielectric material layer 209 after back etching.
Preferably, the depth of the top sub-groove of the first groove is 30nm to 50 nm.
Step 55, as shown in fig. 5J2, a second polysilicon layer 202a is filled in the top sub-groove of the first groove. The formation region of the single diffusion region cutoff structure is not referred to in fig. 5J 1.
And sixthly, performing a metal gate replacement process to replace each dummy gate structure with a metal gate structure and replace the second polysilicon layer 202a with a second metal gate structure.
The sub-steps of the metal gate replacement include:
removing each dummy gate structure and the second polysilicon layer 202 a;
a second gate dielectric layer (not shown) and a metal gate 202b are sequentially formed on the inner side surface of each dummy gate structure and the removed region of the second polysilicon layer 202 a.
Compared with the cut first SDB process adopted in the prior art, the cut last SDB process is adopted in the embodiment of the invention, namely the etching process of the SDB, namely the etching process of the step 52, is placed after the pseudo gate structure is formed, so that the embedded epitaxial layer can be formed before the etching process of the SDB, and the single diffusion region cutting structure can be prevented from generating adverse effects on the epitaxial growth of the embedded epitaxial layer so as to avoid the facet defect of the formed embedded epitaxial layer.
In addition, in the embodiment of the present invention, after the SDB etching process, the first dielectric material layer 209 having a stress in the first groove is provided, and the stress of the first dielectric material layer 209 is selected to be capable of maintaining the stress of the embedded epitaxial layer by interaction with the adjacent embedded epitaxial layers on both sides, and since the stress of the embedded epitaxial layer can improve the carrier mobility of the channel region, the performance of the device can be improved after the stress of the embedded epitaxial layer is maintained, for example, after the stress of the embedded epitaxial layer is maintained, the stress of the embedded epitaxial layer can be prevented from being released to lower the performance of the device, and the stress of the embedded epitaxial layer can be prevented from being increased unevenly to cause the uniformity deterioration of the performance of the device.
In addition, in the embodiment of the present invention, after the first dielectric material layer 209 is filled in the first groove, the step of etching back the first dielectric material layer 209 and filling the second polysilicon layer 202a is further added, and in the subsequent metal gate replacement process, the metal gate replacement can be performed on the second polysilicon layer 202a while performing the metal gate replacement on the dummy gate structure, so that when the metal gate is mechanically ground, polished and planarized, the SDB region has the same effect as a normal device, the planarization effect is better, the defects are fewer, and the process is easier to control, so the embodiment of the present invention further has the characteristics of simple process control and low process cost.
In addition, the etching process of the SDB provided by the embodiment of the invention is performed after the formation of the zero-layer interlayer film, and belongs to an interlayer film process ring, so that the etching process of the SDB is an etching process in a middle-stage process.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (16)
1. A manufacturing method of a single diffusion cutting structure in FinFET is characterized by comprising the following steps:
forming a plurality of fin bodies on a semiconductor substrate, wherein an isolation medium layer is filled in a spacing area between the fin bodies, and the top surface of the isolation medium layer is lower than that of the fin bodies;
forming a pseudo gate structure, wherein the pseudo gate structure covers the side surface and the top surface of the fin body in a gate forming region; the pseudo gate structure is formed by overlapping a first gate dielectric layer and a first polysilicon gate;
step three, forming an embedded epitaxial layer in the fin bodies on two sides of the pseudo gate structure;
forming a zero-layer interlayer film, and performing a planarization process to enable the top surface of the zero-layer interlayer film to be level with the top surface of the pseudo gate structure;
step five, forming a process of the single diffusion region cutting structure, comprising the following sub-steps:
step 51, defining a forming area of the single diffusion area cutting structure by photoetching;
step 52, etching the dummy gate structure in the forming region of the single diffusion region cutting structure and the semiconductor substrate material of the fin body at the bottom of the dummy gate structure to form a first groove;
step 53, filling a first dielectric material layer in the first groove, wherein the first dielectric material layer has stress, and the stress of the embedded epitaxial layer is maintained by the interaction between the stress energy of the first dielectric material layer and the adjacent embedded epitaxial layers at two sides;
step 54, back-etching the first dielectric material layer to lower the top surface of the first dielectric material layer and form a top sub-groove of the first groove above the first dielectric material layer, where the bottom surface of the top sub-groove is equal to or higher than the top surface of the fin body, and the back-etched first dielectric material layer forms the single diffusion area cutting structure;
step 55, filling a second polysilicon layer in the top sub-groove of the first groove;
and sixthly, performing a metal gate replacement process to replace each pseudo gate structure with a metal gate structure and replace the second polycrystalline silicon layer with a second metal gate structure.
2. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 1, wherein: the semiconductor substrate includes a silicon substrate or an SOI substrate.
3. The method of fabricating a single-diffusion cutoff structure in a FinFET of claim 2, wherein: in the first step, the isolation medium layer is an oxide layer and is formed by deposition through an FCVD (plasma chemical vapor deposition) process; after the isolation medium layer is deposited, the isolation medium layer is chemically ground and etched, so that the top surface of the isolation medium layer is etched back to be lower than the top surface of the fin body.
4. The method of fabricating a single-diffusion cutoff structure in a FinFET of claim 2, wherein: in the first step, the fin body is formed by performing patterned etching on the semiconductor substrate.
5. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 4, wherein: each fin body is of a strip-shaped structure.
6. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 1, wherein: the first gate dielectric layer comprises a gate oxide layer.
7. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 5, wherein: in the second step, a first hard mask layer is further formed on the top surface of the first polysilicon gate; the forming process of the dummy gate structure comprises the following sub-steps:
sequentially forming the first gate dielectric layer, the first polysilicon gate and the first hard mask layer;
carrying out graphical etching on the first hard mask layer to remove the first hard mask layer in the grid forming area and keep the first hard mask layer outside the grid forming area;
and etching the first polysilicon gate and the first gate dielectric layer by taking the first hard mask layer as a mask to form the pseudo gate structure.
8. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 7, wherein: on a plane of depression, the pseudo grid electrode structure is of a strip-shaped structure, and the strip-shaped structure of the pseudo grid electrode structure is perpendicular to the strip-shaped structure of the fin body.
9. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 7, wherein: in the second step, after the pseudo gate structure is formed, a step of forming a side wall on the side face of the pseudo gate structure is further included.
10. The method of fabricating a single-diffusion cutoff structure in a FinFET of claim 9, wherein: the third step comprises the following sub-steps:
forming second grooves in the fin bodies on two sides of the pseudo gate structure;
and carrying out epitaxial filling in the second grooves at two sides of the pseudo gate structure to form the embedded epitaxial layer.
11. The method of fabricating a single-diffusion cutoff structure in a FinFET of claim 10, wherein: in the third step, after the formation of the embedded epitaxial layer, the method further comprises the following steps:
and performing source-drain injection to form a source region and a drain region in the embedded epitaxial layer on two sides of the pseudo gate structure respectively.
12. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 7, wherein: in the fourth step, the planarization process of the zero-layer interlayer film comprises a chemical mechanical polishing process and a back etching process; and after the planarization process, the top surface of the zero layer interlayer film is flush with the top surface of the first hard mask layer on the top of the pseudo gate structure.
13. The method of fabricating a single-diffusion cutoff structure in a FinFET of claim 12, wherein: and before the zero interlayer film is formed, a step of forming a contact etching stop layer is further included, and the top surface of the contact etching stop layer after the planarization process in the step four is flush with the top surface of the first hard mask layer on the top of the pseudo gate structure.
14. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 1, wherein: the FinFETs comprise N-type FinFETs and P-type FinFETs;
the material of the embedded epitaxial layer of the N-type FinFET comprises SiP;
the material of the embedded epitaxial layer of the P-type FinFET comprises SiGe.
15. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 1, wherein: in step 53, the material of the first dielectric material layer is SiC or SiN.
16. The method of fabricating a single-diffusion cutoff structure in a FinFET in claim 1, wherein: in step 54, the depth of the top sub-groove of the first groove is 30nm to 50 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110291474.6A CN113130402A (en) | 2021-03-18 | 2021-03-18 | Manufacturing method of single diffusion region cutting structure in FinFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110291474.6A CN113130402A (en) | 2021-03-18 | 2021-03-18 | Manufacturing method of single diffusion region cutting structure in FinFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113130402A true CN113130402A (en) | 2021-07-16 |
Family
ID=76773552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110291474.6A Pending CN113130402A (en) | 2021-03-18 | 2021-03-18 | Manufacturing method of single diffusion region cutting structure in FinFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113130402A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9412616B1 (en) * | 2015-11-16 | 2016-08-09 | Globalfoundries Inc. | Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products |
| US9570442B1 (en) * | 2016-04-20 | 2017-02-14 | Qualcomm Incorporated | Applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure |
| US20180006035A1 (en) * | 2016-06-30 | 2018-01-04 | Qualcomm Incorporated | Fin field effect transistor (fet) (finfet) complementary metal oxide semiconductor (cmos) circuits employing single and double diffusion breaks for increased performance |
| CN110323267A (en) * | 2018-03-29 | 2019-10-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110828569A (en) * | 2018-08-14 | 2020-02-21 | 三星电子株式会社 | Semiconductor device including diffusion interruption region |
| CN110875191A (en) * | 2019-11-28 | 2020-03-10 | 上海华力集成电路制造有限公司 | Method for manufacturing fin type transistor |
-
2021
- 2021-03-18 CN CN202110291474.6A patent/CN113130402A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9412616B1 (en) * | 2015-11-16 | 2016-08-09 | Globalfoundries Inc. | Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products |
| US9570442B1 (en) * | 2016-04-20 | 2017-02-14 | Qualcomm Incorporated | Applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure |
| US20180006035A1 (en) * | 2016-06-30 | 2018-01-04 | Qualcomm Incorporated | Fin field effect transistor (fet) (finfet) complementary metal oxide semiconductor (cmos) circuits employing single and double diffusion breaks for increased performance |
| CN110323267A (en) * | 2018-03-29 | 2019-10-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110828569A (en) * | 2018-08-14 | 2020-02-21 | 三星电子株式会社 | Semiconductor device including diffusion interruption region |
| CN110875191A (en) * | 2019-11-28 | 2020-03-10 | 上海华力集成电路制造有限公司 | Method for manufacturing fin type transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9437597B2 (en) | Static random access memory (SRAM) device with FinFET transistors | |
| US8603893B1 (en) | Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates | |
| US8513078B2 (en) | Structure and method for fabricating fin devices | |
| US8222102B2 (en) | Methods of forming field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells | |
| US20090294840A1 (en) | Methods of providing electrical isolation and semiconductor structures including same | |
| CN102751229B (en) | Fleet plough groove isolation structure, its manufacture method and the device based on this structure | |
| US9620506B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region | |
| KR20100049621A (en) | Method to fabricate adjacent silicon fins of differing heights | |
| US9214529B2 (en) | Fin Fet device with independent control gate | |
| TW201909282A (en) | Semiconductor device and method of forming the same | |
| US20150123211A1 (en) | NARROW DIFFUSION BREAK FOR A FIN FIELD EFFECT (FinFET) TRANSISTOR DEVICE | |
| US20180277648A1 (en) | Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling | |
| CN111986995A (en) | Semiconductor device and method of forming the same | |
| KR102426245B1 (en) | Semiconductor device and method | |
| CN110875191A (en) | Method for manufacturing fin type transistor | |
| TWI435373B (en) | Fully depleted soi device with buried doped layer | |
| US10008496B1 (en) | Method for forming semiconductor device having continuous fin diffusion break | |
| CN113130402A (en) | Manufacturing method of single diffusion region cutting structure in FinFET | |
| CN103187280A (en) | Manufacturing method of fin type field effect transistor | |
| CN113506744B (en) | Manufacturing method of fin field effect transistor | |
| US20230132891A1 (en) | Method for Manufacturing Isolation Structure of Hybrid Epitaxial Area and Active Area in FDSOI | |
| KR100504440B1 (en) | Method for fabricating of semiconductor device | |
| CN115083913A (en) | Method for manufacturing fin field effect transistor | |
| CN114121808A (en) | Manufacturing method of single diffusion region cutting structure in FinFET | |
| TW202310064A (en) | Method of fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |