CN113506744B - Manufacturing method of fin field effect transistor - Google Patents
Manufacturing method of fin field effect transistor Download PDFInfo
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- CN113506744B CN113506744B CN202110685187.3A CN202110685187A CN113506744B CN 113506744 B CN113506744 B CN 113506744B CN 202110685187 A CN202110685187 A CN 202110685187A CN 113506744 B CN113506744 B CN 113506744B
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- 230000005669 field effect Effects 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 47
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 6
- 239000010432 diamond Substances 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims description 16
- 238000001039 wet etching Methods 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 116
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a manufacturing method of a fin field effect transistor, which comprises the following steps: step one, forming a fin body on a semiconductor substrate. Step two, forming a first grid structure formed by superposing a first grid dielectric layer and a first polysilicon gate; forming a source region and a drain region, wherein the method comprises the following steps: and step 31, forming a first side wall and a second side wall on the side surfaces of the first polysilicon gate and the fin body outside the gate forming area respectively. And step 32, performing first fin etching self-alignment on the fin to form a groove with a U-shaped appearance. And step 33, etching the dielectric layer to remove part of the material layer of the second side wall exposed by the first side surface and the second side surface of the groove. Step 34, carrying out second fin etching on the fin body to expand the volume of the groove and form a diamond shape; and 35, filling the epitaxial layer in the groove to form an embedded epitaxial layer and carrying out source-drain doping. The invention can enlarge the volume of the embedded epitaxial layer and simultaneously prevent the source drain epitaxy and the gate bridging, thereby maintaining the improvement of the performance of the device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a method of fabricating a fin field effect transistor (Fin Field Effect Transistor, finFET).
Background
With the development of semiconductor process technology, the gate width is continuously reduced, and the conventional planar CMOS device cannot meet the requirements of the device, such as the control of short channel effect. For technology nodes below 20nm, the fin field effect transistor structure has better electrical performance.
An embedded epitaxial layer is also introduced into the source region and the drain region of the fin field effect transistor, and the stress of the channel region is changed through the embedded epitaxial layers of the source region and the drain region, so that the carrier mobility of the channel region and the performance of the device can be improved. Starting at the 90nm technology node, an embedded SiGe epitaxial layer is introduced to improve the performance of the PMOS; and at the 14nm technology node, an embedded SiP epitaxial layer is introduced to improve the performance of NMOS. In order to better change the stress of the channel region, the volume of the embedded epitaxial layer is generally required to be increased, and after the volume of the embedded epitaxial layer is increased, the risk of bridging (bridge) between the embedded epitaxial layers of the source region and the drain region, namely, the source drain epitaxial layer and the gate is generated, so that the performance of the device is affected, and the performance of the device is easily degraded.
Disclosure of Invention
The invention aims to provide a manufacturing method of a fin field effect transistor, which can enlarge the volume of an embedded epitaxial layer and prevent source drain epitaxy and gate bridging, so that the performance of a device can be improved.
In order to solve the technical problems, the manufacturing method of the fin field effect transistor provided by the invention comprises the following steps:
forming fin bodies on a semiconductor substrate, wherein a spacing area is formed between the fin bodies, an isolation medium layer is filled in the spacing area, and the top surface of the isolation medium layer is lower than the top surface of the fin bodies.
And step two, forming a first gate structure, wherein the first gate structure is formed by superposing a first gate dielectric layer and a first polysilicon gate in a gate forming area.
A first hard mask layer is formed on the top surface of the first polysilicon gate, and the gate forming region is defined by the first hard mask layer.
Forming a source region and a drain region in the fin body at two sides of the first gate structure, wherein the method comprises the following sub-steps:
and step 31, forming a first side wall on the side surface of the first polysilicon gate and simultaneously forming a second side wall on the side surface of the fin body outside the gate forming area.
And step 32, performing first fin etching on the fin body by taking the first hard mask layer, the first side wall and the second side wall as masks so as to form grooves with U-shaped morphology on two sides of the first polysilicon gate in a self-aligned manner.
And step 33, etching the dielectric layer to remove part of the material layer of the second side wall exposed by the first side surface and the second side surface of the groove, thereby enlarging the volume of the groove.
The third side surface of the groove and the side surface of the first side wall are self-aligned, so that the first gate dielectric layer at the bottom of the first polysilicon gate is not consumed, and the bottom of the first polysilicon gate is prevented from being exposed in the groove.
Step 34, performing a second fin etching on the fin body by taking the first hard mask layer, the first side wall and the second side wall as masks so as to expand the volume of the groove and make the shape of the groove diamond; the enlarged groove extends to the bottom of the first side surface and is isolated by the first gate dielectric layer and the first polysilicon gate.
And 35, filling an epitaxial layer in the groove to form an embedded epitaxial layer, and carrying out source-drain doping in the embedded epitaxial layer to form the source region and the drain region.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
The further improvement is that the isolation dielectric layer adopts a shallow trench isolation oxide layer.
In a further improvement, the first hard mask layer is formed by laminating a first oxide layer and a first nitride layer.
In a further improvement, in step 31, the forming steps of the first sidewall and the second sidewall include:
and fully depositing a side wall material layer.
And carrying out comprehensive etching on the side wall material layer to form the first side wall and the second side wall simultaneously.
The side wall material layer comprises an oxide layer, a low-K material layer and a nitride layer which are sequentially overlapped.
In a further improvement, in step 33, the dielectric layer is etched to remove the oxide layer in the second sidewall.
In a further improvement, in the second step, the first gate dielectric layer includes a gate oxide layer or a high dielectric constant layer.
A further improvement is that the first fin body etch uses a dry etch.
The dielectric layer is etched by wet etching.
The second fin body etching is performed by wet etching.
The further improvement is that TMAH is adopted in the etching liquid of the wet etching of the second fin body etching.
Further improvements include the fin field effect transistor comprising an N-type fin field effect transistor and a P-type fin field effect transistor.
Further, when the fin field effect transistor is an N-type fin field effect transistor, the embedded epitaxial layer is an embedded SiP epitaxial layer, and the source region and the drain region are both heavily doped with N-type.
In a further improvement, when the fin field effect transistor is a P-type fin field effect transistor, the embedded epitaxial layer is an embedded SiGe epitaxial layer, and the source region and the drain region are both P-type heavily doped.
In a further improvement, in the first step, the fin bodies are formed by etching the semiconductor substrate, and each fin body is in a strip-shaped structure parallel to each other on a top view.
In the second step, the first gate structures also extend to the surface of the isolation medium layer of the interval region, and the first gate structures on the same row are connected together to form a gate structure row; the gate structure rows and the fin are perpendicular to each other in a top view.
According to the invention, a special setting is made for the groove etching process of the embedded epitaxial layer, after the groove with the U-shaped appearance is formed by the first fin body etching, the groove is not directly expanded into a diamond type by the second fin body etching, but the medium layer etching is carried out to remove part of the material layers of the side walls, namely the second side walls, of the two sides of the fin body exposed on the inner side surface of the groove, so that the groove can be further expanded, the volume of the embedded epitaxial layer can be increased, and the performance of a device can be improved; meanwhile, the dielectric layer etching is performed before the second fin body etching, so that the defect that the bottom surface of the first polysilicon gate is easily exposed in the groove when the dielectric layer etching is performed after the second fin body etching can be eliminated, and finally the source drain epitaxy and the gate bridging can be prevented.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a flowchart of a method of fabricating a finfet in accordance with an embodiment of the present invention;
fig. 2 is a plan view of a finfet formed by a method of fabricating a finfet in accordance with an embodiment of the present invention;
fig. 3A, 4A, 5A, 6A and 7A are cross-sectional view of the fin field effect transistor according to the embodiment of the present invention, taken along the dashed line AA in fig. 2;
fig. 3B, 4B, 5B, 6B and 7B are cross-sectional view of the fin field effect transistor according to the embodiment of the present invention, taken along the dashed line BB in fig. 2;
fig. 3C is a cross-sectional view of the back edge of the fin field effect transistor at the dashed line CC in fig. 2 after forming the sidewall according to the method of manufacturing the fin field effect transistor of the embodiment of the present invention;
fig. 3D is a cross-sectional view illustrating a portion DD in fig. 2 along a back edge of a sidewall formed by a method for fabricating a fin field effect transistor according to an embodiment of the present invention;
fig. 8A is a cross-sectional view of a conventional finfet fabrication method at the same location in fig. 6A after forming a diamond-shaped recess;
fig. 8B is a cross-sectional view of a conventional finfet fabrication method at the same location as fig. 7A after forming an embedded epi layer.
Detailed Description
Fig. 1 is a flowchart of a method for manufacturing a fin field effect transistor according to an embodiment of the present invention; fig. 2 is a plan view of a finfet formed by a method of fabricating a finfet in accordance with an embodiment of the present invention; as shown in fig. 3A, 4A, 5A, 6A and 7A, the method for manufacturing a fin field effect transistor according to the embodiment of the present invention is a cross-sectional structure diagram along the dashed line AA in fig. 2; as shown in fig. 3B, 4B, 5B, 6B and 7B, a cross-sectional view along a dashed line BB in fig. 2 is shown in the steps of the method for manufacturing a fin field effect transistor according to the embodiment of the present invention; fig. 3C is a schematic cross-sectional view of a broken line CC in fig. 2 after forming a sidewall in the method for manufacturing a fin field effect transistor according to the embodiment of the present invention; fig. 3D is a schematic cross-sectional view of the broken line DD in fig. 2 after forming the sidewall of the fin field effect transistor according to the method for manufacturing a fin field effect transistor of the embodiment of the present invention; the manufacturing method of the fin field effect transistor comprises the following steps:
referring to fig. 2 and 3C, a fin 201 is formed on a semiconductor substrate 201a, a space region is formed between the fins 201, an isolation dielectric layer 304 is filled in the space region, and a top surface of the isolation dielectric layer 304 is lower than a top surface of the fin 201.
In an embodiment of the present invention, the semiconductor substrate 201a includes a silicon substrate.
The isolation dielectric layer 304 is a shallow trench isolation oxide layer.
The fin 201 is formed by etching the semiconductor substrate 201a, and each fin 201 has a stripe-like structure parallel to each other in a plan view.
Referring to fig. 2 and 3C, a first gate structure is formed, where the first gate structure is formed by overlapping the first gate dielectric layer 301 and the first polysilicon gate 202 in the gate forming region.
A first hard mask layer 302 is formed on the top surface of the first polysilicon gate 202, and the gate formation region is defined by the first hard mask layer 302.
In the embodiment of the present invention, the first hard mask layer 302 is formed by stacking a first oxide layer and a first nitride layer.
The first gate dielectric layer 301 includes a gate oxide layer or a high dielectric constant layer.
The fin field effect transistor includes an N-type fin field effect transistor and a P-type fin field effect transistor. In fig. 2, a dashed box 203 corresponds to a formation region of one of the N-type finfet; dashed box 204 corresponds to a region where one of the P-type finfet is formed.
In fig. 3A, a cross-sectional structure diagram of a formation region of one of the P-type finfet along a broken line AA is shown. Fig. 3A shows a cross section of the first polysilicon gate 202 in the width direction, and the first hard mask layer 209 is formed on the top surface of the first polysilicon gate 202.
In fig. 3B, a cross-sectional structure diagram including two fins 201 along a dashed line BB is shown, and the first polysilicon gate 202 is not formed in the corresponding region in fig. 3B.
In fig. 3D, a cross-sectional structural view along the dashed line DD is shown including one of the first polysilicon gates 202;
a cross-section of the first polysilicon gate 202 in the width direction is also shown in fig. 3D, but the first polysilicon gate 202 is formed on the surface of the isolation dielectric layer 304 in fig. 3D, and the first polysilicon gate 202 is formed on the surface of the fin body 202 in fig. 3A.
The first gate structures further extend onto the surface of the isolation dielectric 304 of the spacer region, and each of the first gate structures on the same row are connected together and form a row of gate structures; the gate structure rows and the fin 201 are perpendicular to each other in a top view.
Step three, forming a source region and a drain region in the fin body 201 at two sides of the first gate structure, including the following sub-steps:
step 31, as shown in fig. 3A, a first sidewall 3031 is formed on a side surface of the first polysilicon gate 202; as shown in fig. 3B, a second sidewall 3032 is formed at the side of the fin 201 outside the gate formation region.
In this embodiment of the present invention, the forming steps of the first sidewall 3031 and the second sidewall 3032 include:
and fully depositing a side wall material layer.
And performing overall etching on the side wall material layer to form the first side wall 3031 and the second side wall 3032 simultaneously. The side wall material layer comprises an oxide layer 303a, a low-K material layer 303b and a nitride layer 303c which are sequentially stacked. The low-K material layer 303b can reduce the parasitic capacitance of the device.
In step 32, as shown in fig. 4A, the first hard mask layer 302, the first sidewall 3031 and the second sidewall 3032 are used as masks to perform a first fin 201 etching on the fin 201 to form a groove 305a with a U-shaped morphology in a self-aligned manner on two sides of the first polysilicon gate 202. The third and fourth sides of the groove 305a are shown in fig. 4A, and the first and second sides of the groove 305a are shown in fig. 4B.
In the embodiment of the present invention, the first fin 201 is etched by dry etching.
In step 33, as shown in fig. 5B, a dielectric layer etching is performed to remove a portion of the material layer of the second sidewall 3032 exposed on the first side and the second side of the recess 305a, so as to enlarge the volume of the recess 305a.
As shown in fig. 5A, the third side of the recess 305A and the side of the first sidewall 3031 are self-aligned so that the first gate dielectric layer 301 at the bottom of the first polysilicon gate 202 is not consumed and so that the bottom of the first polysilicon gate 202 is prevented from being exposed to the recess 305A.
In this embodiment, the dielectric layer etching is used to remove the oxide layer in the second sidewall 3032.
And the dielectric layer is etched by wet etching.
Step 34, as shown in fig. 6A and fig. 6B, performing a second etching on the fin 201 with the first hard mask layer 302, the first sidewall 3031 and the second sidewall 3032 as masks to expand the volume of the groove 305a and make the shape of the groove 305 after expansion diamond; the enlarged recess 305 extends to the bottom of the first side and is isolated from the first polysilicon gate 202 by the first gate dielectric layer 301.
In the embodiment of the present invention, the second fin 201 is etched by wet etching. Preferably, TMAH is used as the etching solution for the wet etching of the second fin 201.
Step 35, as shown in fig. 7A and fig. 7B, an epitaxial layer is filled in the groove 305a to form an embedded epitaxial layer 306, and source-drain doping is performed in the embedded epitaxial layer 306 to form the source region and the drain region.
When the finfet is an N-type finfet, the embedded epi layer 306 is an embedded SiP epi layer, and both the source and drain regions are heavily doped with N-type. The embedded SiP epitaxial layer is represented by reference numeral 205 alone, as shown in fig. 2.
When the finfet is a P-type finfet, the embedded epi layer 306 is an embedded SiGe epi layer, and both the source and drain regions are heavily P-doped. The embedded SiGe epitaxial layer is represented solely by reference numeral 206, as shown in fig. 2.
When the N-type finfet and the P-type finfet are integrated on the semiconductor substrate 201a at the same time, a source and a drain of the N-type finfet and a source and a drain of the P-type finfet are sequentially formed in a third step.
When the source and drain regions of the N-type finfet are formed, the formation region of the N-type finfet is opened and the formation region of the P-type finfet is simultaneously covered in step 32.
When forming the source and drain regions of the P-type finfet, the forming region of the P-type finfet is opened while simultaneously covering the forming region of the N-type finfet in step 32.
After the third step is completed, the following steps are further included:
forming a Contact Etch Stop Layer (CESL);
forming a zeroth layer interlayer film;
and performing a chemical mechanical polishing process to level the surfaces of the zeroth layer interlayer film and the contact etching stop layer with the first polysilicon gate 202, and simultaneously removing the first hard mask layer 209 on the surface of the first polysilicon gate 202.
And if the first gate structure is a final gate structure, performing a subsequent metal interconnection process after the first gate structure is exposed.
If the first gate structure is used as a dummy gate structure, a metal gate replacement process is further performed, where the metal gate replacement process includes: and removing the first gate structure, and forming a second gate structure in the first gate structure removing area, wherein the second gate structure is formed by superposing a second gate dielectric layer and a metal gate, and the second gate dielectric layer comprises a high dielectric material layer. Thereafter, a subsequent metal interconnect process is performed.
In the embodiment of the invention, the etching process of the groove 305a of the embedded epitaxial layer 306 is specially set, after the groove 305a with the U-shaped appearance is formed by etching the fin body 201 for the first time, the groove 305a is not directly etched for the second time to expand into a diamond shape, but the dielectric layer is etched to remove part of the material layers of the side walls on the two sides of the fin body 201 exposed on the inner side surface of the groove 305a, namely the second side wall 3032, so that the groove 305a can be further expanded, the volume of the embedded epitaxial layer 306 can be increased, and the performance of a device can be improved; meanwhile, the dielectric layer etching in the embodiment of the invention is performed before the second fin body 201 etching, so that the defect that the bottom surface of the first polysilicon gate 202 is easily exposed in the groove 305a when the dielectric layer etching is performed after the second fin body 201 etching can be eliminated, and finally the source drain epitaxy and the gate bridging can be prevented, so that the embodiment of the invention can enlarge the volume of the embedded epitaxial layer 306 and simultaneously prevent the source drain epitaxy and the gate bridging, thereby maintaining the improvement of the performance of the device.
To further illustrate that the embodiments of the present invention can prevent source-drain epitaxy and gate bridging, an opposite example will be described below: as shown in fig. 8A, a cross-sectional structure diagram of a conventional finfet manufacturing method at the same position in fig. 6A after forming a diamond-shaped recess is shown; as shown in fig. 8B, a cross-sectional structure diagram of a conventional method for manufacturing a fin field effect transistor at the same position in fig. 7A after forming an embedded epi layer; compared with the manufacturing method of the fin field effect transistor in the embodiment of the invention, in the existing manufacturing method of the fin field effect transistor, the dielectric layer is etched after the diamond-shaped groove 405 is formed; because the diamond-shaped groove 405 is etched twice, namely, the first etching is dry etching for forming the U-shaped morphology and the second etching is etching for forming the diamond-shaped morphology on the base gate of the U-shaped morphology, and the second etching is usually wet etching; as shown in fig. 8A, after two etches, the bottoms of some of the recesses 405 extend laterally to the bottom of the polysilicon gate 202; in this way, the gate dielectric layer 30 at the bottom of the polysilicon gate 202 is removed during the etching of the dielectric layer, and the removed area of the gate dielectric layer 301 forms a gap 4051.
Thus, after the embedded epitaxial growth shown in fig. 8A, the embedded epitaxial layer 406 also extends into the gap 4051 to form the epitaxial layer 4061, and the epitaxial layer 4061 realizes bridging between the embedded epitaxial layer 406 and the polysilicon gate 202; the embodiment of the invention can eliminate the bridging between the source drain epitaxy and the grid electrode.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. A method of fabricating a fin field effect transistor, comprising:
forming fin bodies on a semiconductor substrate, wherein a spacing area is formed between the fin bodies, an isolation medium layer is filled in the spacing area, and the top surface of the isolation medium layer is lower than the top surface of the fin bodies;
step two, forming a first gate structure, wherein the first gate structure is formed by superposing a first gate dielectric layer and a first polysilicon gate in a gate forming area;
a first hard mask layer is formed on the top surface of the first polysilicon gate, and the gate forming area is defined by the first hard mask layer;
forming a source region and a drain region in the fin body at two sides of the first gate structure, wherein the method comprises the following sub-steps:
step 31, forming a first side wall on the side surface of the first polysilicon gate and simultaneously forming a second side wall on the side surface of the fin body outside the gate forming area;
the side wall material layers of the first side wall and the second side wall comprise an oxide layer, a low-K material layer and a nitride layer which are sequentially overlapped;
step 32, performing first fin etching on the fin body by taking the first hard mask layer, the first side wall and the second side wall as masks so as to form grooves with U-shaped morphology in a self-aligned mode on two sides of the first polysilicon gate;
step 33, etching a dielectric layer to remove part of the material layer of the second side wall exposed by the first side surface and the second side surface of the groove, thereby enlarging the volume of the groove;
the third side surface of the groove and the side surface of the first side wall are self-aligned, so that the first gate dielectric layer at the bottom of the first polysilicon gate is not consumed, and the bottom of the first polysilicon gate is prevented from being exposed in the groove;
in step 33, the dielectric layer is etched to remove the oxide layer in the second sidewall;
step 34, performing a second fin etching on the fin body by taking the first hard mask layer, the first side wall and the second side wall as masks so as to expand the volume of the groove and make the shape of the groove diamond; the third side surface of the enlarged groove extends to the bottom of the first polysilicon gate and is isolated from the first polysilicon gate through the first gate dielectric layer;
and 35, filling an epitaxial layer in the groove to form an embedded epitaxial layer, and carrying out source-drain doping in the embedded epitaxial layer to form the source region and the drain region.
2. The method of manufacturing a fin field effect transistor of claim 1, wherein: the semiconductor substrate includes a silicon substrate.
3. The method of manufacturing a fin field effect transistor of claim 1, wherein: the isolation dielectric layer adopts a shallow trench isolation oxide layer.
4. The method of manufacturing a fin field effect transistor of claim 1, wherein: the first hard mask layer is formed by laminating a first oxide layer and a first nitride layer.
5. The method of manufacturing a fin field effect transistor of claim 1, wherein: in step 31, the forming steps of the first sidewall and the second sidewall include:
comprehensively depositing a side wall material layer;
and carrying out comprehensive etching on the side wall material layer to form the first side wall and the second side wall simultaneously.
6. The method of manufacturing a fin field effect transistor of claim 1, wherein: in the second step, the first gate dielectric layer includes a gate oxide layer or a high dielectric constant layer.
7. The method of manufacturing a fin field effect transistor of claim 1, wherein: and the first fin body etching adopts dry etching.
8. The method of manufacturing a fin field effect transistor of claim 1, wherein: and the dielectric layer is etched by wet etching.
9. The method of manufacturing a fin field effect transistor of claim 2, wherein: and the second fin body etching adopts wet etching.
10. The method of manufacturing a finfet in claim 9, wherein: and the etching liquid of the wet etching of the second fin body etching adopts TMAH.
11. The method of manufacturing a fin field effect transistor of claim 1, wherein: the fin field effect transistor includes an N-type fin field effect transistor and a P-type fin field effect transistor.
12. The method of manufacturing a finfet in claim 11, wherein: when the fin field effect transistor is an N-type fin field effect transistor, the embedded epitaxial layer is an embedded SiP epitaxial layer, and the source region and the drain region are both heavily doped with N-type.
13. The method of manufacturing a finfet in claim 11, wherein: when the fin field effect transistor is a P-type fin field effect transistor, the embedded epitaxial layer is an embedded SiGe epitaxial layer, and the source region and the drain region are both P-type heavily doped.
14. The method of manufacturing a fin field effect transistor of claim 1, wherein: in the first step, the fin bodies are formed by etching the semiconductor substrate, and each fin body is in a strip-shaped structure parallel to each other on a top view.
15. The method of manufacturing a finfet in claim 14, wherein: in the second step, the first gate structures further extend to the surface of the isolation medium layer of the interval region, and the first gate structures on the same row are connected together to form a gate structure row; the gate structure rows and the fin are perpendicular to each other in a top view.
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