CN113130298A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN113130298A CN113130298A CN202110388636.8A CN202110388636A CN113130298A CN 113130298 A CN113130298 A CN 113130298A CN 202110388636 A CN202110388636 A CN 202110388636A CN 113130298 A CN113130298 A CN 113130298A
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- 238000000034 method Methods 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 143
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 122
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 122
- 230000003647 oxidation Effects 0.000 claims abstract description 66
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 66
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 51
- 230000008569 process Effects 0.000 claims abstract description 44
- 238000005468 ion implantation Methods 0.000 claims abstract description 29
- 239000002344 surface layer Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 23
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910017109 AlON Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- CMIHHWBVHJVIGI-UHFFFAOYSA-N gadolinium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Gd+3].[Gd+3] CMIHHWBVHJVIGI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052714 tellurium Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 238000000348 solid-phase epitaxy Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910002091 carbon monoxide Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910018540 Si C Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000002922 simulated annealing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a silicon carbide layer is formed on the substrate; bombarding the silicon carbide layer by adopting ion implantation so as to enable the surface layer of the silicon carbide layer to be amorphous, and forming an amorphous layer of silicon carbide; performing an oxidation process to oxidize the amorphous layer of silicon carbide to a silicon oxide layer. Bombarding the silicon carbide layer by adopting ion implantation to ensure that the surface layer of the silicon carbide layer is amorphized to form an amorphous layer of the silicon carbide, and then carrying out an oxidation process on the amorphous layer of the silicon carbide to generate the silicon oxide layer. Compared with a compact silicon carbide layer, the amorphous layer of the silicon carbide has a faster oxidation speed when being subjected to an oxidation process, and the amorphous layer of the silicon carbide is grown again through solid phase epitaxy when being subjected to the oxidation process, so that the interface quality of the SiC and the silicon oxide can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a method for manufacturing a semiconductor device.
Background
Silicon carbide (SiC) materials have become a hot point of research for new semiconductor devices due to their excellent properties in extreme conditions such as high temperature, strong acid and strong base, and radiation. The SiC can be applied to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and can be oxidized into silicon Oxide to be used as a gate dielectric in the MOSFET.
However, in the process of oxidizing SiC into silicon oxide, the formed silicon oxide closes the pores, prevents oxygen from entering the material, and forms protective oxidation, so that the oxidation rate of the SiC material is relatively slow, a thick high-quality oxide layer is difficult to grow, the interface quality of SiC and silicon oxide is poor, and the channel mobility and the on-resistance of the MOSFET device are severely reduced due to the high-density interface state and poor interface quality. Therefore, there is an urgent need for a method for manufacturing a semiconductor device, which increases the oxidation rate of SiC material and improves the quality of the interface between SiC and silicon oxide.
Disclosure of Invention
In view of the above, an object of the present application is to provide a method for manufacturing a semiconductor device, which increases the oxidation rate of the SiC material and improves the quality of the interface between SiC and silicon oxide.
In order to achieve the purpose, the technical scheme is as follows:
a method of manufacturing a semiconductor device, the method comprising:
providing a substrate, wherein a silicon carbide layer is formed on the substrate;
bombarding the silicon carbide layer by adopting ion implantation so as to enable the surface layer of the silicon carbide layer to be amorphous, and forming an amorphous layer of silicon carbide;
performing an oxidation process to oxidize the amorphous layer of silicon carbide to a silicon oxide layer.
Optionally, the thickness of the amorphous layer of silicon carbide is controlled by ion implantation according to the desired thickness of the silicon oxide layer.
Optionally, the thickness of the amorphous layer of silicon carbide ranges from 5 nm to 200 nm.
Optionally, the energy range of the ion implantation is 20keV-1MeV, and the dose range of the ion implantation is 1e14-1e17/cm2。
Optionally, the bombarded ion has an atomic mass greater than or equal to the atomic mass of Si.
Optionally, the bombarded ion is at least one of Si, Ge, Sn, As, Ga, In, P, Te, or Bi.
Optionally, the oxidation process is at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, oxygen-introduced oxidation or nitrogen oxide-introduced oxidation.
Optionally, the method further includes:
and carrying out an annealing process on the silicon oxide layer, wherein the introduced gas is at least one of nitrogen, argon or nitrogen oxide during the annealing process.
Optionally, the method further includes:
forming other oxide layers on the silicon oxide layer, wherein the other oxide layers are HfO2、Al2O3、AlON、AlN、HfAlON、Y2O3、LaSiOx、Gd2O3、TiO2、Ta2O5At least one of (1).
Optionally, the method further includes:
and forming a gate on the silicon oxide layer.
The embodiment of the application provides a manufacturing method of a semiconductor device, which is characterized in that ion implantation is adopted to bombard a silicon carbide layer, so that the surface layer of the silicon carbide layer is amorphized to form an amorphous layer of silicon carbide, and then the amorphous layer of the silicon carbide is subjected to an oxidation process to generate a silicon oxide layer. Compared with a compact silicon carbide layer, the amorphous layer of the silicon carbide has a faster oxidation speed when being subjected to an oxidation process, and the amorphous layer of the silicon carbide is grown again through solid phase epitaxy when being subjected to the oxidation process, so that the interface quality of the SiC and the silicon oxide can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 shows a schematic flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present application;
fig. 2-6 show schematic device structures during the formation of a semiconductor device according to a fabrication method of an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Currently, silicon carbide (SiC) materials have the advantages of wide band gap, high intrinsic temperature, high thermal conductivity, high insulating strength, and the like, and thus can play an important role in extreme conditions such as high temperature, strong acid, strong base, and radiation, and become a research hotspot of new semiconductor devices. The SiC can be applied to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and can be oxidized into silicon Oxide to be used as a gate dielectric in the MOSFET.
However, in the process of oxidizing SiC to silicon oxide, a higher oxidation temperature, possibly greater than 1100 ℃, is required during the oxidation due to the presence of C atoms. Compared with siliconOxidation to silicon oxide, oxidation of SiC to silicon oxide (SiO)2) In time, more oxygen is consumed and carbon monoxide (CO) is generated, and the oxidation mechanism is more complicated. In addition, when the oxidation process of SiC is carried out, the formed silicon oxide can seal air holes, oxygen is prevented from entering the material to form protective oxidation, and simultaneously, the escape of CO is blocked, so that the oxidation rate of the SiC material is relatively slow, a thicker high-quality oxide layer is difficult to grow, the interface quality of SiC and silicon oxide is poor, and the channel mobility and the on-resistance of the MOSFET device are seriously reduced due to the high-density interface state and the poor interface quality. Therefore, there is an urgent need for a method for manufacturing a semiconductor device, which increases the oxidation rate of SiC material and improves the quality of the interface between SiC and silicon oxide.
Based on the above technical problem, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method including: providing a substrate, wherein a silicon carbide layer is formed on the substrate; bombarding the silicon carbide layer by adopting ion implantation so as to enable the surface layer of the silicon carbide layer to be amorphous, and forming an amorphous layer of silicon carbide; performing an oxidation process to oxidize the amorphous layer of silicon carbide to a silicon oxide layer.
According to the manufacturing method of the semiconductor device, the silicon carbide layer is bombarded by adopting ion implantation, so that the surface layer of the silicon carbide layer is amorphized to form the amorphous layer of the silicon carbide, namely, Si-C bonds on the surface layer of the silicon carbide layer are broken by the ion implantation, the free energy of the surface layer of the silicon carbide layer is increased, the activity of the surface layer is higher, and the oxidation speed of the amorphous layer of the silicon carbide layer in the oxidation process is accelerated. Compared with a compact silicon carbide layer, the amorphous layer of the silicon carbide has a faster oxidation speed when being subjected to an oxidation process, and the amorphous layer of the silicon carbide is grown again through solid phase epitaxy when being subjected to the oxidation process, so that the interface quality of the SiC and the silicon oxide can be improved.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown, the method including the steps of:
s101, providing a substrate 100, wherein a silicon carbide layer 110 is formed on the substrate 100, as shown in fig. 2.
In the embodiment of the present application, the substrate 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In this embodiment, the substrate 100 is a silicon substrate.
A portion of a device structure, which may include an N-type device structure and/or a P-type device structure, may be a planar or a stereoscopic device structure, and the stereoscopic device structure may be a fin device or a nanowire wrap gate device, for example, has been formed on the substrate 100. In the embodiment of the present application, the N-type device structure may be an NMOS, the P-type device structure may be a PMOS, and the device structure at least includes a film layer under the gate dielectric layer.
In an embodiment of the present application, a silicon carbide layer 110 is formed on a substrate 100, as shown with reference to fig. 2. The silicon carbide layer 110, after being oxidized to silicon oxide, may serve as a gate dielectric layer for either an N-type device structure or a P-type device structure.
And S102, bombarding the silicon carbide layer 110 by adopting ion implantation to make the surface layer of the silicon carbide layer 110 amorphous to form an amorphous layer 120 of silicon carbide.
In the embodiment of the present application, the surface layer of the silicon carbide layer 110 is amorphized by a bombardment process of ion implantation, that is, the original crystalline structure of the surface layer of the silicon carbide layer 110 is destroyed by ion implantation, so that the silicon carbide layer is in an amorphous structure, that is, Si — C bonds of the surface layer of the silicon carbide layer are broken by ion implantation, and the free energy of the surface layer of the silicon carbide layer is increased, so that the activity of the surface layer is higher, and the oxidation speed of the amorphous layer of silicon carbide is accelerated when an oxidation process is performed on the surface layer.
Referring to fig. 3, a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure is shown, in which a surface layer of a silicon carbide layer 110 is amorphized by a bombardment process of ion implantation to form an amorphous layer 120 of silicon carbide.
In practical applications, the thickness of the amorphous layer 120 of silicon carbide may be controlled by ion implantation according to the thickness of silicon oxide required in the subsequent oxidation process, that is, at least the amorphous layer 120 of silicon carbide may be oxidized to silicon oxide in the subsequent oxidation process. As an example, the amorphous layer 120 of silicon carbide may have a thickness in the range of 5-200nm, and the oxidized silicon oxide may have a thickness in the range of 5-200 nm.
In the embodiment of the present application, the thickness of the formed amorphous layer 120 of silicon carbide may be controlled by controlling the energy or dose of the ion implantation, so as to obtain the desired thickness of silicon oxide when the amorphous layer 120 of silicon carbide is subsequently oxidized. As an example, the energy of the ion implantation ranges from 20keV to 1MeV, and the dose of the ion implantation ranges from 1e14 to 1e17/cm2。
In the embodiment of the present application, when the silicon carbide layer 110 is bombarded by ion implantation, the atomic mass of the bombarded ions is greater than or equal to the atomic mass of Si, so that Si — C bonds in the surface layer of the silicon carbide layer 110 can be broken to form an amorphous layer. Compared with the ion with smaller atomic mass, the ion with larger atomic mass can reduce the energy and dosage of ion implantation and reduce the cost. As an example, the bombarding ions may be at least one of Si, Ge, Sn, As, Ga, In, P, Te, or Bi.
S103, an oxidation process is performed to oxidize the amorphous layer 120 of silicon carbide into a silicon oxide layer 130, as shown in fig. 4.
In the embodiment of the present application, after obtaining the amorphous layer 120 of silicon carbide, the oxidation process is continued to be performed on the silicon carbide layer 110 and the amorphous layer 120 of silicon carbide, so as to oxidize the amorphous layer 120 of silicon carbide into the silicon oxide layer 130, and since Si — C bonds of the surface layer of the silicon carbide layer are broken during ion implantation, the free energy of the surface layer of the silicon carbide layer is increased, so that the activity of the surface layer is higher, and the oxidation rate of the amorphous layer 120 of silicon carbide during the oxidation process can be accelerated.
In practical applications, at least the amorphous layer 120 of silicon carbide may be oxidized to silicon oxide in the oxidation process, and after the oxidation of the amorphous layer 120 of silicon carbide is completed, the oxidation of the dense silicon carbide layer 110 may be continued. The thickness of the finally obtained silicon oxide layer 130 is not limited in the embodiments of the present application, and the silicon oxide layer 130 may be only the thickness of the amorphous layer 120 of silicon carbide, or may be larger or smaller than the thickness of the amorphous layer 120 of silicon carbide.
In the embodiment of the present application, the amorphous layer 120 of silicon carbide is re-grown by solid phase epitaxy when the oxidation process is performed, so that the quality of the interface between the silicon oxide layer 130 and the silicon nitride layer 110 finally obtained by oxidizing the amorphous layer 120 of silicon carbide becomes good, that is, the quality of the interface between SiC and silicon oxide can be improved by performing the oxidation process after amorphizing the silicon carbide.
In practical application, the oxidation process can be carried out by dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, oxygen-introduced oxidation or nitrogen oxide (N)2O) at least one of oxidation.
In the embodiment of the present application, after the silicon oxide layer 130 is obtained, an annealing process may be further performed on the silicon oxide layer 130 so as to improve the crystalline quality of the silicon oxide layer 130. For example, rapid thermal Annealing (RTP), Direct Simulated Annealing (DSA), Laser Annealing (Laser Annealing), etc. may be used, and the temperature range of the Annealing process may be 400-. Specifically, the gas introduced during the annealing process may be at least one of nitrogen, argon, or nitrogen oxide, wherein the nitrogen oxide may be N2O or NO. During the annealing process, N atoms or Ar atoms may diffuse to the interface between the silicon oxide layer 130 and the silicon nitride layer 110, thereby passivating the interface, further reducing the density of interface states between the silicon oxide layer 130 and the silicon nitride layer 110, and improving the quality of the interface.
Referring to fig. 5, after obtaining the silicon oxide layer 130, another oxide layer 140 may be further formed on the silicon oxide layer 130, and the other oxide layer 140 may be HfO2、Al2O3、AlON、AlN、HfAlON、Y2O3、LaSiOx、Gd2O3、TiO2、Ta2O5At least one of (1). The other oxide layer 140 may adjust the dielectric constant of the gate dielectric to better match the gate material.
Referring to fig. 6, the gate 150 may be formed on the other oxide layer 140 according to the embodiments of the present disclosure, wherein the gate material may be at least one of Poly-Si, TaN, TiN, Al, Ni, or W.
After the semiconductor device according to the embodiment of the present application is formed, other processing processes, such as a metal silicide process and formation of other interconnection structures, may be performed as needed.
The embodiment of the application provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a silicon carbide layer is formed on the substrate; bombarding the silicon carbide layer by adopting ion implantation so as to enable the surface layer of the silicon carbide layer to be amorphous, and forming an amorphous layer of silicon carbide; performing an oxidation process to oxidize the amorphous layer of silicon carbide to a silicon oxide layer.
According to the manufacturing method of the semiconductor device, the silicon carbide layer is bombarded by adopting ion implantation, so that the surface layer of the silicon carbide layer is amorphized to form the amorphous layer of the silicon carbide, namely, Si-C bonds on the surface layer of the silicon carbide layer are broken by the ion implantation, the free energy of the surface layer of the silicon carbide layer is increased, the activity of the surface layer is higher, and the oxidation speed of the amorphous layer of the silicon carbide layer in the oxidation process is accelerated. Compared with a compact silicon carbide layer, the amorphous layer of the silicon carbide has a faster oxidation speed when being subjected to an oxidation process, and the amorphous layer of the silicon carbide is grown again through solid phase epitaxy when being subjected to the oxidation process, so that the interface quality of the SiC and the silicon oxide can be improved.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate, wherein a silicon carbide layer is formed on the substrate;
bombarding the silicon carbide layer by adopting ion implantation so as to enable the surface layer of the silicon carbide layer to be amorphous, and forming an amorphous layer of silicon carbide;
performing an oxidation process to oxidize the amorphous layer of silicon carbide to a silicon oxide layer.
2. The manufacturing method according to claim 1, wherein a thickness of the amorphous layer of silicon carbide is controlled by ion implantation according to a desired thickness of the silicon oxide layer.
3. The manufacturing method according to claim 2, wherein the thickness of the amorphous layer of silicon carbide is in a range of 5 to 200 nm.
4. The method of claim 3, wherein the ion implantation energy is in the range of 20keV to 1MeV and the ion implantation dose is in the range of 1e14 to 1e17/cm2。
5. The method of manufacture of claim 1, wherein the bombarding ions have an atomic mass greater than or equal to the atomic mass of Si.
6. The method of claim 5, wherein the bombarded ions are at least one of Si, Ge, Sn, As, Ga, In, P, Te, or Bi.
7. The method of manufacturing of claim 1, wherein the oxidation process is at least one of dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, oxygen fed oxidation, or nitrogen oxide fed oxidation.
8. The manufacturing method according to any one of claims 1 to 7, characterized in that the method further comprises:
and carrying out an annealing process on the silicon oxide layer, wherein the introduced gas is at least one of nitrogen, argon or nitrogen oxide during the annealing process.
9. The manufacturing method according to any one of claims 1 to 7, characterized in that the method further comprises:
forming other oxide layers on the silicon oxide layer, wherein the other oxide layers are HfO2、Al2O3、AlON、AlN、HfAlON、Y2O3、LaSiOx、Gd2O3、TiO2、Ta2O5At least one of (1).
10. The manufacturing method according to any one of claims 1 to 7, characterized in that the method further comprises:
and forming a gate on the silicon oxide layer.
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Application publication date: 20210716 |