CN113127404B - Method and device for reconstructing network topology structure of CPU interconnection system - Google Patents
Method and device for reconstructing network topology structure of CPU interconnection system Download PDFInfo
- Publication number
- CN113127404B CN113127404B CN202110430491.3A CN202110430491A CN113127404B CN 113127404 B CN113127404 B CN 113127404B CN 202110430491 A CN202110430491 A CN 202110430491A CN 113127404 B CN113127404 B CN 113127404B
- Authority
- CN
- China
- Prior art keywords
- cpu
- network topology
- nodes
- output ports
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000003287 optical effect Effects 0.000 claims abstract description 66
- 238000004590 computer program Methods 0.000 claims description 7
- 238000011156 evaluation Methods 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 7
- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Optical Communication System (AREA)
Abstract
The invention provides a method for reconstructing a network topology structure of a CPU interconnection system, which comprises the following steps: acquiring global flow information and the duty ratio of a current CPU interconnection system; dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on global flow information and the duty ratio of the current CPU interconnection system, wherein the CPU interconnection system comprises a plurality of CPU nodes, and each CPU node comprises at least one group of optical input/output ports; and an optical crossbar interconnect switch for dynamically and configurably connecting at least a portion of the input/output ports of the plurality of CPU nodes to form a ring interconnect network topology. By the reconstruction method, the reconfigurable ring topology network can be realized with lower cost and higher integration level, and the network efficiency is improved.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to a method and apparatus for reconstructing a network topology of a CPU interconnect system.
Background
Currently, in the field of multi-CPU interconnect, common interconnect technologies include Ring interconnect (Ring), mesh interconnect (Mesh), full-Mesh, and the like. These interconnect technologies enable multiple CPUs to work cooperatively by allowing communication between the CPUs being connected. The annular interconnection has low cost and easy wiring, and can save the volume so as to meet the requirement of higher integration level.
Fig. 1 shows a schematic diagram of a prior art ring interconnect structure. As shown in fig. 1, CPU nodes 1, 2, 3 and 4 in the ring interconnect are often interconnected using two ring buses with the same paths but opposite directions, corresponding to the transmission and reception of data, respectively. In the bidirectional ring interconnection, the nodes must be provided with two sets of data transceiving ports, and once networking is completed, the topology structure of the system cannot be changed any more.
However, since the maximum delay inside the ring interconnect is linearly related to the number of nodes, the ring interconnect performance may deteriorate rapidly as the number of nodes increases, especially when most of the traffic in the network needs several intermediate nodes to forward, the overall throughput of the network tends to drop to a very low level, thereby significantly limiting the system performance.
Accordingly, there is a need for a more flexible CPU interconnect system and a method and apparatus for dynamically reconfiguring a CPU interconnect system.
Disclosure of Invention
Therefore, an object of the embodiments of the present invention is to overcome the above-mentioned drawbacks of the related art, and provide a method and apparatus for reconstructing a CPU interconnect system, so that the method and apparatus can dynamically adapt to an internal load, and improve network efficiency.
The above purpose is achieved by the following technical scheme:
according to a first aspect of an embodiment of the present invention, there is provided a CPU interconnect system including: a plurality of CPU nodes, each CPU node including at least one set of optical input/output ports; and an optical crossbar interconnect switch for dynamically and configurably connecting input/output ports of at least a portion of the plurality of CPU nodes to form a ring interconnect network topology.
Optionally, each CPU node includes at least two sets of input-output ports, and the optical crossbar interconnect switch includes a first optical crossbar interconnect switch for dynamically connecting at least a portion of one set of input-output ports of the plurality of CPU nodes to form a forward ring interconnect network topology, and a second optical crossbar interconnect switch for dynamically connecting at least a portion of another set of input-output ports of the plurality of CPU nodes to form a corresponding reverse ring interconnect network topology, the corresponding reverse ring interconnect network topology being the same order but opposite in direction as the CPU nodes of the forward ring interconnect network topology.
According to a second aspect of the embodiment of the present invention, there is also provided a method for reconstructing a network topology of the CPU interconnect system, including: acquiring global flow information and the duty ratio of a current CPU interconnection system; and dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the global flow information and the duty ratio of the current CPU interconnection system.
Optionally, the global traffic information includes: the source node of the traffic, the destination node of the traffic, the size of the traffic, and the number of forwarding nodes through which the traffic passes.
Optionally, the dynamically adjusting the connection relationship between the optical crossbar interconnect switch and the input/output ports of the plurality of CPU nodes based on the global traffic information and the duty ratio of the current CPU interconnect system includes: and dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the proportion of the forwarding flow of the paths, the number of which is greater than a specified threshold value, of the forwarding nodes in the global flow of the current CPU interconnection system to the total flow of the system.
Optionally, the dynamically adjusting the connection relationship between the optical crossbar interconnect switch and the input/output ports of the plurality of CPU nodes based on the global traffic information and the duty ratio of the current CPU interconnect system includes: and dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the proportion of the forwarding flow of the paths, of which the number of forwarding nodes is greater than a specified threshold, in the global flow of the current CPU interconnection system to the maximum throughput of the system.
Optionally, dynamically adjusting the connection relationship of the optical crossbar interconnect switch to the input/output ports of the plurality of CPU nodes by dynamically adjusting: step 7-1), taking the network topology structure of the current CPU interconnection system as an alternative network topology structure; step 7-2), selecting two CPU nodes from the current alternative network topology structure by utilizing a random function; step 7-3), exchanging the sequence of the two CPU nodes to generate a new network topology structure; step 7-4), evaluating the current alternative network topology structure and the new network topology structure, and selecting a network topology structure with a better evaluation result to replace the current alternative network topology structure; and 7-5), repeating the steps 7-2) to 7-4) until the preset times are reached, and adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the finally obtained network topology.
Optionally, the current alternative network topology structure and the new network topology structure are evaluated based on the traffic size of the global traffic information and the number of CPU nodes through which the traffic passes.
According to a third aspect of the embodiment of the present invention, there is provided an apparatus for reconstructing a network topology of the CPU interconnect system, including: the receiving module is used for acquiring global flow information and the duty ratio of the current CPU interconnection system; and a reconstruction module, configured to dynamically adjust a connection relationship between the optical crossbar interconnect switch and the input/output ports of the plurality of CPU nodes based on global traffic information and a duty ratio of the current CPU interconnect system.
According to a fourth aspect of embodiments of the present invention, there is provided a computer readable storage medium having stored thereon a computer program which when executed implements the method according to the second aspect of the above embodiments.
According to a fifth aspect of embodiments of the present invention, there is provided an electronic device comprising a processor and a memory, the memory having stored therein a computer program which, when executed by the processor, is operable to carry out the method according to the second aspect of the embodiments described above.
The technical scheme of the embodiment of the invention can have the following beneficial effects:
the CPU nodes are dynamically connected by using the optical cross interconnection switch in the ring interconnection network topology structure, so that the flow bottleneck of the traditional ring interconnection can be broken when the load in the network is unbalanced, the order of the nodes is adjusted while the ring topology structure is kept unchanged, and most of the flow can be delivered without more forwarding nodes, so that the network utilization rate and throughput are greatly improved; the optical cross interconnection switch is used for forming a multi-CPU ring topology interconnection structure, so that the use amount of IO devices can be reduced, the packaging density and the integration level are improved, the cost is reduced, and a small reconfigurable ring topology interconnection network is constructed with lower cost and higher integration level; in addition, the connection sequence of a plurality of CPU nodes in the interconnection system is dynamically adjusted based on the global flow information and the duty ratio of the current CPU interconnection system, so that the connection sequence can be dynamically adapted to internal loads, and the network efficiency is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:
fig. 1 shows a schematic diagram of a prior art ring interconnect structure. .
Fig. 2 shows a schematic diagram of the working principle of an optical crossbar interconnect switch in the prior art.
Fig. 3 shows a schematic structural diagram of a CPU interconnect system according to one embodiment of the invention.
Fig. 4 shows a schematic structural diagram of a CPU interconnect system according to another embodiment of the present invention.
Fig. 5 shows a flow chart of a method of reconstructing a network topology of a CPU interconnect system in accordance with another embodiment of the present invention.
Fig. 6 shows a schematic diagram of a network topology that does not belong to a basic state set according to an embodiment of the invention.
Fig. 7 shows a schematic structural diagram of an apparatus for reconstructing a network topology of a CPU interconnect system according to one embodiment of the present invention.
Detailed Description
For the purpose of making the technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail by way of specific embodiments with reference to the accompanying drawings. It should be understood that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art without the inventive effort, are intended to be within the scope of the present invention, based on the embodiments herein.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
The optical cross interconnection switch is a switching device applied to optical path transmission, and can realize arbitrary interconnection of N nodes in a network by providing N input ports and N output ports, namely, each input in N paths is connected with the output of a corresponding serial number from the outside, so that one or more annular paths can be formed.
Fig. 2 shows a schematic diagram of the working principle of an optical crossbar interconnect switch in the prior art. As shown in fig. 2 (ase:Sub>A), in the 2 x 2 bend optical cross interconnection switch, there are 2 transmission modes of parallel and cross between 2 input ports and 2 output ports of an optical path, that is, node ase:Sub>A-ase:Sub>A 'interconnection, node B-B' interconnection, and node ase:Sub>A-B 'interconnection, node B-ase:Sub>A' interconnection can be implemented, and the 2 modes can be switched at any time; as shown in fig. 2 (B), in the 4 x 4benes optical crossbar switch, there are 24 transmission modes of parallel and different crossbar between 4 input ports and 4 output ports on the optical path, that is, 24 interconnection modes including, for example, node a-B 'interconnection, node B-C' interconnection, node C-D 'interconnection, node D-a' interconnection, etc. can be implemented, and the various modes can also be switched with each other at any time.
However, there is a one-to-one mapping between the optical crossbar interconnect switch input ports and output ports, wherein any one of the output ports can be driven by only one of the input ports, and wherein any one of the input ports can also be driven by only one of the output ports. Therefore, the optical crossbar interconnect switch cannot realize that multiple CPUs communicate with the same CPU at the same time or one CPU communicates with multiple CPUs at the same time in the interconnect network.
Based on the above study, the inventor finds that, because the optical cross interconnection switch can flexibly change the connection mode of the nodes in the network and the one-to-one mapping relation of the input ports and the output ports, the optical cross interconnection switch can be applied to the annular interconnection, and most of traffic can be delivered without more forwarding nodes by dynamically connecting and adjusting the order of the nodes in the annular interconnection, thereby greatly improving the network utilization rate and throughput.
According to one embodiment of the present invention, there is provided a CPU interconnect system including: a plurality of CPU nodes, each CPU node comprising a set of optical input/output ports; and an optical crossbar interconnect switch for dynamically and configurably connecting input/output ports of the plurality of CPU nodes to form a ring interconnect network topology.
Fig. 3 shows a schematic structural diagram of a CPU interconnect system according to one embodiment of the invention. As shown in fig. 3, the system includes 4 CPU nodes (i.e., node 1, node 2, node 3 and node 4) and 1 4 x 4benes optical cross-connect switch, where the optical cross-connect switch connects the 4 nodes in turn (e.g., node 1-2-3-4-1) through its 4 input ports and 4 output ports, so as to form a unidirectional ring-shaped interconnection network topology structure. The optical crossbar interconnect switch may also dynamically adjust the connection order between 4 nodes by changing the different transmission modes between ports (e.g., changing the node connection order to node 1-3-2-4-1).
In other embodiments, only some nodes in the system (e.g., only nodes 1-2-3-1) may be connected by using the optical interactive interconnection switch according to actual requirements, so as to form a local unidirectional ring network topology.
According to another embodiment of the present invention, there is provided a CPU interconnect system, wherein each CPU node includes at least two sets of input-output ports, the optical crossbar interconnect switch includes a first optical crossbar interconnect switch for dynamically connecting one set of input-output ports of the plurality of CPU nodes to form a forward ring interconnect network topology, and a second optical crossbar interconnect switch for dynamically connecting another set of input-output ports of the plurality of CPU nodes to form a corresponding reverse ring interconnect network topology, the corresponding reverse ring interconnect network topology being the same order but in opposite direction as the CPU nodes of the forward ring interconnect network topology.
Fig. 4 shows a schematic structural diagram of a CPU interconnect system according to another embodiment of the present invention. As shown in fig. 4, the system includes 4 CPU nodes (i.e., node 1, node 2, node 3 and node 4) and 24 x 4benes optical cross-connect switches, each CPU node includes two sets of input and output interfaces, where the first optical cross-connect switch connects the 4 nodes in turn (e.g., node 1-2-3-4-1) through its 4 input ports and 4 output ports, forming a forward ring interconnect network topology; the second optical crossbar interconnect switch connects the 4 nodes in reverse order (e.g., nodes 1-4-3-2-1) through its 4 input ports and 4 output ports to form a corresponding reverse torus interconnect network topology that is the same in order but opposite in direction to the nodes of the forward torus interconnect network topology. Likewise, the first optical crossbar interconnect switch may dynamically adjust the connection order between the 4 nodes (e.g., nodes 1-3-2-4-1) by changing the different transmission modes between the ports; the second optical cross interconnection switch can correspondingly adjust the connection sequence (for example, the nodes 1-4-2-3-1) among 4 nodes by changing different transmission modes among ports, so that the adjusted nodes have the same sequence but opposite directions to form a full duplex interconnection network.
In other embodiments, only some nodes in the system (e.g., only nodes 1-2-3-1 and nodes 1-3-2-1) may be connected by using 2 optical interactive interconnection switches according to actual requirements, so as to form a local bidirectional ring network topology.
The CPU nodes are dynamically connected by using the optical cross interconnection switch in the ring interconnection network topology structure, so that the flow bottleneck of the traditional ring interconnection can be broken when the load in the network is unbalanced, the order of the nodes is adjusted while the ring topology structure is kept unchanged, and most of the flow can be delivered without more forwarding nodes, so that the network utilization rate and throughput are greatly improved. In addition, the optical cross interconnection switch is used for forming a multi-CPU ring topology interconnection structure, so that the use amount of IO devices can be reduced, the packaging density and the integration level are improved, the cost is reduced, and a small reconfigurable ring topology interconnection network is constructed with lower cost and higher integration level.
Based on the CPU interconnect system, according to an embodiment of the present invention, there is provided a method for reconstructing a network topology of the CPU interconnect system, including: calculating global flow information and the duty ratio of the current CPU interconnection system; and dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the global flow information and the duty ratio of the current CPU interconnection system.
Fig. 5 shows a flow chart of a method of reconstructing a network topology of a CPU interconnect system in accordance with another embodiment of the present invention. As shown in fig. 5, the method comprises the steps of:
s510, global flow information and the duty ratio of the current CPU interconnection system are obtained.
By acquiring global traffic information and the duty ratio of the current CPU interconnection system, it can be determined whether the current network topology should be reconfigured to reduce or change the relevant forwarding nodes, thereby improving network performance.
In one embodiment, global traffic information and its duty cycle may be counted by some statistical means (e.g., by the CPU node itself) when the network is operating properly. The global traffic information may include, for example: source node of traffic, destination node of traffic, size of traffic, number of forwarding nodes through which traffic passes, etc. By analyzing the global traffic information after the integration, effective information such as the proportion of the forwarding traffic of a path (such as an ultra-long path occupying more than or equal to N/4 of the forwarding node number) with the number of forwarding nodes larger than a specified threshold value in the current global traffic or the proportion of the forwarding traffic of a path with the number of forwarding nodes larger than the specified threshold value with the maximum throughput of the system can be obtained.
S520, based on the global flow information and the duty ratio of the current CPU interconnection system, the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes is dynamically adjusted.
For the proportion of the forwarding traffic of the paths (such as the ultra-long paths occupying more than or equal to N/4 of the forwarding node number) with the number of forwarding nodes larger than the specified threshold value in the current global traffic or the proportion of the forwarding traffic of the paths with the number of forwarding nodes larger than the specified threshold value in the maximum throughput of the system, the communication efficiency of the whole system is reduced no matter which proportion occupies too much. Thus, in one embodiment, the connection order of the plurality of CPU nodes may be dynamically adjusted based on the proportion of the forwarding traffic of paths having a number of forwarding nodes greater than a specified threshold in the global traffic of the current CPU interconnect system to the total traffic of the system. For example, the distance between the source node and the destination node in the ultra-long path forwarding traffic is adjusted (for example, the distance is adjusted to an adjacent position), so that the distance is changed into short-distance traffic, the forwarding/transmitting capacity of the original forwarding node is released, the burden of the system is reduced, and the total throughput of the system is improved. Likewise, in another embodiment, the connection order of the plurality of CPU nodes is dynamically adjusted based on the proportion of the forwarding traffic of paths having a number of forwarding nodes greater than a specified threshold in the global traffic of the current CPU interconnect system to the maximum throughput of the system.
In one embodiment, the connection order of the plurality of CPU nodes is dynamically adjusted by dynamically adjusting the connection order by:
s521, taking the network topology structure of the current CPU interconnection system as an alternative network topology structure.
S522, selecting two CPU nodes from the current alternative network topology structure by utilizing a random function.
S523, exchanging the sequence of the two CPU nodes to generate a new network topology structure.
S524, evaluating the current alternative network topology structure and the new network topology structure, and selecting the network topology structure with better evaluation result to replace the current alternative network topology structure.
In one embodiment, the current alternative network topology and the new network topology may be evaluated based on the traffic size of the global traffic information and the number of CPU nodes through which the traffic passes. In one embodiment, each piece of traffic information may be evaluated to obtain an evaluation value of a single traffic, and the evaluation values of all the single traffic may be summed to obtain a final evaluation value to evaluate the current alternative network topology or the new network topology. Wherein the evaluation value of the single flow is the flow size/the number of nodes through which the flow passes.
And S525, repeating the steps S522 to S524 until the preset times are reached, and adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the CPU nodes based on the finally obtained network topology structure.
In the above embodiment, the connection sequence of the plurality of CPU nodes in the interconnection system is dynamically adjusted based on the global traffic information and the duty ratio of the current CPU interconnection system, so as to adjust the relative positions of the different nodes to optimize the ring topology internal structure, so that the ring topology internal structure can dynamically adapt to the internal load, and the network efficiency is improved. Meanwhile, the network topology structure is reconstructed through the optical cross interconnection switch at the physical layer, so that the reconfigurable ring topology network can be realized with lower cost and higher integration level.
In one embodiment, it may be set that only one ring path can be allowed and only formed between multiple CPU nodes of the system, and the internal connection mode of the path passing through all input/output ports of all CPU nodes of the system is a feasible connection mode, so that the set of connection modes meeting the conditions forms a basic state set of the ring topology. Any new network topology should be generated as a subset of the basic set of states.
Fig. 6 shows a schematic diagram of a network topology that does not belong to a basic state set according to an embodiment of the invention. As shown in fig. 6 (a), where the optical crossbar connects 4 CPU nodes (i.e., node 1, node 2, node 3, and node 4) to form two independent ring interconnect network topologies, namely network topology 1 (node 1-2-1) and network topology 2 (node 3-4-3); as shown in fig. 6 (B), where the optical crossbar interconnects connect 4 CPU nodes (i.e., node 1, node 2, node 3, and node 4), forming node 1 self-connection and network topology 3 (node 2-3-4-2). Because the ring network topology structure formed by the two connection modes is not in the basic state set, the connection sequence of the CPU nodes cannot be adjusted as the network topology structure after reconstruction.
Through the embodiment, the reconstructed network topology structure can be defined according to actual requirements, so that the network topology structure can cover all CPU nodes in the system only through one ring interconnection, and performance inefficiency caused by frequent reconstruction and low efficiency of the ring network to specific network loads are avoided.
Those skilled in the art will appreciate that the network topology after reconstruction can be calculated in a variety of ways, including but not limited to, by means of enumeration, by means of gradient descent, etc., to find an optimal solution. The locations where the network topology calculations after reconstruction are performed are also varied, including but not limited to a specific computing component, a particular CPU node, or an ensemble of CPU nodes.
Fig. 7 shows a schematic structural diagram of an apparatus for reconstructing a network topology of a CPU interconnect system according to one embodiment of the present invention. As shown in fig. 7, the system 700 includes a receiving module 701 and a reconstructing module 702. Although the block diagrams describe components in a functionally separate manner, such descriptions are for illustrative purposes only. The components shown in the figures may be arbitrarily combined or separated into separate software, firmware, and/or hardware components. Moreover, such components can execute on the same computing device or on multiple computing devices, where the multiple computing devices can be connected by one or more networks, regardless of how they are combined or partitioned.
Wherein the receiving module 701 obtains global traffic information and a duty cycle of the current CPU interconnect system. The reconfiguration module 702 dynamically adjusts the connection relationship of the optical crossbar interconnect switch to the input-output ports of the plurality of CPU nodes based on the global traffic information of the current CPU interconnect system and its duty cycle as described above.
In yet another embodiment of the present invention, there is further provided a computer readable storage medium having stored thereon a computer program or executable instructions which when executed implement the technical solution described in the foregoing embodiment, the implementation principle being similar and not repeated herein. In embodiments of the present invention, a computer-readable storage medium may be any tangible medium that can store data and that can be read by a computing device. Examples of computer readable storage media include hard disk drives, network Attached Storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-R, CD-RWs, magnetic tapes, and other optical or non-optical data storage devices. The computer-readable storage medium may also include a computer-readable medium distributed over a network coupled computer system so that the computer program or instructions may be stored and executed in a distributed fashion.
In another embodiment of the invention, the invention may be implemented in the form of an electronic device. The electronic device comprises a processor and a memory, in which a computer program is stored which, when being executed by the processor, can be used to carry out the method of the invention.
Reference in the specification to "various embodiments," "some embodiments," "one embodiment," or "an embodiment" or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in various embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Thus, a particular feature, structure, or characteristic described in connection with or illustrated in one embodiment may be combined, in whole or in part, with features, structures, or characteristics of one or more other embodiments without limitation, provided that the combination is not non-logical or inoperable.
The terms "comprises," "comprising," and "having" and the like, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Nor does "a" or "an" exclude a plurality. Additionally, the various elements in the drawings of the subject application are for illustration purposes only and are not drawn to scale.
Although the present invention has been described by way of the above embodiments, the present invention is not limited to the embodiments described herein, but includes various changes and modifications made without departing from the scope of the invention.
Claims (7)
1. A CPU interconnect system comprising:
the system comprises a plurality of CPU nodes, a plurality of CPU nodes and a plurality of CPU control nodes, wherein each CPU node comprises at least one group of input/output ports, and global flow information and the duty ratio of the current CPU interconnection system are acquired based on the plurality of CPU nodes; and
an optical crossbar interconnect switch for dynamically and configurably connecting at least a portion of input/output ports of the plurality of CPU nodes to form a ring interconnect network topology, and based on global traffic information of the current CPU interconnect system and its duty cycle, the connection relationship of the optical crossbar interconnect switch to the input/output ports of the plurality of CPU nodes is dynamically adjusted, comprising: dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the proportion of the forwarding flow of the paths with the number of forwarding nodes greater than a specified threshold in the global flow of the current CPU interconnection system to the total flow of the system or the proportion of the forwarding flow of the paths to the maximum throughput of the system; or (b)
Dynamically adjusting the connection relationship of the optical crossbar interconnect switch and the input/output ports of the plurality of CPU nodes by:
step 7-1), taking the network topology structure of the current CPU interconnection system as an alternative network topology structure;
step 7-2), selecting two CPU nodes from the current alternative network topology structure by utilizing a random function;
step 7-3), exchanging the sequence of the two CPU nodes to generate a new network topology structure;
step 7-4), evaluating the current alternative network topology structure and the new network topology structure, and selecting a network topology structure with a better evaluation result to replace the current alternative network topology structure;
step 7-5), repeating the steps 7-2) to 7-4) until reaching the preset times, adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the finally obtained network topology,
wherein each CPU node includes two sets of input-output ports, the optical crossbar interconnect switch includes a first optical crossbar interconnect switch for dynamically connecting at least a portion of one set of input-output ports of the plurality of CPU nodes to form a forward ring interconnect network topology, and a second optical crossbar interconnect switch for dynamically connecting at least a portion of another set of input-output ports of the plurality of CPU nodes to form a corresponding reverse ring interconnect network topology that is the same order but in opposite direction as the CPU nodes of the forward ring interconnect network topology.
2. A method of reconfiguring a network topology of the CPU interconnect system of claim 1, comprising:
acquiring global flow information and the duty ratio of a current CPU interconnection system; and
and dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the global flow information and the duty ratio of the current CPU interconnection system.
3. The reconstruction method according to claim 2, wherein the global traffic information comprises: the source node of the traffic, the destination node of the traffic, the size of the traffic, and the number of forwarding nodes through which the traffic passes.
4. A reconstruction method according to claim 3, wherein the current alternative network topology and the new network topology are evaluated based on the traffic size of the global traffic information and the number of CPU nodes through which traffic passes.
5. An apparatus for reconstructing a network topology of the CPU interconnect system of claim 1, comprising:
the receiving module is used for acquiring global flow information and the duty ratio of the current CPU interconnection system; and
and the reconstruction module is used for dynamically adjusting the connection relation between the optical cross interconnection switch and the input/output ports of the plurality of CPU nodes based on the global flow information and the duty ratio of the current CPU interconnection system.
6. A storage medium having stored therein a computer program which, when executed by a processor, is operable to carry out the method of any of claims 1-4.
7. An electronic device comprising a processor and a memory, the memory having stored therein a computer program which, when executed by the processor, is operable to carry out the method of any of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110430491.3A CN113127404B (en) | 2021-04-21 | 2021-04-21 | Method and device for reconstructing network topology structure of CPU interconnection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110430491.3A CN113127404B (en) | 2021-04-21 | 2021-04-21 | Method and device for reconstructing network topology structure of CPU interconnection system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113127404A CN113127404A (en) | 2021-07-16 |
| CN113127404B true CN113127404B (en) | 2024-03-08 |
Family
ID=76778580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110430491.3A Active CN113127404B (en) | 2021-04-21 | 2021-04-21 | Method and device for reconstructing network topology structure of CPU interconnection system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113127404B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115269209B (en) * | 2022-09-30 | 2023-01-10 | 浙江宇视科技有限公司 | GPU cluster scheduling method and server |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016061957A1 (en) * | 2014-10-22 | 2016-04-28 | 中兴通讯股份有限公司 | Method and apparatus for evaluating service traffic in lte network |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2727289B1 (en) * | 2011-06-28 | 2015-08-12 | Telefonaktiebolaget L M Ericsson (publ) | Topology change in a network with ring topology |
| US9020347B2 (en) * | 2013-09-09 | 2015-04-28 | Oracle International Corporation | Reconfigurable optical interconnect network |
-
2021
- 2021-04-21 CN CN202110430491.3A patent/CN113127404B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016061957A1 (en) * | 2014-10-22 | 2016-04-28 | 中兴通讯股份有限公司 | Method and apparatus for evaluating service traffic in lte network |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113127404A (en) | 2021-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20140139032A (en) | A packet-flow interconnect fabric | |
| US10091091B2 (en) | Direct network having plural distributed connections to each resource | |
| CN101778049A (en) | Router and transmission method thereof on packet-circuit switching chip | |
| Palesi et al. | A method for router table compression for application specific routing in mesh topology NoC architectures | |
| CN114760255B (en) | On-chip and inter-chip integrated network deadlock-free architecture for multi-die interconnection | |
| CN108259387B (en) | Switching system constructed by switch and routing method thereof | |
| CN105471749B (en) | The exponent number flexibly extensive interconnection network topological structure of low diameter and method for routing | |
| CN103124420A (en) | Wireless on-chip network structuring method | |
| CN113127404B (en) | Method and device for reconstructing network topology structure of CPU interconnection system | |
| CN102325089A (en) | Fat tree type network-on-chip mapping method based on differential evolution and predatory search strategy | |
| CN104052663A (en) | Large-scale on-chip chip interconnecting method and routing algorithm for realizing interconnecting structure | |
| CN103761212A (en) | Method for designing mapping scheme and topological structure between task and node in on-chip network | |
| CN112506850B (en) | On-chip and inter-chip interconnection network | |
| Dehghani et al. | A novel approach to optimize fault-tolerant hybrid wireless network-on-chip architectures | |
| Chen et al. | Star-type architecture with low transmission latency for a 2D mesh NOC | |
| CN116260760A (en) | Topology reconstruction method based on flow sensing in multi-core interconnection network | |
| CN114896940B (en) | Design method and device of wafer-level exchange system defined by software | |
| Nickray et al. | Power and delay optimization for network on chip | |
| CN103986670A (en) | Method for obtaining performance of optical switch chip | |
| Lusala et al. | A hybrid router combining sdm-based circuit swictching with packet switching for on-chip networks | |
| Ingle et al. | Mesh topology of NoC architecture using source routing algorithm | |
| Ansari et al. | Advancement in energy efficient routing algorithms for 3-D Network-on-Chip architecture | |
| Zhang et al. | A cellular NoC architecture based on butterfly network coding (CBNoC) | |
| Rahaman et al. | A scalable hierarchical ring based wireless network-on-chip | |
| Chemli et al. | Architecture and performances comparison of network on chip router for hierarchical mesh topology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |