CN113127391A - Design method of DMA data transmission engine compatible with multiple devices - Google Patents
Design method of DMA data transmission engine compatible with multiple devices Download PDFInfo
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- CN113127391A CN113127391A CN202110524492.4A CN202110524492A CN113127391A CN 113127391 A CN113127391 A CN 113127391A CN 202110524492 A CN202110524492 A CN 202110524492A CN 113127391 A CN113127391 A CN 113127391A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/282—Cycle stealing DMA
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
A design method of a DMA data transmission engine compatible with multiple devices comprises the following steps: SGDMA/BDMA compatibility design: BDMA transmission mechanism design, SGDMA transmission mechanism design and DMA-DESC design in SGDMA are used for being compatible with BDMA; designing DMA channel registration; and (3) interrupt design: BDMA interrupt design and SGDMA interrupt design; interrupt and poll configurable designs. The invention designs the DMA function independently, the devices at the upper layer of the DMA use the compatible DMA layer together to transmit data, and the DMA channel can be shared when the DMA resources are in shortage. Through the reservation and the extended design of descriptors in the SGDMA, the BDMA software design is compatible; the DMA transfer performance with high bandwidth transfer requirements is realized by the interrupt and poll configurable and combined configuration mode.
Description
Technical Field
The invention belongs to the field of communication, and particularly relates to a design method of a DMA data transmission engine compatible with multiple devices.
Background
The DMA engine management software is suitable for the condition that DMA upper-layer equipment shares DMA platform resources, and has the characteristics of multiple equipment, multiple functions, complex data transmission function, high data transmission bandwidth and the like. The current localization field does not separately design functions of a DMA layer, and the DMA layer are integrated by combining specific equipment and specific functions.
The design of the current domestic DMA hardware is combined with the design of specific equipment, the transmission of DMA is realized on the function of the specific equipment in the aspect of software design, DMA layer codes cannot be multiplexed when different equipment on the upper layer shares DMA platform resources on a platform with the same DMA hardware design, and the design cost and the period of software are higher.
The current design driven by network controllers uses streaming DMA for data transfer in terms of DMA data transfer. When data is sent, a data source is a protocol stack, and a driver needs to be responsible for releasing memory resources after the data from the protocol stack is sent; when receiving data, the data source is a driver, and the driver needs to be responsible for preparing memory resources for the data to be received before performing DMA transmission on the data from the device, and uploads the received data memory to the protocol stack. Devices like FC controller drives currently use coherent DMA for data transfer in terms of DMA data transfer. The DMA memory is applied and released by a user in a sending or receiving state of data, and the user state and the kernel state need to share page table mapping resources. In terms of DMA design, the usage scenarios of the two DMA and memory resources are very different in design, and different interfaces need to be provided for respective designs. The software interface for applying and releasing the network memory resource and other user mode memory resources is not unified in the current software design scheme. The SGDMA can realize one-time transmission of a plurality of BDMA linked lists, DMA transmission can be efficiently carried out by greatly utilizing DMA resources, and a corresponding Descriptor (DESC) needs to be designed for each BDMA in software design and a linked list structure is formed, so that hardware equipment can carry out one-time gathering transmission on the dispersed BDMAs; the BDMA mode is relatively simple, and when the high-speed hardware data is transmitted, the hardware can complete one-time DMA transmission only by acquiring the information of the source, the destination, the length and the like of the high-speed hardware data. In software design, a device implements either BDMA transfer or SGDMA transfer according to the features of a hardware platform, and is not designed to be integrated currently.
Disclosure of Invention
The invention aims to solve the problems of complex design of a software driving architecture and poor data transmission performance in the prior art, and provides a design method of a DMA data transmission engine compatible with multiple devices, which can simplify the development process of upper-layer software, simplify the design complexity of a software architecture, greatly reuse codes of DMA design, greatly improve the DMA data transmission performance, and keep the design of software unchanged to the greatest extent under the condition of shortage of DMA resources.
In order to achieve the purpose, the invention has the following technical scheme:
a design method of a DMA data transmission engine compatible with multiple devices comprises the following steps:
-SGDMA/BDMA compatibility design;
designing a BDMA transmission mechanism;
designing an SGDMA transmission mechanism;
the DMA-DESC in the SGDMA is designed to be compatible with the BDMA;
-design of DMA channel registration;
-an interrupt design;
interrupt design for BDMA;
an interrupt design of the SGDMA;
interrupt and poll configurable designs.
As a preferred scheme of the invention, the design of the BDMA transmission mechanism is divided into a transmission process and a receiving process; and (3) a sending process: acquiring a virtual address and a length of data to be sent, mapping a memory physical address, filling a BDMA-DESC source physical address register, filling a BDMA-DESC data length register, and completing the sending process after the device finishes sending and generates a DMA to finish interrupt generation; the receiving process comprises the following steps: applying a continuous memory area for data to be received in advance as a target virtual address, mapping the physical address of the memory in the area as a target physical address, filling a target physical address register of the BDMA-DESC, after the DMA finishes the interrupt generation, acquiring the received data through the target virtual address and the DMA-DESC data length register, and finishing the receiving process.
As a preferred scheme of the present invention, the SGDMA transfer mechanism design includes SGDMA-DESC initialization, transmission process and reception process;
specifically, the SGDMA-DESC initializes: applying a continuous memory as a descriptor ring for storing SGDMA-DESC, and mapping the part of memory as a physical address; and (3) a sending process: the method comprises the steps of obtaining a virtual address linked list of a data block linked list to be sent, mapping the virtual address linked list into a physical address linked list, storing physical addresses and length information into an SGDMA-DESC descriptor ring, writing a first descriptor physical address and a tail descriptor physical address of a descriptor sequence used in the ring into an SG descriptor head register and an SG descriptor tail register respectively, generating DMA completion interruption after equipment finishes sending, and finishing the sending process. The receiving process comprises the following steps: the method comprises the steps of forming a memory block chain table annular structure for a memory applying continuous data to be received in advance, mapping the memory to obtain a physical address, filling physical address information of the memory block chain table annular structure into an SGDMA-DESC descriptor ring one by one, obtaining received data descriptor sections on the SGDMA-DESC descriptor ring through an SG descriptor head register and an SG descriptor tail register after the DMA finishes interrupt generation, obtaining the head and the tail of a data block chain received at this time on the corresponding memory block chain table annular structure through descriptor information in the received data descriptor sections, and finishing the receiving process.
As a preferred embodiment of the present invention, the designing for compatibility with the BDMA through the DMA-DESC in the SGDMA includes: in BDMA mode, only one DESC on a DESC ring is used at a time; for transmission, pre-storing a source physical address, a source virtual address and a data length of data to be transmitted to a current DESC on a DESC ring, writing the source physical address and the data length on the current DESC into a DMA source physical address register and a DMA data register respectively, and enabling a current DESC pointer to point to a next new DESC after the data transmission is completed; for receiving, storing a memory address applied in advance into a current DESC ring, writing a target physical address into a DMA target address register, and after the receiving is interrupted, acquiring received data through a length register and a memory virtual address stored in the current DESC, so that a current DESC pointer points to a next new DESC.
As a preferred scheme of the invention, the design of the DMA channel registration is divided into multiple channels and a single channel; multi-channel: aiming at the condition of abundant DMA channel resources, a plurality of devices respectively use respective DMA channels, and the transmission and the reception of each device are also respectively carried out by using the independent DMA channels; single channel: aiming at the condition that DMA channel resources are short, a lock protection mechanism is designed for each channel, and if the channel needs to be shared, the channel lock is acquired on a specific path until the lock is released after DMA transfer is completed.
As a preferred scheme of the present invention, the interrupt design includes a sending stage and a receiving stage; specifically, in the sending stage, a source physical address and a destination physical address of data to be transmitted and the length of the data to be transmitted are filled into a DMA control register, the data can be sent, and DMA completion interruption is generated after the transmission is completed; after the DMA bottom layer equipment receives the data, the source address is the DMA equipment, the source address, the destination physical address and the data length of the data are known, the data are transmitted to the memory, and DMA completion interruption is generated after the transmission is completed.
As a preferred embodiment of the present invention, the design of the BDMA interrupt specifically includes: in the sending process, calling a DMA data transmission interface to fill the source physical address, the destination physical address and the data length of the common part, and finishing a data sending process after finishing the interrupt generation of the DMA;
in the receiving process, a memory for preparing to receive data fills a target physical address, equipment interruption is generated when equipment at the bottom layer of the DMA receives the data, a DMA data transmission interface is called to partially fill a source physical address and a data length together, and a data receiving process is completed after the interruption of the DMA is completed.
As a preferred scheme of the present invention, the interrupt design of the SGDMA specifically includes: in the sending process, the public part is filled in the DESC head and the DESC tail by calling a DMA data transmission interface, and after the DMA finishes the interrupt generation, a data sending process is finished;
in the receiving process, a memory for receiving data is prepared to fill a target physical address, equipment interruption is generated when equipment at the bottom layer of the DMA receives the data, at the moment, a public part is filled in a DESC head and a DESC tail by calling a DMA data transmission interface, and after the interruption generation of the DMA is completed, a data receiving process is completed.
As a preferred solution of the present invention, the design that the interrupt and polling are configurable includes a polling mode, an interrupt mode and a mode that the interrupt combines with polling; a polling mode: if the polling in the equipment data receiving FIFO is not empty each time, calling a data receiving interface to receive data until the state of the equipment data receiving FIFO is empty; an interruption mode: if the DMA bottom layer equipment generates the receiving equipment interrupt, acquiring the data length and the source physical address register in a receiving FIFO controller register, filling a DMA control register by combining the prepared target physical address, and realizing a DMA data receiving process after the DMA finishes the interrupt; interrupt and poll mode: the method comprises the following steps that a polling and interruption combined mode can be used under the condition that the data transmission bandwidth is uncertain, each time data is received through interruption triggering, equipment interruption is closed after the equipment interruption is generated, data are received in a polling mode until a receiving FIFO is empty, then the equipment interruption is opened, and next interruption is waited to be generated; in order to not affect the real-time performance and the processing performance of an operating system responding to other interrupts, a polling threshold is set, the polling times cannot exceed the polling threshold in one polling, if the polling times exceed the polling threshold, an interrupt receiving flow for interrupt preparation of next data is started, and other interrupt processing routines are scheduled for processing.
In a preferred embodiment of the present invention, the interrupt processing is performed in a second half processing mode, that is, a time-consuming operation is placed in the second half of the interrupt for scheduling execution.
Compared with the prior art, the invention has the following beneficial effects:
by independently designing the DMA function, the devices on the upper layer of the DMA commonly use the compatible DMA layer to carry out data transmission, and can also carry out the sharing of the DMA channel when the DMA resources are in shortage. Code is reused to the maximum extent in the design level, and the design of a software framework is simplified. The design of the Descriptor (DESC) is a description linked list realized aiming at the dispersion aggregation characteristic of the SGDMA, the design of the DESC linked list is not needed for the BDMA, and the design of the DESC linked list is reserved in the design of the BDMA, so that the compatibility of the BDMA and the SGDMA is realized. The design method of the DMA data transmission engine with multiple compatible devices conforms to the Linux kernel interface specification, adopts various compatible schemes, and realizes the abstraction of a DMA software layer, including the design compatibility of SGDMA and BDMA, the design compatibility of stream DMA resource management and the resource management of consistent DMA, and the like. The design of the DMA engine layer can efficiently design the function of the device driver on the upper layer, and the requirement of the upper layer on the DMA is uniformly scheduled and managed, so that the consistency of the interface for calling the DMA by different devices is uniform. The method can realize complete autonomous control, uses C language for programming, and passes prototype verification test on a Loongson 3A3000+7A1000 computing platform at present.
Furthermore, the design of DMA channel registration is divided into multiple channels and a single channel, and under the condition that the DMA channel is in short supply, the sharing and multiplexing of the DMA channel are realized by adopting a software mode; the DMA transmission performance required by high-bandwidth transmission is realized by the configurable design of interruption and polling and the combination of a configuration mode; the conventional way of using the NAPI, the method of the present invention differs from the NAPI in that the polling threshold is set to prevent permanent occupation of the DMA channel by a single device.
Drawings
FIG. 1 is a block diagram of a DMA engine of an embodiment of the present invention;
FIG. 2 is a flow chart of the management of sending descriptor rings according to an embodiment of the present invention;
FIG. 3 is a flow chart of the management of receiving descriptor rings according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
The invention provides a design method of a DMA data transmission engine compatible with multiple devices, which realizes DMA data transmission with multiple channels, multiple protocols and high bandwidth.
Specific functions of the high performance DMA engine include: DMA channel registration function, memory-to-device oriented data transfer (send) function, device-to-memory oriented data transfer (receive), efficient descriptor storage function, etc.
Physically, the high-performance DMA engine is mainly composed of the following modules: a DMA channel registration module; 2. an interrupt management module; 3. a data transmission module; 4. a descriptor management module; PCIe bus interface management module, etc.
In order to implement the above functions, the DMA engine controller needs to be designed as a Linux PCIe bus device, and the DMA channel is used by the upper device by providing a DMA channel registration interface for the device to which the DMA channel is applied by the upper layer. An engine module meeting the PCIe bus equipment interface needs to be designed in a Linux kernel architecture, and under the requirement of two modes of a DMA controller, the method provided by the invention integrates the design of SGDMA and BDMA into a whole.
The method specifically comprises the following steps:
(1) SGDMA/BDMA compatibility design;
by reserving and improving the design implementation of the SGDMA-DESC;
BDMA transport mechanism:
and (3) sending: the method comprises the steps of obtaining a virtual address and a length of data to be sent (the memory area is a continuous memory area), mapping a physical address (source physical address and length) of a memory, filling a BDMA-DESC source physical address register and filling a BDMA-DESC data length register (data sending), generating DMA to complete interruption after the device sends data, and completing the sending process.
Receiving: applying for a continuous memory area (target virtual address) for the data to be received in advance, mapping the memory physical address (target physical address), filling a target physical address register of the BDMA-DESC, after the DMA is finished and is generated intermittently, obtaining the received data through the target virtual address and a DMA-DESC data length register, and finishing the receiving process.
SGDMA transfer mechanism:
SGDMA-DESC initialization:
applying for storing a descriptor ring (a continuous memory) of the SGDMA-DESC, and mapping the part of the memory (physical address);
and (3) sending: the method comprises the steps of obtaining a virtual address linked list of a data block linked list to be sent, mapping the virtual address linked list into a physical address linked list, storing physical addresses and length information of a series of continuous memory blocks into an SGDMA-DESC descriptor ring, respectively writing a first descriptor physical address and a tail descriptor physical address of a used descriptor sequence of data in the memory ring into an SG descriptor head register and an SG descriptor tail register, generating DMA completion interrupt after equipment finishes sending, and finishing the sending process.
Receiving: applying a series of continuous memories for data to be received in advance to form a memory block chain table ring structure, mapping the series of block memories (physical addresses), filling the physical address information of the memory block chain table ring into the SGDMA-DESC ring one by one, after the DMA finishes the interrupt generation, acquiring the descriptor segments of the received data on the SGDMA-DESC ring through an SG descriptor head register and an SG descriptor tail register, further acquiring the head and the tail of the received data block chain on the corresponding memory block chain table ring through the descriptor information, and finishing the receiving process.
The DMA-DESC design in SGDMA is reserved for compatibility with BDMA software design:
as the transmission of the BDMA does not need the participation of DESC essentially, for transmission, the data to be transmitted can be transmitted only by filling in the source physical address register and the length register; for receiving, after filling in the destination physical address register, and after the receiving interrupt is generated, the received data can be obtained through the data length register and the virtual memory address for mapping the destination physical address. The SGDMA-DESC is reserved for design requirements and used in the BDMA transfer mode for BDMA compatibility. In the BDMA mode, only one DESC on a DESC ring is used at a time. For transmission, a source physical address, a source virtual address and a data length of data to be transmitted are stored in advance in a current DESC on a DESC ring, the source physical address and the data length on the current DESC are written into a DMA source physical address register and a DMA data register respectively, and after the data transmission is finished, a current DESC pointer is maintained by software to point to a next new DESC. For receiving, information such as a target virtual address of a memory, a target physical address of the memory and the like which are applied in advance are stored in a current DESC ring, the target physical address is written into a DMA target address register, after the interruption of receiving is completed, received data are obtained through a length register and the memory virtual address stored in the current DESC, and finally a current DESC pointer is maintained by software to point to a next new DESC. The management of BDMA data transmission is compatible on the basis of SGDMA software framework design through the compatibility mode.
(2) Designing DMA channel registration;
multi-channel:
if the DMA channel resources on the hardware platform are relatively abundant, multiple devices may use their respective DMA channels, and the transmission and reception of each device may also be performed using separate DMA channels.
Single channel:
if the DMA channel resources on the hardware platform are tight, one channel is used as both the sending channel and the receiving channel, and a device which may use the channel needs to be shared with other devices. In this case, the design of the DMA engine requires the use of virtual multiple channels. The specific compatibility design is as follows: the lock mechanism is designed to protect channel critical resources. A lock protection mechanism is designed for each channel, if the channel needs to be shared (equipment sharing, transceiving sharing), the channel lock is acquired on a specific path until the lock is released after DMA transmission is completed, and the utilization space of the DMA channel can be greatly improved through the lock mechanism.
(3) Interrupt design (the transmission flow (receiving/sending flow) is unified by completing interrupt through DMA);
the method comprises the following steps: extracting a common part of transmission and reception (DMA data transfer interface);
the common part of sending and receiving is the hardware transport mechanism. For transmission: and filling the length of the data to be transmitted into a DMA control register, wherein the data can be transmitted, and DMA is generated to complete interruption after transmission is completed. For receiving, when the DMA underlying device receives data, the source address of the data (for receiving, since the source address is a DMA device, the parameter may not be set without distinguishing between multiple devices and multiple sources), the destination physical address (obtained from a memory to which the data is applied and mapped before receiving the data, and filled in a register), and the length of the data are known, at this time, the data can be transmitted to the memory, and a DMA completion interrupt may be generated after the transmission is completed.
Interrupt design for BDMA:
in the sending process: and calling a common part (a DMA data transmission interface) to fill in a source physical address, a destination physical address and a data length, and finishing a data sending process after finishing the interrupt generation of the DMA.
In the receiving process: preparing a memory for receiving data (filling a target physical address), waiting for equipment interruption when equipment at the bottom layer of the DMA receives the data, calling a common part (a DMA data transmission interface) to fill a source physical address and a data length at the moment, and finishing a data receiving process after the DMA finishes the interruption.
Interrupt design of SGDMA:
in the sending process: and calling a public part (DMA data transmission interface) to fill the DESC head and the DESC tail, and finishing a data sending process after the DMA is finished and the interruption is generated.
In the receiving process: preparing a memory for receiving data (filling a target physical address), waiting for equipment interruption when equipment at the bottom layer of the DMA receives the data, calling a public part (a DMA data transmission interface) to fill a DESC head and a DESC tail, and waiting for the interruption of the DMA to be generated, and finishing a data receiving process.
(4) Interrupt and polling configurable designs; the high bandwidth requirement of the ten-gigabit communication and the requirement of reducing the utilization rate of system resources by the gigabit communication are realized in a compatible manner. The receiving mode can be configured, the polling mode is used for receiving in a high-bandwidth using scene, and the interrupt mode is used for receiving in a low-bandwidth using scene. Specifically, the method is realized by encapsulating a common part of polling and interruption (a DMA data receiving interface which realizes a data physical transmission function in a DMA data receiving direction);
a polling mode: and if the polling in the equipment data receiving FIFO is not empty, calling a data receiving interface to receive data until the state of the equipment data receiving FIFO is empty.
An interruption mode: if the DMA bottom layer equipment generates the receiving equipment interrupt, the data length in the receiving FIFO controller register and the source physical address register are obtained, the DMA control register is filled in by combining the prepared target physical address, and the DMA data receiving process is realized once after the DMA finishes the interrupt.
Interrupt and poll mode: in the case of uncertain data transmission bandwidth, polling combined with interrupts may be used: and each time, the data is received through interrupt triggering, once the device interrupt is generated, the device interrupt is closed, the data is received in a polling mode until the receiving FIFO is empty, the device interrupt is opened, and the next interrupt is waited to be generated. In order not to affect the real-time performance and the processing performance of the operating system responding to other interrupts, the method can be optimized, namely, a polling threshold is set, the polling times cannot exceed the polling threshold in one polling, if the polling times exceed the polling threshold, an interrupt receiving flow for interrupt preparation of next data needs to be started, and other interrupt processing routines are scheduled for processing.
The DMA data transmission engine design method provided by the invention has the advantages that the interrupt processing adopts a latter half processing mode, time-consuming data packaging, condition judgment, protocol data submission and other operations are put in the latter half of the interrupt for scheduling execution, the real-time performance of data processing after interrupt generation is not influenced, and the performance of other equipment sharing interrupt processing is not influenced.
Examples
The embodiment of the design method of the DMA data transmission engine compatible with multiple devices provided by the invention comprises the following steps:
(1) design of SGDMA engine, see fig. 2, fig. 3:
the filled squares represent the DESC currently occupied by HW, and the open squares represent the DESC currently occupied by SW.
The transmission flow is detailed in fig. 2, and the transmission initialization stage:
driving initialization HW _ Next and SW _ Next pointers to the start position of DESC Ring;
driving a reset HW _ Completed pointer;
the driver initializes and enables the DMA engine.
And a transmission stage of the sending packet:
the data reaches the Ethernet data packet sending interface;
a plurality of data packets are marked by SG-DESC and ready to be sent;
driving marks SOP, EOP, and IRQ _ on _ complete in DESC;
drive adding user control information (such as checksums, etc.) to the descriptor;
the update SW _ Next pointer is driven.
And a sending post-processing stage:
the driver checks the completion status of the DESC;
the driver releases the buffer for the packet.
The receiving process is detailed in fig. 3, and the receiving initialization stage is as follows:
the driver initializes each receiving DESC by applying an appropriately sized Ethernet buffer (SKB) or intra-block memory buffer;
initializing a HW _ Next pointer to start DESC Ring, and initializing a SW _ Next pointer to end DESC Ring;
driving a reset HW _ Completed pointer;
driving initialization and enabling a DMA engine;
and a receiving post-processing stage:
the driver checks the completion status of the DESC;
the drive checks the SOP, EOP and user information states;
driving and uploading the finished buffer data to an upper layer;
driving to supplement a new memory buffer area for the DESC;
the update SW _ Next pointer is driven.
(2) Compatibility design for BDMA, see fig. 2, fig. 3:
the solid squares represent that the DESC is currently occupied by HW, and the open squares represent that the DESC is currently occupied by SW;
the transmission flow is detailed in fig. 2, and the transmission initialization stage:
driving initialization HW _ Next and SW _ Next pointers to the start position of DESC Ring;
driving a reset HW _ Completed pointer;
the driver initializes and enables the DMA engine.
And a transmission stage of the sending packet:
the data reaches the Ethernet data packet sending interface;
only one data packet is marked by SG-DESC and is ready to be sent;
driving marks SOP, EOP, and IRQ _ on _ complete in DESC;
drive adding user control information (such as checksums, etc.) to the descriptor;
the update SW _ Next pointer is driven.
And a sending post-processing stage:
the driver checks the completion status of the DESC;
the driver releases the buffer for the packet.
The receiving process is detailed in fig. 3, and the receiving initialization stage is as follows:
the driver initializes each receiving DESC by applying an appropriately sized Ethernet buffer (SKB) or intra-block memory buffer;
initializing a HW _ Next pointer to start DESC Ring, and initializing a SW _ Next pointer to end DESC Ring;
driving a reset HW _ Completed pointer;
driving initialization and enabling a DMA engine;
and a receiving post-processing stage:
the driver checks the completion status of the DESC;
the drive checks the SOP, EOP and user information states;
driving and uploading the finished buffer data to an upper layer;
driving to supplement a new memory buffer area for the DESC;
the update SW _ Next pointer is driven.
The information to be filled in the DMA control register in BDMA/SGDMA mode is shown in table 1:
TABLE 1
DESC Ring pointer specification is shown in Table 2:
TABLE 2
| Pointer mark | Description of the invention |
| HW_Completed | Recording the last descriptor after the DMA engine processing is completed |
| HW_Next | Recording the next descriptor to be processed by the DMA engine |
| SW_Next | Recording the next descriptor to be submitted by the software to the DMA process |
According to the scheme, the controller driver is compiled and compiled by adopting C language, and debugging of the controller driver is completed. Finally, the test result shows that the invention has good practicability and the performance meets the expectation.
Claims (10)
1. A design method of a DMA data transmission engine compatible with multiple devices is characterized by comprising the following steps:
-SGDMA/BDMA compatibility design;
designing a BDMA transmission mechanism;
designing an SGDMA transmission mechanism;
the DMA-DESC in the SGDMA is designed to be compatible with the BDMA;
-design of DMA channel registration;
-an interrupt design;
interrupt design for BDMA;
an interrupt design of the SGDMA;
interrupt and poll configurable designs.
2. The method of claim 1, wherein the BDMA transfer scheme is designed to be divided into a sending process and a receiving process; and (3) a sending process: acquiring a virtual address and a length of data to be sent, mapping a memory physical address, filling a BDMA-DESC source physical address register, filling a BDMA-DESC data length register, and completing the sending process after the device finishes sending and generates a DMA to finish interrupt generation; the receiving process comprises the following steps: applying a continuous memory area for data to be received in advance as a target virtual address, mapping the physical address of the memory in the area as a target physical address, filling a target physical address register of the BDMA-DESC, after the DMA finishes the interrupt generation, acquiring the received data through the target virtual address and the DMA-DESC data length register, and finishing the receiving process.
3. The method of claim 1, wherein the SGDMA transfer scheme design includes SGDMA-DESC initialization, sending, and receiving processes;
specifically, the SGDMA-DESC initializes: applying a continuous memory as a descriptor ring for storing SGDMA-DESC, and mapping the part of memory as a physical address; and (3) a sending process: the method comprises the steps of obtaining a virtual address linked list of a data block linked list to be sent, mapping the virtual address linked list into a physical address linked list, storing physical addresses and length information into an SGDMA-DESC descriptor ring, writing a first descriptor physical address and a tail descriptor physical address of a descriptor sequence used in the ring into an SG descriptor head register and an SG descriptor tail register respectively, generating DMA completion interruption after equipment finishes sending, and finishing the sending process. The receiving process comprises the following steps: the method comprises the steps of forming a memory block chain table annular structure for a memory applying continuous data to be received in advance, mapping the memory to obtain a physical address, filling physical address information of the memory block chain table annular structure into an SGDMA-DESC descriptor ring one by one, obtaining received data descriptor sections on the SGDMA-DESC descriptor ring through an SG descriptor head register and an SG descriptor tail register after the DMA finishes interrupt generation, obtaining the head and the tail of a data block chain received at this time on the corresponding memory block chain table annular structure through descriptor information in the received data descriptor sections, and finishing the receiving process.
4. The method of claim 1, wherein designing by DMA-DESC in SGDMA for compatibility with BDMA comprises: in BDMA mode, only one DESC on a DESC ring is used at a time; for transmission, pre-storing a source physical address, a source virtual address and a data length of data to be transmitted to a current DESC on a DESC ring, writing the source physical address and the data length on the current DESC into a DMA source physical address register and a DMA data register respectively, and enabling a current DESC pointer to point to a next new DESC after the data transmission is completed; for receiving, storing a memory address applied in advance into a current DESC ring, writing a target physical address into a DMA target address register, and after the receiving is interrupted, acquiring received data through a length register and a memory virtual address stored in the current DESC, so that a current DESC pointer points to a next new DESC.
5. The method of claim 1, wherein the design of the DMA channel registration is divided into multiple channels and a single channel; multi-channel: aiming at the condition of abundant DMA channel resources, a plurality of devices respectively use respective DMA channels, and the transmission and the reception of each device are also respectively carried out by using the independent DMA channels; single channel: aiming at the condition that DMA channel resources are short, a lock protection mechanism is designed for each channel, and if the channel needs to be shared, the channel lock is acquired on a specific path until the lock is released after DMA transfer is completed.
6. The method of claim 1, wherein the interrupt design includes a send phase and a receive phase; specifically, in the sending stage, a source physical address and a destination physical address of data to be transmitted and the length of the data to be transmitted are filled into a DMA control register, the data can be sent, and DMA completion interruption is generated after the transmission is completed; after the DMA bottom layer equipment receives the data, the source address is the DMA equipment, the source address, the destination physical address and the data length of the data are known, the data are transmitted to the memory, and DMA completion interruption is generated after the transmission is completed.
7. The multi-device compatible DMA data transfer engine design method of claim 1, wherein the interrupt design of the BDMA specifically comprises: in the sending process, calling a DMA data transmission interface to fill the source physical address, the destination physical address and the data length of the common part, and finishing a data sending process after finishing the interrupt generation of the DMA;
in the receiving process, a memory for preparing to receive data fills a target physical address, equipment interruption is generated when equipment at the bottom layer of the DMA receives the data, a DMA data transmission interface is called to partially fill a source physical address and a data length together, and a data receiving process is completed after the interruption of the DMA is completed.
8. The method of claim 1, wherein the SGDMA interrupt design specifically comprises: in the sending process, the public part is filled in the DESC head and the DESC tail by calling a DMA data transmission interface, and after the DMA finishes the interrupt generation, a data sending process is finished;
in the receiving process, a memory for receiving data is prepared to fill a target physical address, equipment interruption is generated when equipment at the bottom layer of the DMA receives the data, at the moment, a public part is filled in a DESC head and a DESC tail by calling a DMA data transmission interface, and after the interruption generation of the DMA is completed, a data receiving process is completed.
9. The method of claim 1, wherein the interrupt and polling configurable design includes a polling mode, an interrupt mode, and an interrupt and polling mode; a polling mode: if the polling in the equipment data receiving FIFO is not empty each time, calling a data receiving interface to receive data until the state of the equipment data receiving FIFO is empty; an interruption mode: if the DMA bottom layer equipment generates the receiving equipment interrupt, acquiring the data length and the source physical address register in a receiving FIFO controller register, filling a DMA control register by combining the prepared target physical address, and realizing a DMA data receiving process after the DMA finishes the interrupt; interrupt and poll mode: the method comprises the following steps that a polling and interruption combined mode can be used under the condition that the data transmission bandwidth is uncertain, each time data is received through interruption triggering, equipment interruption is closed after the equipment interruption is generated, data are received in a polling mode until a receiving FIFO is empty, then the equipment interruption is opened, and next interruption is waited to be generated; in order to not affect the real-time performance and the processing performance of an operating system responding to other interrupts, a polling threshold is set, the polling times cannot exceed the polling threshold in one polling, if the polling times exceed the polling threshold, an interrupt receiving flow for interrupt preparation of next data is started, and other interrupt processing routines are scheduled for processing.
10. The method of claim 1, wherein the interrupt processing is performed in a second half of the processing mode, that is, the time-consuming operation is scheduled to be executed in the second half of the interrupt.
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