CN113127253A

CN113127253A - Method for searching memory data applied to data storage device

Info

Publication number: CN113127253A
Application number: CN202010175858.7A
Authority: CN
Inventors: 吴家宏; 杨国政
Original assignee: Asolid Technology Co Ltd
Current assignee: Asolid Technology Co Ltd
Priority date: 2020-01-15
Filing date: 2020-03-13
Publication date: 2021-07-16
Also published as: TW202129650A; TWI703567B

Abstract

The invention provides a data storage device and a searching method of memory data. The searching method comprises the following steps: the method comprises the steps of distinguishing a storage block into a plurality of sub-blocks, wherein each sub-block is divided into a label block and an address information block, and the label block comprises an identifier, a reverse identifier, an error correction code and a reverse error correction code; selecting one of the sub-blocks as a selected sub-block; judging whether the selected sub-block is a reliable data block or not according to the identifier, the reverse identifier, the error correction code and the reverse error correction code; when the selected sub-block is the reliable data block, the address information block of the selected sub-block is read to obtain the storage address information of the code information.

Description

Method for searching memory data applied to data storage device

Technical Field

The present invention relates to a data storage device and a method for searching memory data, and more particularly, to a data storage device for recording a large amount of data and a method for searching memory data.

Background

In response to the requirement of big data analysis, the data storage device is often used to record a large amount of data. The memory of the data storage device may also be used to record code information (code information) related to the memory parameters. When searching and reading the code information, the following problems may occur: firstly, the wrong code information is read because the storage line where the code information is located generates a bad line (bad column) problem; secondly, searching code information to be read in a memory for storing a large amount of data, and often consuming a large amount of time; third, during the reading operation of the memory, the problem of reading interference needs to be avoided so as to maintain the reliability of the read code information.

Based on the above problems, how to obtain code information quickly and reliably becomes an important issue for designers in the field.

Disclosure of Invention

The present invention is directed to a data storage device and a method for searching memory data, which can quickly search out required information from a large amount of data.

According to an embodiment of the present invention, a method for searching data in a memory includes: the method comprises the steps of distinguishing a storage block into a plurality of sub-blocks, wherein each sub-block is divided into a label block and an address information block, and the label block records a plurality of identifiers, a plurality of reverse identifiers, a plurality of error correction codes and a plurality of reverse error correction codes; selecting one of the sub-blocks as a selected sub-block; reading the identifier, the reverse identifier, the error correcting code and the reverse error correcting code in the label block of the selected sub-block, and judging whether the selected sub-block is a reliable data block or not according to the identifier, the reverse identifier, the error correcting code and the reverse error correcting code; when the selected sub-block is a reliable data block, the address information block of the selected sub-block is read to obtain the storage address information of the code information.

In an embodiment of the invention, the identifier, the reverse identifier, the error correction code, and the reverse error correction code identifier are disposed in the tag block in an interleaved manner.

In an embodiment of the invention, the step of determining whether the selected sub-block is a reliable data block according to the identifier, the reverse identifier, the error correction code, and the reverse error correction code includes: calculating a first number of identifiers equal to a first set value; calculating a second number of reverse identifiers equal to the first reverse setpoint; when the first number and the second number are not less than the first threshold, reading the error correction code and the reverse error correction code; selecting a selected error correcting code and a selected reverse error correcting code, wherein the selected error correcting code and the selected reverse error correcting code are complementary; selecting the error correcting code and the reverse error correcting code as a standard error correcting code and a standard reverse error correcting code respectively, calculating a third number of error correcting codes equal to the standard error correcting code, and calculating a fourth number of reverse error correcting codes equal to the standard reverse error correcting code; and when the third number and the fourth number are not less than the second threshold value, judging the selected sub-block as a reliable data block.

In an embodiment according to the present invention, the data of the identifiers are the same, the data of the reverse identifiers are the same, and each identifier is complementary to the data content of the corresponding reverse identifier.

In an embodiment of the present invention, the data of the error correction codes are the same, the data of the inverse error correction codes are the same, and each error correction code is complementary to the data content of the corresponding error correction code.

In an embodiment of the invention, the address information block records a plurality of address information and a plurality of inverted address information in a staggered configuration, and the address information and the corresponding inverted address information form the same set of address information pairs.

In an embodiment of the present invention, each of the address information includes a plurality of bytes, and each of the inverted address information includes a plurality of bytes, wherein, when the selected sub-block is a reliable data block, the step of reading the address information block of the selected sub-block to obtain the storage address information of the code information includes: selecting one of the address information pairs for comparison, and if the address information in the selected address information pair is complementary with the inverted address information, then the pair of address information is called standard address information and standard inverted address information; comparing each byte of standard address information with each address information one by one, and recording the comparison result as the same first quantity; judging whether the first quantity is greater than a first threshold value or not so as to record each byte of the corresponding address information to obtain storage position information; comparing each byte of standard reverse address information with each reverse address information one by one, and recording the comparison result as the same second quantity; and judging whether each second number is greater than a second threshold value or not to record each byte of the corresponding reverse address information so as to obtain reverse storage position information.

In an embodiment of the invention, the searching method includes reading code information in the memory according to the storage address information.

In an embodiment of the invention, the block reading selection code selects one of the sub-blocks as the selected sub-block according to the block selection code.

According to an embodiment of the present invention, a data storage device includes a memory and a controller. The memory stores code information. The controller is coupled to the memory and configured to execute the method for searching the memory data.

Based on the above, in the embodiments of the present invention, the tag block is set in the plurality of sub-blocks of the memory, the reliability of the corresponding sub-block is determined by the identifier, the reverse identifier, the error correction code, and the reverse error correction code in the tag block, and the address information stored in the reliable data block is read, so that the storage address information of the code information with high reliability can be quickly obtained, and the correct code information can be quickly read.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a diagram illustrating a method for searching data in a memory according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a sub-block of a memory according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a method for searching data in a memory according to another embodiment of the present invention;

FIG. 4 is a diagram illustrating a sub-block according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of one embodiment of an identifier, reverse identifier, according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating steps for determining reliable data blocks according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of an embodiment of an error correction code and an inverse error correction code according to an embodiment of the invention;

FIG. 8 is a flowchart illustrating the steps of determining reliable data blocks according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating an embodiment of an address information block;

FIG. 10 is a flowchart illustrating an exemplary address information search operation;

FIG. 11 is a diagram illustrating a data storage device according to an embodiment of the present invention.

Description of the reference numerals

1110: a controller;

1120: a memory;

1130: a selection code generator;

11: a data storage device;

210: a storage block;

211-214: a sub-block;

400: a sub-block;

ADD: an address information block;

AG 1-AGM: a pair of address information;

CIADD 1-CIADDM: address information;

CIADDI 1-CIADDIM: reverse address information;

ECC 1-ECCN: an error correction code;

ECCI 1-ECCIN: an inverse error correction code;

G1-GN: a group;

s1010 to S1050: searching address information;

s110 to S140, S310 to S380: searching data of the memory;

s610 to S640, S810 to S840: determining a reliable data block;

SEL: selecting a code;

TAG: a label block;

TG 1-TGN, TAG 1-TAG 256: an identifier;

TGI 1-TGIN, TAGI 1-TAGI 256: a reverse direction identifier.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Referring to fig. 1, fig. 1 shows a method for searching data in a memory according to an embodiment of the invention. In step S110, the memory block is divided into a plurality of sub-blocks, wherein each sub-block has a tag block and an address information block. The tag block records a plurality of identifiers, a plurality of reverse identifiers, a plurality of error correction codes, and a plurality of reverse error correction codes. The address information block records a plurality of address information and a plurality of inverted address information, wherein the address information is a storage address of the code information in the memory.

Referring to fig. 2, fig. 2 is a schematic diagram illustrating a sub-block of a memory according to an embodiment of the invention. The memory block 210 of the memory can be divided into 4 sub-blocks 211-214, for example.

Please note that, in the present embodiment, when the memory block records the storage address of the code information, the plurality of identifiers, the plurality of inverse identifiers, the plurality of error correction codes, the plurality of inverse error correction codes, the plurality of address information and the plurality of inverse address information are recorded in one sub-block (e.g., the sub-block 211), and the data of the sub-block 211 is copied to other sub-blocks (e.g., the sub-blocks 212-214). That is, in the initial state, the same data is recorded in a plurality of sub-blocks of the memory block. However, after a certain period of time has elapsed since the sub-blocks 211-214 are read, some of the data in the sub-blocks 211-214 may be altered due to read disturb or other factors.

Referring back to fig. 1, in step S120, one of the plurality of sub-blocks is selected as the selected sub-block. In step S120, the sub-block can be selected according to a block selection code. The block select code may be external to the memory and may have multiple bits. The number of bits of the selected code may be determined according to the number of sub-blocks. The number of sub-blocks is less than or equal to the power of 2A, where A is the number of bits in the selected code.

In step S130, the identifier, the reverse identifier, the error correction code, and the reverse error correction code in the tag block of the selected sub-block are read. And judging whether the selected sub-block is a reliable data block according to the identifier, the reverse identifier, the error correction code and the reverse error correction code. Please note that, in the present embodiment, a plurality of identifiers and a plurality of reverse identifiers are recorded in one tag block. The identifier and the plurality of reverse identifiers are preset values, and in the initial state, the data of all identifiers recorded in one tag block are the same, the data of all reverse identifiers are also the same, and the identifiers are complementary with the data of the reverse identifiers.

In another aspect, the predetermined identifier may have a plurality of bits, wherein the data content of adjacent bits is complementary. That is, taking the identifier with 8 bits as an example, the identifier may be 0x55 or 0xAA with 16 bits. In contrast, in the initial state, the identifier and the reverse identifier are complementary, again taking 8 bits as an example, when the identifier is 0x55 with 16 bits, the reverse identifier is 0xAA with 16 bits; when the identifier is a 16-bit 0xAA, the reverse identifier is a 16-bit 0x 55.

As for the error correction code and the inverse error correction code, the error correction code and the inverse error correction code may be preset values. In the initial state, the data of all error correction codes recorded in one tag block is the same, and the data of all inverse error correction codes recorded in one tag block is also the same. Further, in the initial state, the error correction code is complementary to the data of the inverse error correction code. For example, in the case of an error correction code having 8 bits, the error correction code may be preset to 0x80 in hexadecimal; in contrast, the reverse error correction code may be 0x7F in hexadecimal.

In this embodiment, the identifier and the reverse identifier may be alternately disposed at consecutive addresses in the tag block, and the error correction code and the reverse error correction code may be alternately disposed at consecutive addresses in the tag block. In an embodiment of the present invention, the identifier, the reverse identification code, the error correction code, and the reverse error correction code may be sequentially disposed at consecutive addresses in the tag block.

Of course, the sequence of the addresses of the tag, the reverse tag, the error correction code and the reverse error correction code in the tag block is not limited to the above manner, and the designer may set the addresses in any sequence according to actual requirements. The number of bits of the identifier, the reverse identifier, the error correction code, and the reverse error correction code is not particularly limited, and the 8-bit example is only for convenience of description and is not intended to limit the scope of the present invention.

In step S130, the embodiment may determine whether the corresponding sub-block is a reliable data block by reading the identifier, the reverse identifier, the error correction code, and the reverse error correction code in the tag block, and checking the complementary status of the data of the identifier and the reverse identifier, and checking the mutation status of the error correction code and the reverse error correction code. And, according to the determination result in step S130, when the sub-block is a reliable data block, reading the address information block of the sub-block, and thereby obtaining the storage address information of the code information.

Referring to fig. 3, fig. 3 is a flowchart illustrating an operation of a method for searching data in a memory according to another embodiment of the invention. The memory block has for example 8 kbytes. In fig. 3, after the big data search is started, step S310 determines the block selection code, and step S321 is performed when the selection code is b10 in binary; step S322 is executed when the tile selection code is binary b 00; and performs step S323 when the tile selection code is b11 or b01 in binary.

In step S321, search for 4k to 6k sub-blocks (range 2) in the storage block; step S322, searching 0 k-2 k sub-blocks (range 0) in the storage block; in step S323, search is performed for 2k to 4k sub-blocks (range 1) in the block.

Step S330 determines whether the current search range is less than or equal to 3, if the search range is less than or equal to 3, it indicates that not all the sub-blocks have been searched, and step S340 can be executed to continue the search. On the other hand, if the search range is larger than 3, it indicates that all the sub-blocks have been searched, and step S360 indicates that the search operation has failed.

In step S340, it is determined whether the address information of the code information is obtained, and step S380 is executed to indicate that the search is successful under the condition that the address information of the code information is obtained. In addition, under the condition that the address information of the code information is not obtained, step S350 is executed to search the next sub-block (search range +1) in the search range under the condition that the result coincidence number is smaller than the threshold value but larger than the retry threshold number (step S370), step S330 is executed again, and under the condition that the result coincidence number is not larger than the retry threshold value, step S360 is entered to indicate that the block search operation fails.

Under the condition that the address information of the code information is obtained, the required code information can be read out from the memory according to the address information of the code information.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a sub-block according to an embodiment of the invention. The sub-block 400 has a TAG block TAG and an address information block ADD. The TAG records identifiers TG1 TGN, reverse identifiers TGI1 TGIN, error correction codes ECC1 ECCN, and reverse error correction codes ECCI1 ECCIN of a plurality of groups G1 GN. Taking the first group G1 as an example, the first group G1 sequentially records an identifier TG1, a reverse identifier TGI1, an error correction code ECC1, and a reverse error correction code ECCI 1.

In the address information block ADD, address information CIADD1 to ciadm and reverse address information CIADDI1 to CIADDIM of code information are recorded in order. Wherein the address information CIADD 1-ciadm and the reverse address information CIADDI 1-CIADDIM are interleaved in the address information block ADD.

The address information CIADD1 to ciadm and the corresponding reverse address information CIADD1 to CIADDIM form a plurality of address information groups AG1 to AGM, respectively, and each of the address information CIADD1 to CIADDIM and the corresponding reverse address information CIADDI1 to CIADDIM form an address information pair).

Referring to fig. 5, fig. 5 is a schematic diagram illustrating an embodiment of an identifier and a reverse identifier according to an embodiment of the present invention. In fig. 5, for example, 256 identifiers TAG 1-TAG 256 are recorded in the TAG block TAG, wherein the identifiers TAG 1-TAG 256 may be equal to 0x55 in hexadecimal in the initial state. The TAG block TAG records the reverse identifiers TAGI1 TAGI256 corresponding to the identifiers TAG1 TAG256, respectively, and the reverse identifiers TAGI1 TAGI256 are all equal to 0xAA in hexadecimal in the initial state.

Please refer to fig. 6, which is a flowchart illustrating a procedure for determining reliable data blocks according to an embodiment of the present invention. In step S610, 256 TAG TAGs 1 through 256 of the TAG tiles TAG are read, and it is determined whether the number of the TAG TAGs 1 through TAG256 is equal to 0x55 and is greater than or equal to a threshold value (64) (1/4 of the total number of the TAG TAGs 1 through TAG 256). If it is determined that no data variation occurs in the number of the read identifiers TAG1 through TAG256, which is not less than 1/4, step S620 may be performed. On the other hand, if the number of data variations among the read identifiers TAG 1-TAG 256 exceeds 3/4, the corresponding sub-block is determined to be an unreliable sub-block, and step S640 is performed to indicate a failure.

Step S620 reads the 256 reverse identifiers TAGI1 to TAGI256 in the TAG, and determines whether the number of the reverse identifiers TAGI1 to TAGI256 is equal to 0xAA or greater than or equal to a reference value (64) (1/4 of the total number of the reverse identifiers TAGI1 to TAGI 256). If it is determined that the number of the read reverse identifiers TAGI1 to TAGI256 is not less than 1/4 without data variation, step S630 is executed to search for the error correction code and the reverse error correction code. On the other hand, if it is determined that the number of data variations occurring in the read reverse identifiers TAGI 1-TAGI 256 exceeds 3/4, the corresponding sub-block is an unreliable sub-block, and step S640 is performed to indicate a failure.

It should be noted that the reference value is not necessarily set to 64, and the designer may set the threshold value according to the required degree of stringency. When the strictness of determining whether a sub-block is a reliable data block is relatively high, the threshold may be set to be greater than 64, i.e., to account for a relatively high proportion of all the identifiers TAG1 through TAG256 and the reverse identifiers TAG1 through TAG 256. In contrast, when the strictness of determining whether the sub-block is a reliable data block is relatively low, the threshold may be set to be less than 64, i.e., to be a relatively low ratio of all the identifiers TAG1 TAG256 and the reverse identifiers TAGI1 TAGI 256.

Referring to fig. 7 and 8, fig. 7 is a schematic diagram illustrating an error correction code and an inverse error correction code according to an embodiment of the invention, and fig. 8 is a flowchart illustrating a step of determining a reliable data block according to an embodiment of the invention. In FIG. 7, the error correction codes ECC1 ECCI256 and the corresponding reverse error correction codes ECCI1 ECCI256 are recorded in the tag chunk. In the initial state, the data of the error correction codes ECC 1-ECC 256 are all the same and equal to, for example, 0x80 in hexadecimal, and the data of the inverse error correction codes ECCI 1-ECCI 256 are all the same and equal to, for example, 0x7F in hexadecimal, wherein the error correction codes ECC 1-ECC 256 in the initial state are complementary to the inverse error correction codes ECCI 1-ECCI 256.

In fig. 8, step S810 reads one of the error correction codes ECC1 to ECC256 (for example, reads the first group of error correction codes ECC1), reads the corresponding reverse error correction code ECCI1, and determines whether the error correction code ECC1 is complementary to the reverse error correction code ECCI 1. If the ECC1 is complementary to the ECCI1, it indicates that there is no data variation between the ECC1 and the ECCI1, and the ECC1 and ECCI can be set as a standard ECC and a standard ECCI, respectively, and step S820 is performed. On the other hand, if the error correction code ECC1 and the reverse error correction code ECCI1 are not complementary to each other, indicating that the error correction code ECC1 and the reverse error correction code ECCI1 have data variations, step S811 is performed to check the next set of error correction codes (e.g., the error correction code ECC2) and the next set of reverse error correction codes (e.g., the reverse error correction code ECCI2), and step S810 is re-executed.

In step S820, the error correction codes ECC 1-ECC 256 of each group are compared with the standard error correction code, and whether the number of the error correction codes ECC 1-ECC 256 identical to the standard error correction code is greater than a threshold (64) is calculated, and if the number of the error correction codes ECC 1-ECC 256 identical to the standard error correction code is not less than the threshold, step S830 is performed. In contrast, if the number of the error correction codes ECC 1-ECC 256 is less than the threshold, step S850 is executed to indicate that the search fails.

In step S830, the reverse error correction codes ECCI 1-ECCI 256 of each group are compared with the standard reverse error correction code, and whether the number of the reverse error correction codes ECCI 1-ECCI 256 identical to the standard reverse error correction code is greater than a threshold value (64) is calculated, and if the number of the reverse error correction codes ECCI 1-ECCI 256 identical to the standard reverse error correction code is not less than the threshold value, step S840 is performed to search for the address information.

It should be noted that in step S830, the operation of comparing the reverse error correction codes ECCI1 to ECCI256 of each group with the standard reverse error correction code may be performed by determining whether or not the reverse error correction codes ECCI1 to ECCI256 of each group are complementary to the standard error correction code.

Please refer to fig. 9 and 10 for address information searching operation, wherein fig. 9 is a schematic diagram illustrating an address information block according to an embodiment of the present invention, and fig. 10 is a flowchart illustrating an address information searching operation according to an embodiment of the present invention. In fig. 9, a plurality of address information CIADD1 to CIADD128 and a plurality of reverse address information CIADDI1 to CIADDI128 storing code information are recorded in the address information block. In the initial state, all address information CIADD 1-CIADD 128 are identical and equal to 0x12345678 in hexadecimal, for example. Also, in the initial state, all of the reverse address information CIADDI 1-CIADDI 128 are the same and equal to, for example, 0xEDCBA987 in hexadecimal. The address information CIADD1 to CIADD128 and the reverse address information CIADD1 to CIADD128 are alternately arranged in the address information block, and the address information CIADD1 to CIADD128 and the reverse address information CIADD1 to CIADD128 respectively corresponding thereto form a plurality of address information pairs CADDP1 to CADDP 128.

In fig. 10, step S1010 reads one of the address information CIADD1 to CIADD128 (for example, reads the address information CIADD1 of the first group), reads the corresponding reverse address information CIADD1, and determines whether the address information CIADD1 is complementary to the reverse address information CIADD 1. When the address information CIADD1 and the reverse address information CIADDI1 are complementary, the address information CIADD1 and the reverse address information CIADDI1 are respectively set as the standard address information and the standard reverse address information, and step S1021 is performed. On the other hand, when the address information CIADD1 and the reverse address information CIADDI1 are not complementary, step S1011 is executed to perform the reading and determining operations of the next group of address information (e.g., the second group of address information CIADD2) and the reverse address information (e.g., the second group of reverse address information CIADDI 2).

In the present embodiment, taking the address information CIADD1 as an example, the address information CIADD1 has a plurality of bytes (4 in the present embodiment), which are respectively the 0 th byte composed of "7" and "8"; byte 1 consisting of "5, 6"; byte 2 consisting of "3, 4"; and a 3 rd byte consisting of "2, 1". Similarly, taking the reverse address information CIADDI1 as an example, the reverse address information CIADDI1 has the same number of bytes (4), which are respectively the 0 th byte composed of "8 and 7"; byte 1 consisting of "a, 9"; byte 2 consisting of "C, B"; and a 3 rd byte consisting of "E, D".

Based on the above, step S1021 to step S1024 compare the address information CIADD1 to CIADD128 with the standard address information byte by byte. To explain in detail, in step S1021, the 0 th byte of each of the address information CIADD1 to CIADD128 is compared with the 0 th byte of the standard address information, and the comparison result is calculated to be the same number. If the calculated number is not less than the threshold value (═ 32), step S1022 is performed. On the contrary, if the calculated number is smaller than the threshold value (32), step S1050 is executed to indicate that the search result is a failure.

Next, in step S1022, the 1 st byte of each of the address information CIADD1 to CIADD128 is compared with the 1 st byte of the standard address information, and the same number is calculated as the comparison result. If the calculated number is not less than the threshold value (═ 32), step S1023 is executed. On the contrary, if the calculated number is smaller than the threshold value (32), step S1050 is executed to indicate that the search result is a failure.

Similarly, in steps S1023 and S1024, the 2 nd and 3 rd bytes in each of the address information CIADD1 to CIADD128 are compared with the 2 nd and 3 rd bytes of the standard address information, respectively, and step S1031 is executed if the calculated number is not less than the threshold value (═ 32). If the number calculated in one of the steps S1023 and S1024 is smaller than the threshold value (32), step S1050 is executed to indicate that the search result is a failure.

Step S1031 to step S1034 make byte-by-byte comparison between each byte of the reverse address information CIADDI1 to CIADDI128 and the standard address information, and determine whether the two are complementary. In detail, step S1031 calculates the number of complementary bytes of each 0 th byte of the reverse address information CIADDI1 to CIADDI128 to the 0 th byte of the standard address information, and if the calculated number is not less than the threshold value (═ 32), step S1032 is executed. On the contrary, if the calculated number is smaller than the threshold value (═ 32), step S1050 is executed to indicate that the search result is a failure.

Step S1032 calculates the number of 1 st bytes of the reverse address information CIADDI1 to CIADDI128, which is complementary to the 1 st byte of the standard address information, and if the calculated number is not less than the threshold value (32), step S1033 is performed. On the contrary, if the calculated number is smaller than the threshold value (═ 32), step S1050 is executed to indicate that the search result is a failure.

By analogy, steps S1033 and S1034 respectively calculate the number of each 2 nd and 3 rd byte of the reverse address information CIADDI1 to CIADDI128, which is complementary to the 2 nd and 3 rd byte of the standard address information. If the calculated number is not less than the threshold value (32), step S1040 is performed, and the output address information (equal to the standard address information) of the code information is obtained. On the contrary, if one of the calculated numbers is smaller than the threshold value (═ 32), step S1050 is executed to indicate that the search result is a failure.

Incidentally, the operations in steps S1031 to S1034 may be modified such that each byte of the reverse address information CIADDI1 to CIADDI128 is compared with the standard reverse address information byte by byte, and step S1040 or step S1050 is executed by calculating the same number of comparison results as the size relationship with the threshold value (═ 32).

In addition, the execution sequence of steps S1021 to step 1024 is not limited, and the designer can design the execution sequence of steps S1021 to step 1024. The execution order of steps S1031 to 1034 is not limited, and steps S1031 to 1034 may be executed in preference to steps S1021 to 1024.

In addition, step S1040 may obtain the address information of the stored code information when the execution results of steps S1021 to 1024 and steps S1031 to 1034 are in real time in sequence, so that the code information stored in the memory may be obtained quickly and accurately by reading the code information according to the output address information.

Referring to fig. 11, fig. 11 is a schematic diagram illustrating a data storage device according to an embodiment of the invention. The data storage device 11 includes a controller 1110, a memory 1120, and a selector code generator 1130. The selection code generator 1130 may be a hardware fuse device and is configured to provide the selection code SEL. The controller 1110 is coupled to the memory 1120 and the selection code generator 1130, and performs a search process of the code information according to the selection code SEL in fig. 3. The controller 1110 executes the operation flows shown in fig. 6, 8, and 10 to quickly and safely obtain the storage address information of the code information, so as to read the code information stored in the memory in which the large data is described.

In this embodiment, the memory 1120 can be any type of memory. In an embodiment of the present invention, the memory 1120 may be a flash memory, such as a NAND flash memory. The controller 1110 may be a processor with computing capabilities. Alternatively, the controller 1110 may be a Hardware Circuit designed by Hardware Description Language (HDL) or any other digital Circuit design known to those skilled in the art, and implemented by Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD) or Application-specific Integrated Circuit (ASIC).

In summary, the present invention divides the storage block into a plurality of sub-blocks, and each sub-block has a tag block and an address information block. By making a decision on the identifier, the reverse identifier, the error correction code, and the reverse error correction code in the label block, the reliability of the sub-block can be known. Therefore, the address information block of the reliable sub-block can be read, and the storage address information of the reliable code information can be quickly obtained so as to obtain the code information.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for searching data in a memory, comprising:

the method comprises the steps of distinguishing a storage block into a plurality of sub-blocks, wherein each sub-block is divided into a label block and an address information block, and the label block records a plurality of identifiers, a plurality of reverse identifiers, a plurality of error correction codes and a plurality of reverse error correction codes;

selecting one of the sub-blocks as a selected sub-block;

reading the plurality of identifiers, the plurality of reverse identifiers, the plurality of error correction codes, and the plurality of reverse error correction codes in the tag block of the selected sub-block, and determining whether the selected sub-block is a reliable data block according to the plurality of identifiers, the plurality of reverse identifiers, the plurality of error correction codes, and the plurality of reverse error correction codes; and

when the selected sub-block is the reliable data block, reading the address information block of the selected sub-block to obtain storage address information of code information.

2. The search method of claim 1, wherein the identifiers, the reverse identifiers, the error correction codes, and the reverse error correction code identifiers are interleaved in the tag block.

3. The method of claim 2, wherein the step of determining whether the selected sub-block is the reliable data block according to the identifiers, the reverse identifiers, the error correction codes and the reverse error correction codes comprises:

calculating a first number of the plurality of identifiers equal to a first set value

Calculating a second number of the plurality of reverse identifiers equal to the first reverse set point

When the first number and the second number are not less than a first threshold, reading the error correction codes and the reverse error correction codes

Selecting a selected error correcting code and selecting an inverse error correcting code, wherein the selected error correcting code and the selected inverse error correcting code are complementary, and the selected error correcting code and the selected inverse error correcting code are a standard error correcting code and a standard inverse error correcting code respectively

Calculating a third number of the plurality of error correction codes equal to the standard error correction code

Calculating a fourth number of the plurality of inverse error correction codes equal to the standard inverse error correction code; and

and when the third number and the fourth number are not less than a second threshold value, judging the selected sub-block as the reliable data block.

4. The searching method of claim 3, wherein the data of the identifiers are the same, the data of the reverse identifiers are the same, and each identifier is complementary to the data content of the corresponding reverse identifier.

5. The method of claim 3, wherein the plurality of error correction codes have the same data, the plurality of inverse error correction codes have the same data, and each error correction code is complementary to the data content of the corresponding error correction code.

6. The method of claim 1, wherein the address information block records a plurality of address information and a plurality of inverted address information in a staggered configuration, and the plurality of address information and the plurality of inverted address information respectively form a plurality of address information pairs.

7. The searching method of claim 6, wherein each of the address information includes a plurality of bytes, each of the inverted address information includes a plurality of bytes,

wherein, when the selected sub-block is the reliable data block, the step of reading the address information block of the selected sub-block to obtain the storage address information of the code information comprises:

selecting one of the plurality of address information pairs as a standard address information pair, wherein standard address information in the standard address information pair is complementary to standard inverted address information;

comparing the standard address information with each address information byte by byte, and recording a plurality of first numbers with the same comparison result;

judging whether each first quantity is greater than a first threshold value or not to record each byte of corresponding address information so as to obtain each byte of the storage address information;

comparing the standard reverse address information with each reverse address information byte by byte, and recording a plurality of second numbers with the same comparison result; and

and judging whether each second quantity is greater than a second threshold value or not to record each byte of the corresponding reverse address information so as to obtain each byte of the reverse storage address information.

8. The method of claim 1, further comprising reading the code information from the memory according to the storage address information.

9. The method of claim 1, wherein selecting one of the sub-blocks as the selected sub-block comprises:

reading a selection code, and selecting one of the sub-blocks as the selected sub-block according to the selection code.

10. The searching method of claim 9, further comprising:

and when the selected sub-block is not the reliable data block, changing the selection code and selecting another sub-block of the plurality of sub-blocks as the selected sub-block.

11. The searching method of claim 1, wherein the identifier has a plurality of bits, and the data contents of two adjacent bits of the plurality of bits are complementary.

12. A data storage device, comprising:

a memory for storing code information; and

a controller coupled to the memory for:

dividing a storage block into a plurality of sub-blocks, wherein each sub-block is provided with a tag block and an address information block, and the tag block records a plurality of identifiers, a plurality of reverse identifiers, a plurality of error correction codes and a plurality of reverse error correction codes;

selecting one of the sub-blocks as a selected sub-block;

and when the selected sub-block is the reliable data block, reading the address information block of the selected sub-block to obtain the storage address information of the code information.

13. The data storage device of claim 12, wherein the controller is further configured to:

calculating a first number of the plurality of identifiers equal to a first set value;

calculating a second number of the plurality of reverse identifiers equal to a first reverse set point;

when the first number and the second number are not less than a first threshold, reading the error correction codes and the reverse error correction codes;

selecting a standard error correcting code and a standard reverse error correcting code, wherein the standard error correcting code and the standard reverse error correcting code are complementary;

calculating a third number of the plurality of error correction codes equal to the standard error correction code;

14. The data storage device of claim 13, wherein the data of the plurality of identifiers is the same, the data of the plurality of reverse identifiers is the same, and each of the identifiers is complementary to the data content of a corresponding each of the reverse identifiers.

15. The data storage device of claim 13, wherein the plurality of error correction codes are identical in data, the plurality of inverse error correction codes are identical in data, and each of the error correction codes is complementary to a data content of a corresponding one of the error correction codes.

16. The data storage device of claim 12, wherein the address information block records a plurality of address information and a plurality of inverted address information in a staggered arrangement, and the plurality of address information and the plurality of inverted address information respectively form a plurality of address information pairs.

17. The data storage device of claim 16, wherein each of the address information comprises a plurality of bytes, and wherein each of the inverted address information comprises a plurality of bytes the controller is further configured to:

selecting one of the plurality of address information pairs as a standard address information pair, wherein one standard address information of the standard address information pair is complementary to standard inverted address information;

and judging whether each second quantity is greater than a second threshold value or not to record each byte of the corresponding reverse address information so as to obtain each byte of the reverse output position information.

18. The data storage device of claim 12, wherein the controller is further configured to read the code information from the memory according to the storage address information.

19. The data storage device of claim 12, further comprising:

a selection code generator coupled to the controller for providing a selection code,

the controller selects one of the sub-blocks as the selected sub-block according to the selection code.

20. The data storage device of claim 19 wherein the controller alters the selection code and selects another of the plurality of sub-blocks as the selected sub-block when the selected sub-block is not the reliable data block.