CN113126422B - OPC correction method for improving metal wire process hot spot - Google Patents
OPC correction method for improving metal wire process hot spot Download PDFInfo
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- CN113126422B CN113126422B CN202110226492.6A CN202110226492A CN113126422B CN 113126422 B CN113126422 B CN 113126422B CN 202110226492 A CN202110226492 A CN 202110226492A CN 113126422 B CN113126422 B CN 113126422B
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- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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Abstract
The invention discloses an OPC correction method for improving metal wire process hot spots, which comprises the following steps: firstly, carrying out first double pattern splitting and OPC correction on an original mask plate layout and screening out a metal wire process hot spot pattern close to a device auxiliary pattern; secondly, splitting double patterns for the second time, coloring all the device auxiliary patterns near the metal wire process hot spot patterns into different colors, re-splitting the original mask plate layout, and splitting the metal wire process hot spot patterns and the nearby device auxiliary patterns onto the first and second layers of mask plate layouts respectively; and thirdly, carrying out second OPC correction to obtain a final mask plate layout. The invention can effectively improve the photoetching process window of the metal wire process hot spot pattern and reduce the risk of short circuit or open circuit of the metal wire process hot spot pattern.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing method, and more particularly, to an Optical Proximity Correction (OPC) method for improving a metal line process hot spot.
Background
With the continuous advance of the semiconductor integrated circuit manufacturing industry, semiconductor process processes are moving toward smaller and smaller feature sizes. For more advanced processes at 16nm and below, the minimum space period of the pattern in the design layout is far beyond the theoretical pattern resolution limit of 193nm immersion lithography machines. Therefore, the design layout cannot be effectively transferred to the silicon wafer through a single mask plate only by the optical proximity effect correction technology. Double Patterning Technology (DPT), a lithography etching-lithography etching (LELE) process Technology, is used to split the original design layout into two mask plates, so that the dense design layout pattern can be exposed and transferred onto the silicon wafer through the two mask plates. Compared with the exposure of a single mask plate, the dual pattern splitting technology increases the period size (pitch) between the pattern patterns of the layout, reduces the requirement of the design layout on a photoetching system, improves the distortion degree of the photoetching process to a great extent, improves the photoetching process window, and is particularly suitable for complicated design patterns such as complicated metal wire layers.
Typical double pattern splitting techniques include coloring and splitting two parts. Coloring means that the pattern of the entire layout is distributed into two different colors as uniformly as possible. To avoid obtaining multiple possible results after splitting, the designer would add a marked graph with fixed coloring to the original design layout, thereby fixing the split result. The coloring process may be understood as assigning a color to an independent pattern on the layout, thereby splitting adjacent patterns having a distance less than a predetermined design rule size onto two masks. In the layout Design Rule (Design Rule), there is a strict Rule limit for the dual pattern split, and all dual pattern split results must meet the Rule. Otherwise, conflict graphs are generated, the graphs cannot be completed through pure coloring and splitting, and the layout is often required to be redesigned, so that the product development cycle is often increased. Secondly, the industry uses the double patterning technique to cut and sew (cut) the layout pattern, but this increases the process difficulty and also has the risk.
Because the density of the metal wire layer layout patterns of the nodes below 16nm is extremely high, even after the layout splits two photomasks, the space period of some patterns is still less than 100nm and is relatively close to the photoetching resolution limit of an immersion photoetching machine. Therefore, even if the double patterning technology is used, for the metal wire layer, because the pattern density of the original design layout is too high, the pattern space period is too short, and a process hot spot of short circuit or open circuit is easy to generate.
Disclosure of Invention
The invention aims to provide an OPC correction method for improving metal wire process hot spots, which can effectively improve the photoetching process window of metal wire process hot spot patterns and reduce the risk of short circuit or open circuit of the metal wire process hot spot patterns.
In order to solve the technical problem, the OPC correction method for improving the metal wire process hot spot provided by the invention comprises the following steps:
firstly, carrying out first double pattern splitting and first OPC correction on an original mask plate layout, and screening out a metal wire process hot spot pattern close to the auxiliary pattern of the device.
And secondly, checking coloring and splitting conditions of the metal wire process hot spot graph and the nearby device auxiliary graph in the first dual graph splitting, and performing second dual graph splitting, wherein in the second dual graph splitting, the device auxiliary graphs nearby the metal wire process hot spot graph are all colored into different colors opposite to the colors of the metal wire process hot spot graph, the original mask plate domain is re-split according to coloring, and the second dual graph splitting divides the metal wire process hot spot graph to a first layer of mask plate domain and divides the device auxiliary graphs nearby the metal wire process hot spot graph to a second layer of mask plate domain.
And thirdly, performing second OPC correction, wherein the second OPC correction is used for performing OPC correction on the first layer of mask plate layout and the second layer of mask plate layout respectively to obtain a final mask plate layout.
In a further improvement, in the first step, the metal line process hot spot pattern includes a metal line pattern with a risk of short circuit or open circuit.
In a further improvement, the metal line process hot spot pattern further comprises the metal line pattern in which the device auxiliary patterns are regularly arranged.
In a further improvement, in the second dual pattern splitting, the coloring and splitting result of the metal line process hot spot pattern is fixed to the coloring and splitting result of the first dual pattern splitting, only the coloring of the device auxiliary pattern near the metal line process hot spot pattern is changed, and the device auxiliary pattern near the metal line process hot spot pattern is completely colored in a different color without violating the design rule.
In the second dual pattern splitting of step two, the coloring and splitting results of the layout patterns other than the device auxiliary patterns, which are all colored to be different colors near the metal wire process hot spot patterns, are also fixed as the coloring and splitting results of the first dual pattern splitting.
In a further improvement, in the second step, the range of the device auxiliary patterns which are all colored in different colors and are positioned near the metal wire process hot spot patterns is within 200 nm.
The further improvement is that the hot spot pattern of the metal wire process is a sparse pattern after the coloring in the second dual pattern splitting is completed.
In a further improvement, in the first dual graph splitting, the coloring and splitting are performed in a uniform distribution manner.
The further improvement is that, in the second OPC correction in the third step, the OPC correction on the first-layer mask layout includes the following sub-steps:
and carrying out rule-based OPC correction on the first layer mask plate layout to obtain a first target layer.
And filling a sub-resolution auxiliary pattern in the area, near the metal wire process hot spot pattern, of the first target layer, where the device auxiliary pattern is removed.
And carrying out model-based OPC correction on the first target layer to obtain a first layer final mask plate layout corresponding to the first layer mask plate layout.
The further improvement is that in the second OPC of the third step, the OPC of the second layer mask layout obtains a second layer final mask layout, and the final mask layout is composed of the first layer mask layout and the second layer final mask layout.
According to the method, for the metal wire process hot spot patterns close to the auxiliary patterns of the devices, the first double pattern splitting and the first OPC correction are carried out, the metal wire process hot spot patterns are screened out according to the first OPC correction result, then the second double pattern splitting is carried out, the auxiliary patterns of the devices close to the metal wire process hot spot patterns in the second double pattern splitting are colored into different colors, namely, the colors opposite to the colors of the metal wire process hot spot patterns, and the splitting is carried out according to the coloring, so that the metal wire process hot spot patterns and the adjacent auxiliary patterns of the devices can be split into mask layouts in different layers, namely, a first layer of mask layout and a second layer of mask layout, the areas close to the metal wire process hot spot patterns can be sparse areas, and the increase of sparsity close to the metal wire process hot spot patterns can provide enough space for filling the sub-resolution auxiliary patterns, so that photoetching process windows of the metal wire process hot spot patterns can be effectively increased, and the risk of short circuit or open circuit of the metal wire process hot spot patterns is reduced.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flowchart of an OPC correction method for improving metal line process hot spots according to an embodiment of the present invention;
FIG. 2A is a layout pattern structure near a colored metal line process hot spot pattern of a first double pattern split according to a first method step of the present invention;
FIG. 2B is a layout pattern structure of a colored metal line process hot spot pattern of a second double pattern split according to method step two of the present disclosure;
fig. 2C is a layout graph structure in the OPC correction of the first-layer mask layout by the second OPC correction in the third step of the method according to the embodiment of the present invention.
Detailed Description
FIG. 1 is a flow chart of an OPC correction method for improving metal line process hot spots according to an embodiment of the present invention; as shown in fig. 2A, it is a layout pattern structure near a colored metal line process hot spot pattern of the first double pattern splitting of the method step one in the embodiment of the present invention; as shown in fig. 2B, the layout pattern structure is a layout pattern structure near the colored metal line process hot spot pattern of the second double pattern splitting in the method step two in the embodiment of the present invention; as shown in fig. 2C, the layout graph structure in the OPC correction on the first-layer mask layout for the second OPC correction in the third step of the method according to the embodiment of the present invention is shown, and the OPC correction method for improving the metal wire process hot spot according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 2A, a first double pattern splitting and a first OPC correction are performed on an original mask layout, and a metal line process hot spot pattern near a device auxiliary pattern is screened out.
In fig. 2A, the figures in the region corresponding to the dashed box 101 are all device auxiliary figures, and the figures below the dashed box 101 are all metal line figures.
In the first double graph splitting, each graph is colored by two colors and split according to the coloring. And in the first dual graph splitting, coloring and splitting are carried out in an evenly distributed mode.
The metal wire pattern corresponding to the mark 1 and the device auxiliary pattern corresponding to the mark 2 are separated onto the same mask plate layout on one layer, and the metal wire pattern corresponding to the mark 3 and the device auxiliary pattern corresponding to the mark 4 are separated onto the same mask plate layout on the other layer.
The length of the metal line pattern closest to the area 101 in the metal line pattern corresponding to the mark 1 is limited by another mask layout, so that the metal line pattern cannot grow outwards correspondingly through OPC, and the space reaching the metal line pattern below is small, so that the sub-resolution auxiliary pattern 6 cannot be added. And the space of the device auxiliary pattern which is uniformly split up when the device auxiliary pattern reaches the upper part is too small, so that the sub-resolution auxiliary pattern 6 cannot be filled. Through OPC simulation inspection, it is found that the metal wire open circuit is easily generated at the position, and the photoetching process window is smaller. That is, the metal line pattern with shorter length corresponding to the mark 1 in fig. 2A is the metal line process hot spot pattern, which is screened out in the first step.
In fig. 2A, the metal line pattern that is prone to open circuit is shown, and the metal line hot spot pattern further includes a metal line pattern that is at risk of short circuit and the metal line pattern that is located nearby the device auxiliary pattern and has a regular arrangement. Generally, the spatial period near the hot spot pattern of the metal line process after the first double pattern splitting is completed is close to the lithographic resolution limit of a lithography machine.
And secondly, as shown in fig. 2B, checking coloring and splitting conditions of the metal wire process hot spot pattern and the nearby device auxiliary pattern in the first double pattern splitting, and performing second double pattern splitting, wherein in the second double pattern splitting, the device auxiliary patterns nearby the metal wire process hot spot pattern are all colored into different colors opposite to the colors of the metal wire process hot spot pattern, and the original mask plate layout is re-split according to coloring, and the second double pattern splitting splits the metal wire process hot spot pattern onto a first layer of mask plate layout and splits the device auxiliary patterns nearby the metal wire process hot spot pattern onto a second layer of mask plate layout.
In fig. 2B, the colors of the device assistant patterns located near the metal line process hot spot patterns are all as shown by marks 4, and these colors are opposite to the colors of the metal line process hot spot patterns corresponding to marks 1.
In the method according to the embodiment of the present invention, in the second dual pattern splitting, the coloring and splitting results of the metal wire process hot spot pattern are fixed to the coloring and splitting results of the first dual pattern splitting, only the coloring of the device auxiliary pattern near the metal wire process hot spot pattern is changed, and the device auxiliary patterns near the metal wire process hot spot pattern are all colored in different colors without violating the design rule. In the second double pattern splitting in the second step, the coloring and splitting results of the layout patterns other than the device auxiliary pattern, which are all colored differently near the metal line process hot spot pattern, are also fixed as the coloring and splitting results of the first double pattern splitting. As can be seen from comparison with fig. 2A, in fig. 2B, only the coloring of the device auxiliary pattern corresponding to the two marks 2 appearing in fig. 2B needs to be changed, and the coloring of the other patterns is not superficial. Preferably, the device auxiliary pattern colored in all different colors is located within 200nm of the vicinity of the metal line process hot spot pattern.
As shown in fig. 2B, the hot spot pattern of the metal line process after the coloring in the second dual pattern splitting is a sparse pattern.
Referring to the graphs corresponding to the mark 1 and the mark 2 in fig. 2C, it can be seen that the shortest metal line graph corresponding to the mark 1, that is, the vicinity of the metal line process hot spot graph is sparse, which is beneficial to adding the sub-resolution auxiliary graph 6 in the subsequent second OPC correction.
And thirdly, performing second OPC correction as shown in FIG. 2C, wherein the second OPC correction is used for performing OPC correction on the first layer of mask layout and the second layer of mask layout respectively to obtain a final mask layout.
In the second OPC correction of the third step, the OPC correction of the first-layer mask layout includes the following sub-steps:
and carrying out rule-based OPC correction on the first layer mask plate layout to obtain a first target layer, wherein the first target layer is shown as a mark 5.
And filling a sub-resolution auxiliary pattern 6 in the region, near the metal wire process hot spot pattern, of the first target layer, where the device auxiliary pattern is removed. The sub-resolution auxiliary pattern 6 can improve a photolithography process window.
And carrying out model-based OPC correction on the first target layer to obtain a first layer final mask plate layout corresponding to the first layer mask plate layout.
And step three, in the second OPC, performing OPC on the second layer of mask plate layout to obtain a second layer of final mask plate layout, wherein the final mask plate layout consists of the first layer of mask plate layout and the second layer of final mask plate layout. In actual photoetching, photoetching definition is carried out by respectively adopting the first layer mask plate layout and the second layer final mask plate layout.
According to the embodiment of the invention, aiming at the metal wire process hot spot graphs close to the auxiliary graph of the device, the first double graph splitting and the first OPC correction are carried out, the metal wire process hot spot graphs are screened out according to the first OPC correction result, then the second double graph splitting is carried out, the auxiliary graphs of the device close to the metal wire process hot spot graphs in the second double graph splitting are all colored into different colors, namely, the colors opposite to the colors of the metal wire process hot spot graphs, and the splitting is carried out according to the coloring, so that the metal wire process hot spot graphs and the adjacent auxiliary graphs of the device can be split into different layers of mask plates, namely, a first layer of mask plate layout and a second layer of mask plate layout, the areas close to the metal wire process hot spot graphs are sparse areas, and the sparsity increase near the metal wire process hot spot graphs can provide enough space for filling the sub-resolution auxiliary graphs 6, so that the photoetching process windows of the metal wire process graphs can be effectively increased, and the risk of short circuit or open circuit of the metal wire process hot spot graphs is reduced.
In addition, the method of the embodiment of the invention can locally modify the condition of double graph color distribution to carry out local coloring splitting and OPC correction on the basis of not increasing a large amount of operation time.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (10)
1. An OPC correction method for improving metal wire process hot spots is characterized by comprising the following steps:
firstly, carrying out first double pattern splitting and first OPC correction on an original mask plate layout, and screening out a metal wire process hot spot pattern close to a device auxiliary pattern;
checking coloring and splitting conditions of the metal wire process hot spot pattern and the nearby device auxiliary patterns in the first dual pattern splitting, and performing second dual pattern splitting, wherein in the second dual pattern splitting, the device auxiliary patterns nearby the metal wire process hot spot pattern are all colored into different colors opposite to the colors of the metal wire process hot spot pattern, the original mask plate layout is re-split according to coloring, and the second dual pattern splitting splits the metal wire process hot spot pattern onto a first layer of mask plate layout and splits the device auxiliary patterns nearby the metal wire process hot spot pattern onto a second layer of mask plate layout;
and thirdly, performing second OPC correction, wherein the second OPC correction is used for performing OPC correction on the first layer of mask plate layout and the second layer of mask plate layout respectively to obtain a final mask plate layout.
2. The OPC correction method for improving metal line process hot spots according to claim 1, wherein: in the first step, the metal wire process hot spot pattern comprises a metal wire pattern with short circuit or open circuit risks.
3. The OPC correction method for improving metal line process hot spots of claim 2, wherein: the metal line process hot spot pattern further includes the metal line pattern in which the device auxiliary patterns are regularly arranged in the vicinity.
4. The OPC correction method for improving metal line process hot spots according to claim 1, wherein: in the second dual pattern splitting, the coloring and splitting results of the metal wire process hot spot pattern are fixed as the coloring and splitting results of the first dual pattern splitting, only the coloring of the device auxiliary patterns near the metal wire process hot spot pattern is changed, and the device auxiliary patterns near the metal wire process hot spot pattern are all colored in different colors on the premise of not violating the design rules.
5. The method of claim 4 for improving OPC correction of metal line process hot spots, wherein: in the second dual pattern splitting, the coloring and splitting results of the layout patterns except the device auxiliary patterns, which are all colored to be different colors near the metal wire process hot spot patterns, are also fixed as the coloring and splitting results of the first dual pattern splitting.
6. The OPC correction method for improving metal line process hot spots according to claim 1 or 4, wherein: in the second step, the range of the device auxiliary patterns which are all colored into different colors and are positioned near the metal wire process hot spot patterns is within 200 nm.
7. The method of claim 4 for improving OPC correction of metal line process hot spots, wherein: and after coloring in the second dual pattern splitting, the metal wire process hot spot pattern is a sparse pattern.
8. The OPC correction method for improving metal line process hot spots according to claim 1 or 2, wherein: in the first step, the first dual graph splitting is performed by coloring and splitting in a uniform distribution mode.
9. The OPC correction method for improving metal line process hot spots according to claim 1, wherein: in the second OPC correction, the OPC correction on the first layer mask plate layout comprises the following sub-steps:
carrying out rule-based OPC correction on the first layer mask plate layout to obtain a first target layer;
filling sub-resolution auxiliary patterns in the areas, near the metal wire process hot spot patterns, of the first target layer, where the device auxiliary patterns are removed;
and carrying out model-based OPC on the first target layer to obtain a first layer final mask plate layout corresponding to the first layer mask plate layout.
10. The method of improving OPC correction of a metal line process hotspot of claim 9, wherein: and step three, in the second OPC, performing OPC on the second layer of mask plate layout to obtain a second layer of final mask plate layout, wherein the final mask plate layout consists of the first layer of mask plate layout and the second layer of final mask plate layout.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101241517A (en) * | 2007-02-06 | 2008-08-13 | 台湾积体电路制造股份有限公司 | Method, device and system for a pattern layout split |
| CN102841509A (en) * | 2011-04-04 | 2012-12-26 | Asml荷兰有限公司 | Integration of lithography apparatus and mask optimization process with multiple patterning process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8327301B2 (en) * | 2009-02-03 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Routing method for double patterning design |
| US10670973B2 (en) * | 2015-05-20 | 2020-06-02 | Asml Netherlands B.V. | Coloring aware optimization |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101241517A (en) * | 2007-02-06 | 2008-08-13 | 台湾积体电路制造股份有限公司 | Method, device and system for a pattern layout split |
| CN102841509A (en) * | 2011-04-04 | 2012-12-26 | Asml荷兰有限公司 | Integration of lithography apparatus and mask optimization process with multiple patterning process |
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