CN113113494A - GAA transistor structure, preparation method thereof and electronic equipment - Google Patents

GAA transistor structure, preparation method thereof and electronic equipment Download PDF

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Publication number
CN113113494A
CN113113494A CN202110381182.1A CN202110381182A CN113113494A CN 113113494 A CN113113494 A CN 113113494A CN 202110381182 A CN202110381182 A CN 202110381182A CN 113113494 A CN113113494 A CN 113113494A
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nmos
layer
pmos
fin
device units
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张卫
徐敏
陈鲲
杨静雯
王晨
徐赛生
吴春蕾
尹睿
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The invention provides a GAA transistor structure, a preparation method thereof and electronic equipment, wherein the structure comprises the following components: a transistor substrate, a plurality of device units; the device unit comprises a stacking layer arranged on the transistor substrate and an outer metal gate crossing the outer side of the stacking layer, wherein the stacking layer comprises a plurality of nano layers and a plurality of metal gate layers which are alternately stacked; the plurality of device units comprise PMOS device units and NMOS device units, the PMOS device units are arranged in a PMOS area of the substrate, and the NMOS device units are arranged in an NMOS area of the substrate; along the target direction, the distribution quantity of the PMOS device units on the PMOS area is more than that of the NMOS device units on the NMOS area, the target direction is perpendicular to the channel direction of the nano layer, the total area of the surfaces for carrying current in the nano layer of the PMOS device units is larger than that of the surfaces for carrying current in the nano layer of the NMOS device units, and the performance of the GAA transistor structure is improved.

Description

GAA transistor structure, preparation method thereof and electronic equipment
Technical Field
The invention relates to the technical field of semiconductors, in particular to a GAA transistor structure, a preparation method of the GAA transistor structure and electronic equipment.
Background
In recent years, silicon-based chip processes have been developed according to moore's law, and device structures have been developed from planar transistors to fin-type transistors and to gate-all-around transistors, and accordingly, a series of innovative process technologies have been invented and applied. In a conventional planar transistor, the hole mobility is about half of the electron mobility on the Si (100) plane, and in order to match the PMOS and NMOS currents to form a CMOS, a large area PMOS has to be designed: approximately 2 times that of NMOS. In order to reduce the size (Footprint) of PMOS, the Strained-Si technology is invented, and the mobility of holes on the Si surface is increased by introducing compressive stress on the PMOS channel, so that the PMOS current matching NMOS is improved.
With the continuous reduction of the size of transistor devices, the channel of the transistor is continuously shortened, the small-size effect is more and more obvious, and the fin type transistor is generated. The grid electrode of the fin type transistor (FinFET) adopts a fork-shaped 3D framework similar to a fish fin, and the channel is wrapped from three sides, so that the channel current control is enhanced, and the leakage current is reduced. In FinFET technology, most of the carriers are transported on the Si (110) sidewalls, where the mobility of the electrons is instead smaller than the mobility of the holes (as shown in the table below). Therefore, after stress tensile stress is introduced in the FinFET technology, the currents of the NMOS region and the PMOS region under the same Footprint can be basically balanced.
With the coming of 3nm nodes, higher requirements are provided for the gate control capability, size, power consumption and the like of the transistor, and compared with a FinFET structure, a gate-all-around transistor (GAA) can realize more excellent transistor performance by wrapping four sides of a channel (a plurality of nano sheets/nano wires) by a gate, and can better meet the technical requirements of 3nm nodes and even below sizes. In the ring gate nanosheet (or nanowire) channel, carriers are transported along the upper and lower surfaces of Si (which may be, for example, the upper and lower surfaces 10311 of the nanolayer in fig. 1) and the sidewall of Si (which may be, for example, the side surface 10312 of the nanolayer in fig. 1), when the hole mobility on the sidewall of Si is about 1/3 of the electron mobility, the mobility mismatch is severe.
Disclosure of Invention
The invention provides a GAA transistor structure, a preparation method thereof and electronic equipment, which aim to solve the problem of unbalanced performance of a PMOS (P-channel metal oxide semiconductor) area and an NMOS (N-channel metal oxide semiconductor) area.
According to a first aspect of the present invention, there is provided a GAA transistor structure comprising: a transistor substrate, a plurality of device units; the device unit comprises a stacking layer arranged on the transistor substrate and an outer metal gate crossing the outer side of the stacking layer, wherein the stacking layer comprises a plurality of nano layers and a plurality of metal gate layers which are alternately stacked;
the plurality of device units comprise PMOS device units and NMOS device units, the PMOS device units are arranged in a PMOS area of the transistor substrate, and the NMOS device units are arranged in an NMOS area of the transistor substrate;
along a target direction, the distribution quantity of the PMOS device units on the PMOS region is more than that of the NMOS device units on the NMOS region, the target direction is perpendicular to the channel direction of the nano layer, and the total area of the surfaces for carrying current in the nano layer of the PMOS device units is larger than that of the surfaces for carrying current in the nano layer of the NMOS device units.
Optionally, the widths of the nanolayer and the metal gate layer in the PMOS device unit are smaller than the widths of the nanolayer and the metal gate layer in the NMOS device unit, where the width refers to a dimension along the target direction.
Optionally, the device unit further includes a source and a drain, and the source and the drain are distributed on two sides of the corresponding stacked layer along the channel direction and connected to the nano layer therein.
Optionally, the widths of the PMOS device units are the same, and the widths of the NMOS device units are the same, where the widths refer to the dimension along the target direction.
Optionally, the thickness of the nanolayer is in the interval range of 3nm to 30 nm; the thickness of the metal gate layer is in the range of 3nm to 30 nm.
According to a second aspect of the present invention, there is provided a method for preparing a GAA transistor structure according to the first aspect of the present invention and its optional embodiments, comprising:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a channel layer and a sacrificial layer which are alternately laminated;
etching the epitaxial layer and the substrate to form a transistor substrate, and an NMOS fin part and a PMOS fin part which are arranged on the transistor substrate, wherein the NMOS fin part is positioned in an NMOS region of the transistor substrate, the PMOS fin part is positioned in a PMOS region of the transistor substrate, the distribution quantity of the PMOS fin parts on the PMOS region is more than that of the NMOS fin parts on the NMOS region along a target direction, and the target direction is perpendicular to the channel direction of the channel layer; the total area of the side face, parallel to the channel direction, in the channel layer of the PMOS fin part is larger than the total area of the side face, parallel to the channel direction, in the channel layer of the NMOS fin part;
forming the GAA transistor structure based on the transistor substrate, the PMOS fin portion and the NMOS fin portion, wherein the nano layer is formed on the channel layer.
Optionally, the epitaxial layer and the substrate are etched based on multiple exposure of a multi-layer mask, and widths of the mask for forming the NMOS fin portion by etching and the mask for forming the PMOS fin portion by etching are different.
Optionally, forming the GAA transistor based on the transistor substrate, the PMOS fin and the NMOS fin includes:
forming a pseudo gate stack spanning the outer sides of the PMOS fin portion and the NMOS fin portion;
etching the PMOS fin part, the NMOS fin part and the pseudo gate stack at the outer side of the NMOS fin part to form a stack structure corresponding to each device unit, wherein the stack structures of different device units are mutually spaced; the stacked structure comprises nano layers and sacrificial layers which are alternately stacked;
forming a source electrode and a drain electrode on two sides of the stacking structure along the channel direction;
removing the dummy gate stack and the sacrificial layer;
and filling metal gates between the stacked nano layers and outside the stacked structure to form the stacked layer and the outer metal gate, thereby obtaining the GAA transistor structure.
Optionally, after forming the dummy gate stack crossing the outer sides of the PMOS fin and the NMOS fin, the method further includes:
forming a dielectric layer on the outer side of the dummy gate stack;
etching the PMOS fin part, the NMOS fin part and the pseudo gate stack on the outer side of the NMOS fin part to form a stack structure corresponding to each device unit, and the method specifically comprises the following steps:
and etching the PMOS fin part, the NMOS fin part, the pseudo gate stack and the dielectric layer at the outer side of the NMOS fin part to form a stack structure corresponding to each device unit.
Optionally, after forming the transistor substrate and the NMOS fin portion and the PMOS fin portion disposed on the transistor substrate, the method further includes:
forming stress to the channel layer in the NMOS fin and/or the PMOS fin.
According to a third aspect of the present invention there is provided an electronic device comprising a GAA transistor structure or a device formed on the basis of said transistor structure as described in the first aspect of the present invention and its alternatives.
According to the GAA transistor structure, the preparation method thereof and the electronic device, the PMOS device units and the NMOS device units with different numbers are adopted along the target direction, the total area of the surfaces for carrying current in the nano layers of the PMOS device units is larger than that of the surfaces for carrying current in the nano layers of the NMOS device units, the mobility matching of the PMOS device units and the NMOS device units is realized, the balance of the performances of a PMOS area and an NMOS area is further ensured, and the performance of the GAA transistor structure is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a GAA transistor structure along the channel direction in accordance with one embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of A-A' in an embodiment of the present invention;
FIG. 3 is a first schematic flow chart of a method for fabricating a GAA transistor structure according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure for forming an epitaxial region in an embodiment of the invention;
FIG. 5 is a schematic diagram of a mask formation configuration in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure for forming a channel region according to an embodiment of the present invention;
FIG. 7 is a first flowchart illustrating the step S303 according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a structure for forming a device cell in an embodiment of the invention;
FIG. 9 is a schematic structural diagram illustrating the structure of the dummy gate stack after the sacrificial layer and the dummy gate stack are removed according to an embodiment of the present invention;
FIG. 10 is a second flowchart illustrating the step S303 according to an embodiment of the present invention;
FIG. 11 is a second schematic flow chart illustrating a method for fabricating a GAA transistor structure according to an embodiment of the present invention;
FIG. 12 is a first diagram illustrating a portion of a fin structure formed according to an embodiment of the present invention;
FIG. 13 is a second schematic diagram illustrating a partial structure of a fin formed in accordance with an embodiment of the present invention;
FIG. 14 is a schematic diagram of a portion of a fin structure in an embodiment of the invention;
fig. 15 is a fourth schematic view illustrating a partial structure of a fin formed according to an embodiment of the present invention.
Description of reference numerals:
101-a transistor substrate; 101n-NMOS region; 101p-PMOS region; 102n-NMOS device cells; 103 n-stacked layers; 1031 n-nanolayer; 1032 n-metal gate layer; 104 n-outer metal gate;
102p-PMOS device cells; 103 p-stacked layers; 1031 p-nanolayer; 1032 p-metal gate layer; 104 p-outer metal gate; 105-a source electrode; 106-drain electrode; 10311-upper and lower surfaces of the nanolayer; 10312-nano layer side surface;
201-a substrate; 201n-NMOS region; a 201p-PMOS region; 202-an epitaxial region; 2021-sacrificial layer; 2022-a channel layer; 203-a mask; 202 n-stacked structure; 202 p-stacked structure; 2021 n-sacrificial layer; 2022 n-nanolayer; 2021 p-sacrificial layer; 2022 p-nanolayer;
401-a first oxide layer; 402-a first mask layer; 403-a second oxide layer; 404-an amorphous silicon layer; 405-a second mask layer; 406-an anti-reflective coating; 407-an isolation layer; 408-mask sidewalls.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 1, a GAA transistor structure includes: a transistor substrate 101, a plurality of device units 102; the device units (e.g., the PMOS device unit 102p and the NMOS device unit 102n shown in fig. 1) include stacked layers (e.g., the stacked layer 103n of the NMOS device unit 102n and the stacked layer 103p of the PMOS device unit 102p shown in fig. 1) provided on the transistor substrate and outer metal gates (e.g., the outer metal gate 104n and the outer metal gate 104p shown in fig. 1) crossing the outside of the stacked layers, and the stacked layers include a plurality of nano-layers (e.g., the nano-layer 1031n of the NMOS device unit and the nano-layer 1031p of the PMOS device unit shown in fig. 1) and a plurality of metal gate layers (e.g., the metal gate layer 1032n of the NMOS device unit and the metal gate layer 1032p of the PMOS device unit shown in fig. 1) stacked alternately; the nano layer can be a nano wire, a nano sheet or other shapes.
The outer metal gate of each device unit and the metal gate layer form a metal gate corresponding to the device unit.
The plurality of device units comprise PMOS device units 102p and NMOS device units 102n, the PMOS device units 102p are arranged in a PMOS area 101p of the transistor substrate 101, and the NMOS device units 102n are arranged in an NMOS area 101n of the transistor substrate 101;
along a target direction, the distribution number of the PMOS device units 102p on the PMOS region 101p is greater than the distribution number of the NMOS device units 102n on the NMOS region 101n, the target direction is perpendicular to the channel direction of the nanolayer, and the total area of the surfaces for carrying current in the nanolayer of the PMOS device units 102p is greater than the total area of the surfaces for carrying current in the nanolayer of the NMOS device units 102 n.
The nano layer may be Si, the transistor substrate may be Si, or Silicon On Insulator (SOI for short) On an insulating substrate.
The NMOS region 101n and the PMOS region 101p metal gates (including the outer metal gate and the metal gate layer) may be made of different metal gate materials according to the types of ions doped in the corresponding regions.
In the same device unit, the thicknesses of the multiple nanolayers can be the same, for example, the thickness of each nanolayer is 3nm, and can also be different; in the same device unit, the thicknesses of the multiple metal gate layers may be the same, for example, the thicknesses of the metal gate layers are all 5nm, and may also be different; in the same device unit, the thicknesses of the nano layer and the metal gate layer may be the same, for example, in the same device unit, the thicknesses of the nano layers and the thicknesses of the metal gate layers are both 3nm, and the thicknesses of the nano layers and the metal gate layers may be different, for example, in the same device unit, the thicknesses of the nano layers are 3nm, and the thicknesses of the metal gate layers are 5 nm.
The widths of the PMOS device units can be the same or different along the target direction; the widths of the plurality of NMOS device units can be the same or different; the widths of the nano-layer 1031p and the metal gate layer 1032p in the PMOS device unit may be the same as the widths of the nano-layer 1031n and the metal gate layer 1032n in the NMOS device unit, or may be different from the widths of the nano-layer 1031n and the metal gate layer 1032n in the NMOS device unit;
it can be seen that, in the target direction, no matter whether the widths of the PMOS device units are the same or not, and whether the widths of the NMOS device units are the same or not, and whether the widths of the nanolayer 1031p and the metal gate layer 1032p in the PMOS device units are the same or not, and whether the widths of the nanolayer 1031n and the metal gate layer 1032n in the NMOS device units are the same or not, as long as the number of device units is different, and the total area of the surfaces for current carrying in the nanolayers of the PMOS device unit 102p is larger than the total area of the surfaces for current carrying in the nanolayers of the NMOS device unit 102n, the balance of the performances of the PMOS device unit 102p and the NMOS device unit 102n is realized, and the balance is included.
In one example, a Shallow Trench Isolation (STI) is included between any two adjacent device units to isolate the adjacent device units.
The number of layers of the stacked layers of the PMOS device unit and the NMOS device unit can be different or the same, and corresponding design can be made according to requirements.
By employing different numbers of PMOS device units 102p and NMOS device units 102n along the target direction and making the total area of the surfaces for current carrying in the nanolayers of the PMOS device units (which may be, for example, the sum of the areas of the upper and lower surfaces 10311 of the nanolayers and the side surface 10322 of the nanolayers in fig. 1) larger than the total area of the surfaces for current carrying in the nanolayers of the NMOS device units, a match of the mobilities of the PMOS device units and the NMOS device units is achieved, thereby ensuring a balance of the performance of the PMOS region and the NMOS region.
In one embodiment, the widths of the nano-layer 1031p and the metal gate layer 1032p in the PMOS device unit are smaller than the widths of the nano-layer 1031n and the metal gate layer 1032n in the NMOS device unit, wherein the widths refer to the dimension along the target direction.
Referring to fig. 2, in one embodiment, the device unit further includes a source 105 and a drain 106, and the source 105 and the drain 106 are distributed on two sides of the corresponding stacked layer along the channel direction and connected to the nano-layer therein.
In one example, isolation layers are disposed between the source and the drain and the outer metal gate and the metal gate layer, respectively, to isolate the source and the drain from the outer metal gate and the metal gate layer, respectively, so as to prevent the gate, the source and the drain of the finally formed GAA transistor structure from being shorted.
In one embodiment, the PMOS device cells 102p have the same width, and the NMOS device cells 102n have the same width, where the width refers to the dimension along the target direction.
In one embodiment, the nanolayer has a thickness in the range of from 3nm to 30 nm; the thickness of the metal gate layer is in the range of 3nm to 30 nm.
Referring to fig. 3 to 6, a method for fabricating a GAA transistor structure includes:
s301: forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a channel layer and a sacrificial layer which are alternately laminated;
the substrate 201 may be Si or SOI, the channel layer 2022 may be Si, the sacrificial layer 2021 may be SiGe, the thickness of the channel layer 2022 is 3nm to 30nm, and the thickness of the sacrificial layer 2021 is 3nm to 30 nm; the thickness of each channel layer may be the same, for example, the thickness of each channel layer is 3nm, or may be different; the thickness of each sacrificial layer can be the same, for example, the thickness of each sacrificial layer is 5nm, and can also be different; the thicknesses of the sacrificial layer and the channel layer may be the same, for example, the thickness of each channel layer and the thickness of each sacrificial layer are both 3nm, or may be different, for example, the thickness of each channel layer is 3nm and the thickness of each sacrificial layer is 5 nm.
S302: etching the epitaxial layer and the substrate to form a transistor base and an NMOS fin part and a PMOS fin part which are arranged on the transistor base,
the NMOS fins 202n are located in an NMOS region 2021n of the transistor substrate, the PMOS fins 202p are located in a PMOS region 2021p of the transistor substrate 101, and along a target direction, the number of the PMOS fins 202p in the PMOS region is greater than the number of the NMOS fins 202n in the NMOS region, and the target direction is perpendicular to a channel direction of the channel layer; the total area of the side surfaces parallel to the channel direction in the channel layer of the PMOS fin portion 202p is larger than the total area of the side surfaces parallel to the channel direction in the channel layer of the NMOS fin portion 202 n;
in step S302, different etching processes may be adopted in the specific process of etching the NMOS fin portion and the PMOS fin portion according to different requirements, and no matter what etching process is adopted to obtain the NMOS fin portion and the PMOS fin portion, as long as the number of the PMOS fin portions 202p in the PMOS region is greater than the number of the NMOS fin portions 202n in the NMOS region along the target direction, the total area of the side surfaces parallel to the channel direction in the channel layer of the PMOS fin portion 202p is greater than the total area of the side surfaces parallel to the channel direction in the channel layer of the NMOS fin portion 202n, and both are included in the protection scope of the present invention.
S303: forming the GAA transistor structure based on the transistor substrate, the PMOS fin portion and the NMOS fin portion, wherein the nano layer is formed on the channel layer.
In step S303, a gate electrode including a source electrode, a drain electrode, an outer metal gate, and a metal gate layer, an isolation layer between the metal gate layer and the source electrode and the drain electrode, and an etching sacrificial layer to release a channel may be formed, and the process of forming the gate electrode may be to form a gate electrode by forming a dummy gate electrode (i.e., a gate electrode having no electrical function), or may be to form a gate electrode directly; the materials of the source electrode, the drain electrode and the grid electrode can adopt different doping according to different transistor substrates.
In one embodiment, referring to fig. 6, the widths of the mask for forming the NMOS fin portion by etching and the mask for forming the PMOS fin portion by etching are different.
In the above embodiment, along the target direction, the width of the NMOS fin pattern is greater than the width of the PMOS fin pattern, so that in the GAA transistor structure, along the target direction, the width of the nanolayer of the NMOS device unit is greater than the width of the nanolayer of the PMOS device unit, and further, the total area of the surface for carrying current in the nanolayer of the PMOS device unit is greater than the total area of the surface for carrying current in the nanolayer of the NMOS device unit, so as to achieve the balance between the performance of the NMOS device unit and the performance of the PMOS device unit.
Referring to fig. 7 and 8, in one embodiment, step S303 specifically includes:
s3031: forming a dummy gate stack spanning the PMOS and NMOS fin outsides,
a consistent process environment (e.g., consistent topography) of the surface of the GAA transistor structure is provided by the dummy gate stack 204, i.e., the gate stack without electrical functionality, and further, in a subsequent manufacturing process, the dummy gate stack can be replaced with a gate with electrical functionality;
s3032: etching the PMOS fin part, the NMOS fin part and the pseudo gate stack at the outer side of the NMOS fin part to form a stack structure corresponding to each device unit,
the stacked structures of different device units are mutually spaced; the stacked structure includes nano-layers 2022 and the sacrificial layers 2021 stacked alternately, and a cross section of the formed structure along a channel direction can be as shown in fig. 8;
s3033: forming a source electrode and a drain electrode on two sides of the stacking structure along the channel direction;
in step S3033, the source or the gate may be formed by, for example, etching a portion of the sacrificial layer in fig. 8 toward the central axis of the corresponding stacked structure, and the etched space may be used to grow an isolation layer to isolate the finally formed gate from the source and the drain; for example, a portion of the nanolayer 2022 in the stacked structure in fig. 8 is epitaxially grown in a direction away from the central axis of the stacked structure, and then the source and the drain are further epitaxially grown, and the process steps for forming the source and the drain may select an appropriate process according to requirements, so that the GAA transistor structure achieves better performance.
S3034: removing the dummy gate stack and the sacrificial layer;
s3035: and filling metal gates between the stacked nano layers and outside the stacked structure to form the stacked layer and the outer metal gate, thereby obtaining the GAA transistor structure.
In one example, the periphery of the nanolayers of the stack may form a dielectric layer to isolate the metal gate layer, the outer metal gate and the nanolayers.
Referring to fig. 10, in an embodiment, after the step S3031, the method further includes:
s3036: forming a dielectric layer on the outer side of the dummy gate stack;
in a further embodiment, after step S3033, the dielectric layer formed in step S3036 may be filled and planarized.
Step S3032 specifically includes:
s30321: and etching the PMOS fin part, the NMOS fin part, the pseudo gate stack and the dielectric layer at the outer side of the NMOS fin part to form a stack structure corresponding to each device unit.
Referring to fig. 11, in an embodiment, after step S302, the method further includes:
s304: forming stress to the channel layer in the NMOS fin and/or the PMOS fin.
In step S304, stress is introduced into the channel region to increase the mobility of holes in the device cell, so that the PMOS device cell current matches the NMOS device cell.
In one example, a compressive stress may be introduced only in a channel region between PMOS device units, increasing mobility of holes on a nano layer in the PMOS device units, and increasing current of the PMOS device units;
in another example, different stresses may be introduced between the PMOS device units and the NMOS device units, respectively, so that the PMOS device units are current matched to the NMOS device units;
in yet another example, tensile stress may be introduced only in the channel region between NMOS device cells, reducing the mobility of holes on the nanolayers in the NMOS device cells, such that PMOS device cell current matches NMOS device cell current.
An alternative to step S302 will be described below with reference to fig. 12 to 15, and any scheme capable of implementing fin etching in the field may be used as an alternative to the embodiment of the present invention, and is not limited to the following example.
The epitaxial layer and the substrate are etched based on multiple exposure of a multi-layer mask, and the widths of the mask for forming the NMOS fin parts and the mask for forming the PMOS fin parts through etching are different.
Referring to fig. 12 to fig. 15, in an example, the step S302 specifically includes:
in fig. 12, the substrate 201 and the epitaxial region 202 composed of the channel layer 2022 and the sacrificial layer 2021 are used as the bottom structure of the etched fin, and SiO is sequentially formed on the bottom structure2A first oxide layer 401, a first mask layer 402 made of SiN, and SiO2A second oxide layer 403 formed, an amorphous silicon layer 404 formed of a-Si, a second mask layer 405 formed of SiN, and an anti-reflective coating 406 formed of soc (spin On carbon), resulting in structure a in fig. 12;
patterning the second mask layer 405 in the obtained structure A to obtain a structure B, and removing the anti-reflection coating 406 in the structure B to obtain a structure C;
etching the structure C, forming an anti-reflection coating 406 formed by SoC again to obtain a structure D in fig. 13, performing patterning processing on the first mask layer 402 in the obtained structure D, performing etching based on the patterned structure to obtain a structure E, and removing the anti-reflection coating 406 in the structure E to obtain a structure F;
forming SiO between adjacent fin portions of structure F2The isolation layer 407 is formed, and the anti-reflective coating 406 formed on SoC is formed again to obtain the structure G in fig. 14, the first mask layer 402 in the obtained structure G is patterned and etched based on the patterned structure to obtain the structure H, the anti-reflective coating 406 in the structure H is removed, and the obtained structure is filled with SiO2Realizing flattening to obtain a structure I;
forming a mask sidewall 408 made of SiN on the surface of the fin portion of the structure I, forming an anti-reflective coating 406 made of SoC again to obtain a structure J in fig. 15, performing patterning processing on the mask sidewall 408 in the structure J, performing etching based on the patterned structure to obtain a structure K, etching a part of the mask sidewall 408 on the surface of the anti-reflective coating 406 in the structure K to obtain a structure L, and removing the anti-reflective coating 406 in the structure L to obtain a structure M.
It can be seen that the mask 203 shown in fig. 6 is only schematically shown, and can be understood as a single layer mask when multiple exposures are not employed, and can also be understood as: it embodies the desired effect of forming mask layers, mask sidewalls, patterned mask layers, and mask sidewalls multiple times during multiple exposures, and further, structure M in fig. 15 can be considered to correspond to the structure in fig. 6, and first mask layer 402 and mask sidewalls 408 can be considered to correspond to mask 203 in fig. 6.
Meanwhile, the first mask layer, the second mask layer and the mask side wall can be understood as the mask.
An embodiment of the present invention further provides an electronic device, which includes the GAA transistor structure or the device formed based on the GAA transistor structure.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (11)

1. A GAA transistor structure, comprising: a transistor substrate, a plurality of device units; the device unit comprises a stacking layer arranged on the transistor substrate and an outer metal gate crossing the outer side of the stacking layer, wherein the stacking layer comprises a plurality of nano layers and a plurality of metal gate layers which are alternately stacked;
the plurality of device units comprise PMOS device units and NMOS device units, the PMOS device units are arranged in a PMOS area of the transistor substrate, and the NMOS device units are arranged in an NMOS area of the transistor substrate;
along a target direction, the distribution quantity of the PMOS device units on the PMOS region is more than that of the NMOS device units on the NMOS region, the target direction is perpendicular to the channel direction of the nano layer, and the total area of the surfaces for carrying current in the nano layer of the PMOS device units is larger than that of the surfaces for carrying current in the nano layer of the NMOS device units.
2. The GAA transistor structure of claim 1, wherein the width of the nanolayer and metal gate layer in the PMOS device cell is smaller than the width of the nanolayer and metal gate layer in the NMOS device cell, wherein the width is along the target direction.
3. The GAA transistor structure of claim 1, wherein the device unit further comprises a source and a drain, the source and the drain being distributed on two sides of the corresponding stacked layers along the channel direction and connected to the nano-layer therein.
4. The GAA transistor structure of claim 1, wherein the PMOS device cells have the same width and the NMOS device cells have the same width, wherein the width is the dimension along the target direction.
5. The GAA transistor structure of any of claims 1 to 4, wherein the nanolayer has a thickness in the interval range of 3nm to 30 nm; the thickness of the metal gate layer is in the range of 3nm to 30 nm.
6. A method of making the GAA transistor structure of any of claims 1 to 5, comprising:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a channel layer and a sacrificial layer which are alternately laminated;
etching the epitaxial layer and the substrate to form a transistor substrate, and an NMOS fin part and a PMOS fin part which are arranged on the transistor substrate, wherein the NMOS fin part is positioned in an NMOS region of the transistor substrate, the PMOS fin part is positioned in a PMOS region of the transistor substrate, the distribution quantity of the PMOS fin parts on the PMOS region is more than that of the NMOS fin parts on the NMOS region along a target direction, and the target direction is perpendicular to the channel direction of the channel layer; the total area of the side face, parallel to the channel direction, in the channel layer of the PMOS fin part is larger than the total area of the side face, parallel to the channel direction, in the channel layer of the NMOS fin part;
forming the GAA transistor structure based on the transistor substrate, the PMOS fin portion and the NMOS fin portion, wherein the nano layer is formed on the channel layer.
7. The method of claim 6, wherein the epitaxial layer and the substrate are etched based on multiple exposures of a multi-layer mask, and wherein the widths of the mask used to etch the NMOS fin and the mask used to etch the PMOS fin are different.
8. The method of claim 6, wherein forming the GAA transistor based on the transistor substrate, the PMOS fin, and the NMOS fin comprises:
forming a pseudo gate stack spanning the outer sides of the PMOS fin portion and the NMOS fin portion;
etching the PMOS fin part, the NMOS fin part and the pseudo gate stack at the outer side of the NMOS fin part to form a stack structure corresponding to each device unit, wherein the stack structures of different device units are mutually spaced; the stacked structure comprises nano layers and sacrificial layers which are alternately stacked;
forming a source electrode and a drain electrode on two sides of the stacking structure along the channel direction;
removing the dummy gate stack and the sacrificial layer;
and filling metal gates between the stacked nano layers and outside the stacked structure to form the stacked layer and the outer metal gate, so as to obtain the GAA transistor structure.
9. The method of claim 8, further comprising, after forming a dummy gate stack that spans outside of the PMOS and NMOS fins:
forming a dielectric layer on the outer side of the dummy gate stack;
etching the PMOS fin part, the NMOS fin part and the pseudo gate stack on the outer side of the NMOS fin part to form a stack structure corresponding to each device unit, and the method specifically comprises the following steps:
and etching the PMOS fin part, the NMOS fin part, the pseudo gate stack and the dielectric layer at the outer side of the NMOS fin part to form a stack structure corresponding to each device unit.
10. The method of any of claims 6 to 9, further comprising, after forming the transistor substrate and the NMOS and PMOS fins disposed on the transistor substrate:
forming stress to the channel layer in the NMOS fin and/or the PMOS fin.
11. An electronic device comprising the GAA transistor structure of any one of claims 1 to 5 or a device formed based on the transistor structure.
CN202110381182.1A 2021-04-09 2021-04-09 GAA transistor structure, preparation method thereof and electronic equipment Pending CN113113494A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024208144A1 (en) * 2023-04-04 2024-10-10 中国科学院微电子研究所 Hybrid integrated sram storage unit structure and manufacturing method therefor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150370948A1 (en) * 2014-06-23 2015-12-24 Synopsys, Inc. Memory cells having transistors with different numbers of nanowires or 2d material strips
CN110970431A (en) * 2018-09-28 2020-04-07 芯恩（青岛）集成电路有限公司 Complementary inverter structure of inversion mode fully-enclosed gate nanosheet and manufacturing method thereof
CN112563209A (en) * 2019-09-26 2021-03-26 台湾积体电路制造股份有限公司 Method for forming semiconductor device
US20210098625A1 (en) * 2019-09-27 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150370948A1 (en) * 2014-06-23 2015-12-24 Synopsys, Inc. Memory cells having transistors with different numbers of nanowires or 2d material strips
CN110970431A (en) * 2018-09-28 2020-04-07 芯恩（青岛）集成电路有限公司 Complementary inverter structure of inversion mode fully-enclosed gate nanosheet and manufacturing method thereof
CN112563209A (en) * 2019-09-26 2021-03-26 台湾积体电路制造股份有限公司 Method for forming semiconductor device
US20210098625A1 (en) * 2019-09-27 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024208144A1 (en) * 2023-04-04 2024-10-10 中国科学院微电子研究所 Hybrid integrated sram storage unit structure and manufacturing method therefor

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