CN113113064A - SRAM memory cell circuit - Google Patents

SRAM memory cell circuit Download PDF

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Publication number
CN113113064A
CN113113064A CN202110518201.0A CN202110518201A CN113113064A CN 113113064 A CN113113064 A CN 113113064A CN 202110518201 A CN202110518201 A CN 202110518201A CN 113113064 A CN113113064 A CN 113113064A
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tube
nmos
pmos
transistor
electrode
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CN113113064B (en
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何卫锋
张灏
孙亚男
毛志刚
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Shanghai Jiaotong University
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Shanghai Jiaotong University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses an SRAM memory cell circuit, which comprises a first inverter and a second inverter, wherein the first inverter and the second inverter form a negative feedback circuit to reduce leakage current. Compared with the traditional phase inverter, the first phase inverter formed by the first PMOS tube, the third PMOS tube, the first NMOS tube and the third NMOS tube in the circuit can place a leakage path in a deep cut-off state on the premise of ensuring the phase inversion function, so that the leakage current is reduced by two to three orders of magnitude. Similarly, the second inverter formed by the second PMOS tube, the fourth PMOS tube, the second NMOS tube and the fourth NMOS tube has lower static power consumption compared with the traditional inverter. The first inverter and the second inverter form a feedback structure, so that opposite data can be stored, and the static power consumption of the whole storage unit is remarkably reduced.

Description

SRAM memory cell circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an SRAM memory cell circuit.
Background
The main unit of the current SRAM is a 6T structure, and referring to fig. 1, fig. 1 is a schematic circuit structure of a conventional 6T SRAM memory cell. In order to operate the 6T cell at ultra-low voltage, designers tend to increase the transistor size, but the adjusted 6T cell causes greater static power consumption, thereby significantly increasing the power consumption of the overall SRAM memory cell array. The ultra-low voltage circuit is a circuit with a power supply voltage near the threshold voltage of a transistor, and is widely applied to an SRAM by virtue of ultra-low power consumption on the premise of meeting application requirements. However, as the power supply voltage is reduced, the static power consumption of the SRAM memory cell array becomes a major component of the power consumption of the whole system on chip due to the characteristics of the SRAM that has a large memory size and the memory cells have a low activation probability.
Therefore, it is desirable to provide an SRAM memory cell that can effectively reduce static power consumption.
Disclosure of Invention
The invention aims to provide an SRAM memory cell circuit, which is used for solving the problem that the static power consumption of an SRAM memory cell array in the prior art is large.
In order to solve the above technical problem, the present invention provides an SRAM memory cell circuit, including:
a first phase inverter formed by a first PMOS tube, a third PMOS tube, a first NMOS tube and a third NMOS tube;
a second inverter consisting of a second PMOS tube, a fourth PMOS tube, a second NMOS tube and a fourth NMOS tube;
the first inverter and the second inverter form a negative feedback circuit to reduce the leakage current of the SRAM memory cell circuit.
Optionally, the system further comprises a fifth PMOS transistor forming a first pull-down network bypass and a sixth PMOS transistor forming a second pull-down network bypass;
the first pull-down network bypass is connected with the first inverter;
the second pull-down network bypass is connected with the second inverter.
Optionally, the transistor further comprises a fifth NMOS transistor and a sixth NMOS transistor;
the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are connected with a power supply voltage, the drain electrode of the third NMOS tube is connected with the source electrode of the first PMOS tube, the drain electrode of the fifth NMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube, the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the third PMOS tube and the drain electrode of the sixth NMOS tube, and the source electrode of the first NMOS tube is connected with the drain electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube;
the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with ground voltage, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth PMOS tube and the drain electrode of the sixth PMOS tube;
the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are connected with a word line, the source electrode of the fifth NMOS tube is connected with a bit line, the source electrode of the sixth NMOS tube is not connected with the bit line, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are used as enabling ends.
Optionally, the body terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage, and the body terminals of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all connected to a ground voltage.
Optionally, the SRAM memory cell circuit, while holding data: the enable end is at a high level, and the voltage value of the enable end is higher than the power supply voltage;
the SRAM memory cell circuit is used for reading and writing data: the enable terminal is at a low level, and the voltage value of the enable terminal is lower than the ground voltage.
Optionally, the method further comprises:
a first bypass formed by a fifth NMOS tube and a fifth PMOS tube;
a second bypass formed by a sixth NMOS tube and a sixth PMOS tube;
the first bypass is connected to the first inverter and the second bypass is connected to the second inverter.
Optionally, the transistor further comprises a seventh NMOS transistor and an eighth NMOS transistor;
the source electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor, the source electrode of the fifth NMOS transistor and the source electrode of the sixth NMOS transistor are connected with a power supply voltage, the drain electrode of the third NMOS tube and the drain electrode of the fifth NMOS tube are connected with the source electrode of the first PMOS tube, the drain electrode of the seventh NMOS transistor is connected with the grid electrode of the first PMOS transistor, the grid electrode of the first NMOS transistor, the grid electrode of the fourth PMOS transistor, the grid electrode of the fourth NMOS transistor, the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the third PMOS tube and the drain electrode of the eighth NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube;
the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with ground voltage, the drain electrode of the fourth NMOS tube and the drain electrode of the sixth NMOS tube are connected with the source electrode of the second PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth PMOS tube and the drain electrode of the sixth PMOS tube;
the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube are connected with a word line, the source electrode of the seventh NMOS tube is connected with a bit line, the source electrode of the eighth NMOS tube is not connected with the bit line, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are used as enabling ends, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are used as enabling non-ends.
Optionally, body ends of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage;
the body ends of the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are all connected with ground voltage.
Optionally, the SRAM memory cell circuit, while holding data: the enable terminal is at a low level, the voltage value of the enable terminal is lower than the ground voltage, the enable non-terminal is at a high level, and the voltage value of the enable non-terminal is higher than the power voltage;
the SRAM memory cell circuit is used for reading and writing data: the enable terminal is at a high level, the voltage value of the enable terminal is higher than the power voltage, the enable non-terminal is at a low level, and the voltage value of the enable non-terminal is lower than the ground voltage. Compared with the prior art, the invention has the following beneficial effects:
1. the invention provides an SRAM memory cell circuit, which comprises a first phase inverter and a second phase inverter, wherein the first phase inverter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a third PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a third NMOS tube. The second phase inverter comprises a second PMOS tube, a fourth PMOS tube, a second NMOS tube and a fourth NMOS tube, and the first phase inverter and the second phase inverter form a negative feedback circuit to reduce leakage current. Compared with the traditional phase inverter, the first phase inverter formed by the first PMOS tube, the third PMOS tube, the first NMOS tube and the third NMOS tube in the circuit can place a leakage path in a deep cut-off state on the premise of ensuring the phase inversion function, so that the leakage current is reduced by two to three orders of magnitude. Similarly, the second inverter formed by the second PMOS tube, the fourth PMOS tube, the second NMOS tube and the fourth NMOS tube has lower static power consumption compared with the traditional inverter. The first inverter and the second inverter form a feedback structure, so that opposite data can be stored, and the static power consumption of the whole storage unit is remarkably reduced.
2. Because the drive strength of the fifth NMOS tube and the sixth NMOS tube in the conducting state is greater than the pull-up or pull-down network of the first phase inverter and the second phase inverter, the stability of the SRAM memory cell circuit is further improved compared with that of a traditional 6T memory cell circuit when the SRAM memory cell circuit is subjected to write operation.
Drawings
FIG. 1 is a schematic diagram of a conventional 6T SRAM cell circuit;
FIG. 2 is a schematic structural diagram of an SRAM memory cell circuit according to an embodiment;
FIG. 3 is a waveform diagram illustrating the operation of the circuit of FIG. 2;
FIG. 4 is a comparison diagram of static power consumption of a conventional 6T SRAM cell circuit and the SRAM cell circuit of the first embodiment of the present application under different voltages;
fig. 5 is a schematic structural diagram of an SRAM memory cell circuit according to a second embodiment;
FIG. 6 is a waveform diagram illustrating the operation of the circuit of FIG. 5;
FIG. 7 is a comparison diagram of static power consumption of a conventional 6T SRAM memory cell circuit and the SRAM memory cell circuit in the second embodiment of the present application under different voltages;
FIG. 8 is a comparison diagram of read power consumption of the conventional 6T SRAM memory cell circuit and the SRAM memory cell circuit in the second embodiment of the present application under different voltages;
FIG. 9 is a schematic diagram illustrating a comparison between write power consumption of a conventional 6T SRAM memory cell circuit and that of the SRAM memory cell circuit in the second embodiment of the present application under different voltages;
wherein, in fig. 2 and 5: p1-first PMOS transistor, P2-second PMOS transistor, P3-third PMOS transistor, P4-fourth PMOS transistor, P5-fifth PMOS transistor, P6-sixth PMOS transistor, N1-first NMOS transistor, N2-second NMOS transistor, N3-third NMOS transistor, N4-fourth NMOS transistor, N5-fifth NMOS transistor, N6-sixth NMOS transistor, N7-seventh NMOS transistor, N8-eighth NMOS transistor, WL-word line, BL-bit line, BLB-bit line NOT, EN-enable signal, ENB-enable NOT signal, VDD-supply voltage, VSS-ground voltage, QB-first storage node, Q-second storage node, LU-first intermediate node, RU-second intermediate node, LD-third intermediate node, RD-fourth intermediate node.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Referring to fig. 2, an embodiment of the invention provides an SRAM memory cell circuit, which includes a first inverter and a second inverter, wherein the first inverter includes a first PMOS transistor P1, a third PMOS transistor P3, a first NMOS transistor N1, and a third NMOS transistor N3; the second phase inverter comprises a second PMOS tube P2, a fourth PMOS tube P4, a second NMOS tube N2 and a fourth NMOS tube N4; the first inverter and the second inverter form a negative feedback circuit to reduce leakage current.
The difference from the prior art is that the invention provides an SRAM memory cell circuit, which includes a first inverter and a second inverter, wherein the first inverter includes a first PMOS transistor P1, a third PMOS transistor P3, a first NMOS transistor N1, and a third NMOS transistor N3. The second inverter comprises a second PMOS tube P2, a fourth PMOS tube P4, a second NMOS tube N2 and a fourth NMOS tube N4, and the first inverter and the second inverter form a negative feedback circuit to reduce leakage current. Compared with the traditional inverter, the first inverter formed by the first PMOS tube P1, the third PMOS tube P3, the first NMOS tube N1 and the third NMOS tube N3 in the circuit of the invention can place a leakage current path in a deep cut-off state on the premise of ensuring the inversion function by the third PMOS tube P3 and the third NMOS tube N3, thereby reducing the leakage current by two to three orders of magnitude. Similarly, the second inverter formed by the second PMOS transistor P2, the fourth PMOS transistor P4, the second NMOS transistor N2 and the fourth NMOS transistor N4 has lower static power consumption than the conventional inverter. The first inverter and the second inverter form a negative feedback structure, can store opposite data, and remarkably reduces the static power consumption of the whole storage unit.
The above inventive idea is illustrated below in connection with two specific embodiments:
example one
Referring to fig. 2, the SRAM cell circuit of the present embodiment further includes a fifth PMOS transistor P5 to form a first pull-down network bypass, and the first pull-down network bypass is connected to the first inverter.
Further, with continued reference to fig. 2, the SRAM cell circuit further includes a sixth PMOS transistor P6 forming a second pull-down network bypass, and the second pull-down network bypass is connected to the second inverter. Because the drive strength of the fifth NMOS tube and the sixth NMOS tube in the conducting state is greater than the pull-up or pull-down network of the first phase inverter and the second phase inverter, the stability of the SRAM memory cell circuit is further improved compared with that of a traditional 6T memory cell circuit when the SRAM memory cell circuit is subjected to write operation.
Optionally, with continuing reference to fig. 2, the SRAM memory cell circuit may further include a fifth NMOS transistor and a sixth NMOS transistor, and based on this, it can be seen that the structure of the SRAM memory cell circuit in this application is a 12T SRAM memory cell circuit, and the connection relationship of each component is as follows:
a source of the third NMOS transistor N3 and a source of the fourth NMOS transistor N4 are connected to a power supply voltage VDD, a drain of the third NMOS transistor N3 is connected to a source of the first PMOS transistor P1, a drain of the fifth NMOS transistor is connected to a gate of the first PMOS transistor P1, a gate of the first NMOS transistor N1, a gate of the fourth PMOS transistor P4, a gate of the fourth NMOS transistor N4, a drain of the second PMOS transistor P2, and a drain of the second NMOS transistor N2, a drain of the first PMOS transistor P1 and a drain of the first NMOS transistor N1 are connected to a gate of the second NMOS transistor N2, a gate of the second PMOS transistor P2, a gate of the third NMOS transistor N3, a gate of the third PMOS transistor P3, and a drain of the sixth NMOS transistor, and a source of the first NMOS transistor N1 is connected to a drain of the third NMOS transistor P3 and a drain of the fifth NMOS transistor P5.
The source electrode of the third PMOS transistor P3, the source electrode of the fourth PMOS transistor P4, the source electrode of the fifth PMOS transistor P5 and the source electrode of the sixth PMOS transistor P6 are connected to ground, the drain electrode of the fourth NMOS transistor N4 is connected to the source electrode of the second PMOS transistor P2, and the source electrode of the second NMOS transistor N2 is connected to the drain electrode of the fourth PMOS transistor P4 and the drain electrode of the sixth PMOS transistor P6.
The grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are connected with a word line, the source electrode of the fifth NMOS tube is connected with a bit line, the source electrode of the sixth NMOS tube is not connected with the bit line, and the grid electrode of the fifth PMOS tube P5 and the grid electrode of the sixth PMOS tube P6 are used as enabling ends.
Optionally, bulk terminals of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are all connected to the power supply voltage VDD, and bulk terminals of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor and the sixth NMOS transistor are all connected to ground voltage.
Specifically, the SRAM cell circuit further includes a first storage node QB and a second storage node Q, the drain of the first PMOS transistor P1 is set as the first storage node QB, and the drain of the second PMOS transistor P2 is set as the second storage node Q. The SRAM memory cell circuit may further include a first intermediate node LU, a second intermediate node RU, a third intermediate node LD, and a fourth intermediate node RD, wherein a source of the first PMOS transistor P1 is set as the first intermediate node LU, a source of the second PMOS transistor P2 is set as the second intermediate node RU, a source of the first NMOS transistor N1 is set as the third intermediate node LD, and a source of the second NMOS transistor N2 is set as the fourth intermediate node RD.
Referring to fig. 2 and fig. 3, fig. 3 is a waveform schematic diagram of an operating principle of the SRAM memory cell circuit according to the present invention, and the following application examples of specific retention and read/write operations are used to illustrate the technical solution of the SRAM memory cell circuit according to the present application:
when the SRAM memory cell circuit performs a holding operation, the word line WL is a negative voltage lower than the ground level during the data holding period of the SRAM memory cell circuit, so that the fifth NMOS transistor and the sixth NMOS transistor are in a deep cut-off state, and signal changes on the bit line and the bit line bar cannot affect the first storage node QB and the second storage node Q.
The enable signal is at a high level higher than the power supply voltage VDD, and the first pull-down network bypass formed by the fifth PMOS transistor P5 and the second pull-down network bypass formed by the sixth PMOS transistor P6 are both in a deep cut-off state, and cannot affect the first storage node QB and the second storage node Q.
In the circuit of the present invention, the first PMOS transistor P1, the third PMOS transistor P3, the first NMOS transistor N1, and the third NMOS transistor N3 constitute the first inverter, and compared with a conventional inverter, the third PMOS transistor P3 and the third NMOS transistor N3 can use the node voltages of the first intermediate node LU and the third intermediate node LD to place a leakage current path in a deep cut-off state on the premise of ensuring an inversion function, so that the leakage current is reduced by two to three orders of magnitude. Similarly, the second PMOS transistor P2, the fourth PMOS transistor P4, the second NMOS transistor N2, and the fourth NMOS transistor N4 constitute the second inverter, which has lower static power consumption than a conventional inverter. The first inverter and the second inverter form a feedback structure, so that opposite data can be stored, and the static power consumption of the whole storage unit is remarkably reduced.
When the SRAM memory cell circuit performs a write operation, since the write 0 and write 1 operations are similar, the write operation of data will be described in this embodiment by taking only the example of writing data 0 to the SRAM memory cell circuit.
During data writing, an enable signal is a negative voltage lower than a ground level, and the first pull-down network bypass formed by the fifth PMOS transistor P5 and the second pull-down network bypass formed by the sixth PMOS transistor P6 are both in a conducting state, so that the driving capability of the first inverter and the second inverter pull-down network is compensated.
Meanwhile, the word line WL is at a high level higher than the power supply voltage VDD, and at this time, the fifth NMOS transistor and the sixth NMOS transistor are in a strong conduction state. The drains of the second PMOS transistor P2 and the second NMOS transistor N2, and the gates of the first PMOS transistor P1, the first NMOS transistor N1, the fourth PMOS transistor P4, and the fourth NMOS transistor N4 are connected to a bit line BL. Since the bit line BL is at low level 0, assuming that the second storage node Q is at high level 1, the second storage node Q is discharged through the fifth NMOS transistor, and new data 0 is gradually written. Meanwhile, the drains of the first PMOS transistor P1 and the first NMOS transistor N1, the gates of the second PMOS transistor P2, the second NMOS transistor N2, the third PMOS transistor P3 and the third NMOS transistor N3 are turned on with the bit line non-BLB, and new data 1 is gradually written into the first storage node QB. Since the first inverter and the second inverter constitute a feedback loop, new data can be quickly brought into a stable state. Meanwhile, the drive strength of the fifth NMOS tube and the sixth NMOS tube in a conducting state is greater than that of the pull-up or pull-down network of the first phase inverter and the second phase inverter, so that the write stability is further improved compared with that of a traditional 6T storage unit circuit.
When the SRAM memory cell circuit carries out reading operation, the word line WL is at a high level higher than the power supply voltage VDD during the reading operation, the bit line BL and the bit line non-BLB are precharged to be at a high level, and the enable signal is at a negative voltage lower than the ground level. The fifth NMOS transistor, the sixth NMOS transistor, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are all in a conducting state. If the second storage node Q is 0 and the first storage node QB is 1, the bit line BL discharges through the fifth NMOS transistor, the second NMOS transistor N2, the fourth PMOS transistor P4, and the sixth PMOS transistor P6. Since the gate of the sixth PMOS transistor P6 is connected to the enable signal, it is in a strong conduction state, that is, the voltage drop between the fourth intermediate node RD and the ground is 0, so that the discharge current can be enhanced, and the read stability can be improved.
Referring to fig. 4, fig. 4 is a schematic diagram showing comparison of static power consumption of memory arrays respectively formed by a conventional 6T memory cell circuit and an SRAM memory cell circuit with very low static power consumption according to the present invention under different power supply voltages VDD. It can be seen that the static power consumption of the SRAM memory cell circuit proposed by the present invention is significantly improved compared to the conventional 6T memory cell structure. When the power supply voltage VDD is 0.4V, the structure provided by the invention reduces the static power consumption by 435 times.
Example two
Referring to fig. 5, the SRAM memory cell circuit in this embodiment further includes a seventh NMOS transistor N7 and an eighth NMOS transistor N8, and based on this, it can be seen that the structure of the SRAM memory cell circuit in this application is a 14T SRAM memory cell circuit, and the connection relationship of each component is as follows:
the source electrode of the third NMOS transistor N3, the source electrode of the fourth NMOS transistor N4, the source electrode of the fifth NMOS transistor N5 and the source electrode of the sixth NMOS transistor N6 are connected to a power supply voltage VDD, the drain electrode of the third NMOS transistor N3 and the drain electrode of the fifth NMOS transistor N5 are connected to the source electrode of the first PMOS transistor P1, the drain electrode of the seventh NMOS transistor N7 is connected with the gate electrode of the first PMOS transistor P1, the gate electrode of the first NMOS transistor N1, the gate electrode of the fourth PMOS transistor P4, the gate electrode of the fourth NMOS transistor N4, the drain electrode of the second PMOS transistor P2 and the drain electrode of the second NMOS transistor N2, the drain electrode of the first PMOS transistor P1 and the drain electrode of the first NMOS transistor N1 are connected with the grid electrode of the second NMOS transistor N2, the grid electrode of the second PMOS transistor P2, the grid electrode of the third NMOS transistor N3, the grid electrode of the third PMOS transistor P3 and the drain electrode of the eighth NMOS transistor N8, the source electrode of the first NMOS transistor N1 is connected with the drain electrode of the third PMOS transistor P3 and the drain electrode of the fifth PMOS transistor P5.
The source electrode of the third PMOS transistor P3, the source electrode of the fourth PMOS transistor P4, the source electrode of the fifth PMOS transistor P5 and the source electrode of the sixth PMOS transistor P6 are connected to a ground voltage VSS, the drain electrode of the fourth NMOS transistor N4 and the drain electrode of the sixth NMOS transistor P2 are connected to the source electrode of the second PMOS transistor P2, and the source electrode of the second NMOS transistor N2 is connected to the drain electrode of the fourth PMOS transistor P4 and the drain electrode of the sixth PMOS transistor P6.
The gate of the seventh NMOS transistor N7 and the gate of the eighth NMOS transistor N8 are connected to a word line, the source of the seventh NMOS transistor N7 is connected to a bit line, the source of the eighth NMOS transistor N8 is not connected to a bit line, the gates of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are used as enable terminals, and the gates of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are used as enable terminals.
Optionally, bulk terminals of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are all connected to the power supply voltage VDD. The bulk terminals of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 are all connected to a ground voltage VSS.
Specifically, the SRAM cell circuit further includes a first storage node QB and a second storage node Q, the drain of the first PMOS transistor P1 is set as the first storage node QB, and the drain of the second PMOS transistor P2 is set as the second storage node Q.
The SRAM memory cell circuit further includes a first intermediate node LU, a second intermediate node RU, a third intermediate node LD, and a fourth intermediate node RD, the source of the first PMOS transistor P1 is set as the first intermediate node LU, the source of the second PMOS transistor P2 is set as the second intermediate node RU, the source of the first NMOS transistor N1 is set as the third intermediate node LD, and the source of the second NMOS transistor N2 is set as the fourth intermediate node RD.
Referring to fig. 5 and fig. 6, fig. 6 is a waveform diagram illustrating an operating principle of the SRAM memory cell circuit according to the present invention, and the following application examples of specific retention and read/write operations are used to illustrate the technical solution of the SRAM memory cell circuit according to the present application:
when the SRAM memory cell circuit performs a holding operation, during a period in which the SRAM memory cell circuit holds data, the word line WL is at a negative voltage lower than the ground voltage VSS, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are placed in a deep cut state, and signal changes on the bit line BL and the bit line non-BLB cannot affect the first storage node QB and the second storage node Q.
The enable signal EN is a negative voltage lower than the ground voltage VSS, the enable non-signal ENB is a high level higher than the power supply voltage VDD, and the first bypass formed by the fifth NMOS transistor N5 and the fifth PMOS transistor P5 and the second bypass formed by the sixth NMOS transistor N6 and the sixth PMOS transistor P6 are both in a deep cut-off state and cannot affect the first storage node QB and the second storage node Q.
Compared with the traditional inverter, the third PMOS tube P3 and the third NMOS tube N3 can place a leakage path in a deep cut-off state on the premise of ensuring an inverting function, so that static power consumption is reduced by two to three orders of magnitude. At this time, the node voltages of the first intermediate node LU and the third intermediate node LD play roles of holding data and suppressing a leakage current. Similarly, the second PMOS transistor P2, the fourth PMOS transistor P4, the second NMOS transistor N2, and the fourth NMOS transistor N4 form a second inverter, which has lower static power consumption than the conventional inverter. The first inverter and the second inverter form a feedback structure, and can store opposite data with extremely low static power consumption overhead.
When the SRAM memory cell circuit performs a write operation, since the write 0 and write 1 operations are similar, a write operation of data will now be described by taking, as an example, write data 0 to the memory cell circuit of the present invention.
During writing data, the enable signal EN is at a high level higher than the power voltage VDD, the enable non-signal ENB is at a negative voltage lower than the ground voltage VSS, the first bypass formed by the fifth NMOS transistor N5 and the fifth PMOS transistor P5, and the second bypass formed by the sixth NMOS transistor N6 and the sixth PMOS transistor P6 are both in a conducting state, such that the voltage values of the first intermediate node LU and the second intermediate node RU are the power voltage VDD, and the voltage values of the third intermediate node LD and the fourth intermediate node RD are the ground voltage VSS, thereby enhancing the driving capability of the pull-up network and the pull-down network of the first inverter and the second inverter.
Meanwhile, the word line WL is set to a high level, and at this time, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are in a turn-on state. The drains of the second PMOS transistor P2 and the second NMOS transistor N2, and the gates of the first PMOS transistor P1, the first NMOS transistor N1, the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected to the bit line BL. Since the bit line BL is at low level 0, assuming that the second storage node Q is at high level 1, the second storage node Q is discharged through the seventh NMOS transistor N7, and new data 0 is gradually written. Meanwhile, the drains of the first PMOS transistor P1 and the first NMOS transistor N1, and the gates of the second PMOS transistor P2, the second NMOS transistor N2, the third PMOS transistor P3 and the third NMOS transistor N3 are conducted with the bit line non-BLB, and the new data 1 is gradually written into the first storage node QB. Since the first inverter and the second inverter constitute a feedback loop, new data can be quickly brought into a stable state. Meanwhile, the drive strength of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 in a conducting state is greater than that of the pull-up or pull-down network of the first inverter and the second inverter, so that the write stability is further improved compared with that of a traditional 6T memory cell circuit.
When the SRAM memory cell circuit performs a read operation, the word line WL is at a high level during the read operation, the bit line BL and the bit line non-BLB are precharged to a high level, the enable signal EN is at a high level higher than the power supply voltage VDD, and the enable non-signal ENB is at a negative voltage lower than the ground voltage VSS. The seventh NMOS transistor N7, the eighth NMOS transistor N8, the fifth NMOS transistor N5, the fifth PMOS transistor P5, the sixth NMOS transistor N6 and the sixth PMOS transistor P6 are all in a conducting state. If the second storage node Q is 0 and the second storage node QB is 1, the bit line BL discharges through the seventh NMOS transistor N7, the second NMOS transistor N2, the fourth PMOS transistor P4 and the sixth PMOS transistor P6. Since the gate of the sixth PMOS transistor P6 is connected to the enable non-signal ENB and is in a strong conduction state, that is, the fourth intermediate node RD is conducted to the ground, the discharge current can be enhanced, and the read stability is improved.
Referring to fig. 7, fig. 7 is a schematic diagram showing comparison of static power consumption of memory arrays respectively formed by a conventional 6T memory cell circuit and an ultra-low voltage oriented low power consumption SRAM memory cell circuit according to the present invention under different power supply voltages VDD. It can be seen that the static power consumption of the SRAM memory cell circuit proposed by the present invention is significantly improved compared to the conventional 6T memory cell structure. When the power supply voltage VDD is 0.4V, the structure proposed by the present invention reduces the static power consumption by 242 times.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating a comparison of write power consumption of memory arrays respectively formed by a conventional 6T memory cell circuit and an ultra-low voltage oriented SRAM memory cell circuit according to the present invention under different power supply voltages VDD. It can be seen that the circuit structure proposed by the present invention has lower write power consumption than the conventional 6T memory cell structure. When the power supply voltage VDD is 0.4V, the structure provided by the invention reduces the write power consumption by 45%.
Referring to fig. 9, fig. 9 is a comparison diagram of read power consumption of memory arrays respectively formed by the conventional 6T memory cell circuit and the ultra-low voltage oriented SRAM memory cell circuit according to the present invention under different power supply voltages VDD. It can be seen that the static power consumption of the circuit structure provided by the invention is improved in the range of 0.2V-0.45V compared with the conventional 6T memory cell structure, and is greater than the read power consumption of the conventional 6T memory cell structure when the power supply voltage VDD is greater than 0.45V. When the power supply voltage VDD is 0.4V, the structure provided by the invention reduces the reading power consumption by 65%.
In summary, the present invention provides an SRAM memory cell circuit, which includes a first inverter and a second inverter, where the first inverter includes a first PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a third NMOS transistor. The second phase inverter comprises a second PMOS tube, a fourth PMOS tube, a second NMOS tube and a fourth NMOS tube, and the first phase inverter and the second phase inverter form a negative feedback circuit to reduce leakage current. Compared with the traditional phase inverter, the first phase inverter formed by the first PMOS tube, the third PMOS tube, the first NMOS tube and the third NMOS tube in the circuit can place a leakage path in a deep cut-off state on the premise of ensuring the phase inversion function, so that the leakage current is reduced by two to three orders of magnitude. Similarly, the second inverter formed by the second PMOS tube, the fourth PMOS tube, the second NMOS tube and the fourth NMOS tube has lower static power consumption compared with the traditional inverter. The first inverter and the second inverter form a feedback structure, so that opposite data can be stored, and the static power consumption of the whole storage unit is remarkably reduced.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. An SRAM memory cell circuit, comprising:
a first phase inverter formed by a first PMOS tube, a third PMOS tube, a first NMOS tube and a third NMOS tube;
a second inverter consisting of a second PMOS tube, a fourth PMOS tube, a second NMOS tube and a fourth NMOS tube;
the first inverter and the second inverter form a negative feedback circuit to reduce the leakage current of the SRAM memory cell circuit.
2. The SRAM memory cell circuit of claim 1, further comprising a fifth PMOS transistor forming a first pull-down network bypass and a sixth PMOS transistor forming a second pull-down network bypass;
the first pull-down network bypass is connected with the first inverter;
the second pull-down network bypass is connected with the second inverter.
3. The SRAM memory cell circuit of claim 2, further comprising a fifth NMOS transistor and a sixth NMOS transistor;
the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are connected with a power supply voltage, the drain electrode of the third NMOS tube is connected with the source electrode of the first PMOS tube, the drain electrode of the fifth NMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube, the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the third PMOS tube and the drain electrode of the sixth NMOS tube, and the source electrode of the first NMOS tube is connected with the drain electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube;
the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with ground voltage, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth PMOS tube and the drain electrode of the sixth PMOS tube;
the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are connected with a word line, the source electrode of the fifth NMOS tube is connected with a bit line, the source electrode of the sixth NMOS tube is not connected with the bit line, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are used as enabling ends.
4. The SRAM memory cell circuit of claim 3, wherein the body terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage, and the body terminals of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all connected to ground.
5. The SRAM memory cell circuit of claim 3, wherein, while the SRAM memory cell circuit is holding data: the enable end is at a high level, and the voltage value of the enable end is higher than the power supply voltage;
the SRAM memory cell circuit is used for reading and writing data: the enable terminal is at a low level, and the voltage value of the enable terminal is lower than the ground voltage.
6. The SRAM memory cell circuit of claim 1, further comprising:
a first bypass formed by a fifth NMOS tube and a fifth PMOS tube;
a second bypass formed by a sixth NMOS tube and a sixth PMOS tube;
the first bypass is connected to the first inverter and the second bypass is connected to the second inverter.
7. The SRAM memory cell circuit of claim 6, further comprising a seventh NMOS transistor and an eighth NMOS transistor;
the source electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor, the source electrode of the fifth NMOS transistor and the source electrode of the sixth NMOS transistor are connected with a power supply voltage, the drain electrode of the third NMOS tube and the drain electrode of the fifth NMOS tube are connected with the source electrode of the first PMOS tube, the drain electrode of the seventh NMOS transistor is connected with the grid electrode of the first PMOS transistor, the grid electrode of the first NMOS transistor, the grid electrode of the fourth PMOS transistor, the grid electrode of the fourth NMOS transistor, the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor, the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube are connected with the grid electrode of the second NMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the third PMOS tube and the drain electrode of the eighth NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the third PMOS tube and the drain electrode of the fifth PMOS tube;
the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected with ground voltage, the drain electrode of the fourth NMOS tube and the drain electrode of the sixth NMOS tube are connected with the source electrode of the second PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth PMOS tube and the drain electrode of the sixth PMOS tube;
the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube are connected with a word line, the source electrode of the seventh NMOS tube is connected with a bit line, the source electrode of the eighth NMOS tube is not connected with the bit line, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are used as enabling ends, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are used as enabling non-ends.
8. The SRAM memory cell circuit of claim 7, wherein body terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the supply voltage;
the body ends of the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are all connected with ground voltage.
9. The SRAM memory cell circuit of claim 7, wherein, while the SRAM memory cell circuit is holding data: the enable terminal is at a low level, the voltage value of the enable terminal is lower than the ground voltage, the enable non-terminal is at a high level, and the voltage value of the enable non-terminal is higher than the power voltage;
the SRAM memory cell circuit is used for reading and writing data: the enable terminal is at a high level, the voltage value of the enable terminal is higher than the power voltage, the enable non-terminal is at a low level, and the voltage value of the enable non-terminal is lower than the ground voltage.
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