CN113109955A - Display substrate, display device and detection method - Google Patents

Display substrate, display device and detection method Download PDF

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Publication number
CN113109955A
CN113109955A CN202110400356.4A CN202110400356A CN113109955A CN 113109955 A CN113109955 A CN 113109955A CN 202110400356 A CN202110400356 A CN 202110400356A CN 113109955 A CN113109955 A CN 113109955A
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China
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sub
lighting test
signal line
test signal
control signal
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CN202110400356.4A
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Chinese (zh)
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CN113109955B (en
Inventor
张建平
张静
王志强
崔辛超
刘元
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to CN202110400356.4A priority Critical patent/CN113109955B/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Abstract

A display substrate, a detection method and a display device are provided, wherein the display substrate comprises a display area and a peripheral area surrounding the display area, the peripheral area comprises a lighting test unit arranged on a first side of the display area, a multi-path selection unit arranged on a second side of the display area, and a fan-shaped area arranged on one side, far away from the display area, of the multi-path selection unit, the fan-shaped area comprises a plurality of fan-out leads, the first side and the second side are opposite to each other, and the display area comprises a plurality of sub-pixel columns and a plurality of data lines in one-to-one correspondence with the sub-pixel columns; the lighting test unit provides a lighting test signal to the data line; and the multi-path selection unit provides a signal of one fan-out lead to the data lines corresponding to at least two sub-pixel columns. According to the scheme provided by the embodiment, the lighting test unit and the multi-path selection unit are independently arranged, so that the defect of the fan-out lead wire is conveniently detected.

Description

Display substrate, display device and detection method
Technical Field
The present disclosure relates to display technologies, and more particularly, to a display substrate, a display device and a detection method.
Background
The liquid crystal display panel is mainly composed of a Thin Film Transistor (TFT) and a Color Filter (CF) substrate, and lighting detection is performed after a box is formed, whether a liquid crystal cell is defective or not is confirmed, a Polarizer (POL) is attached to a good product, and a module is assembled by module processes such as Bonding IC (Bonding IC) and Flexible Printed Circuit (FPC) and then lighting is performed to confirm whether a defect exists or not. The lighting of the liquid crystal box and the lighting of the module are different, when the liquid crystal box is lighted, a lighting jig Probe (PIN) is directly pressed to the input voltage of a liquid crystal box slave Cell Test (CT) unit to realize display; when the module is lighted, the voltage signal will pass through the FPC and Integrated Circuit (IC) and enter the display area through the fan-shaped area (Fanout) to realize display.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the disclosure provides a display substrate, a display device and a detection method.
In one aspect, an embodiment of the present disclosure provides a display substrate, where the display substrate includes a display area and a peripheral area surrounding the display area, the peripheral area includes a lighting test unit disposed on a first side of the display area, a multi-path selection unit disposed on a second side of the display area, and a sector area disposed on a side of the multi-path selection unit away from the display area, the sector area includes a plurality of fan-out leads, the first side and the second side are opposite sides, and the display area includes a plurality of sub-pixel rows and a plurality of data lines corresponding to the sub-pixel rows one to one;
the lighting test unit is electrically connected with a plurality of test control ends, a lighting test signal end and the data line and is configured to provide a lighting test signal of the lighting test signal end to the data line under the control of the test control ends;
the multiplexing unit is electrically connected with a plurality of data control terminals, fan-out leads and the data lines, and is configured to provide signals of the fan-out leads to the data lines under the control of the data control terminals, and provide signals of one fan-out lead to the data lines corresponding to at least two sub-pixel columns.
In an exemplary embodiment, a signal of one fan-out lead is supplied to a data line corresponding to a plurality of non-adjacent sub-pixel columns.
In an exemplary embodiment, the lighting test signal terminal includes a first lighting test signal terminal and a second lighting test signal terminal, the lighting test unit includes a first lighting test signal line electrically connected to the first lighting test signal terminal, a second lighting test signal line electrically connected to the second lighting test signal terminal, first switch units corresponding to the sub-pixel rows one by one, a plurality of first control signal lines electrically connected to the plurality of test control terminals, respectively, the first switch units electrically connected to the first lighting test signal line or the second lighting test signal line, and one first control signal line, wherein,
the first switch unit is configured to supply a signal of the first lighting test signal line or the second lighting test signal line to a data line under control of the first control signal line, and a signal of the first lighting test signal line is supplied to a data line corresponding to an even column of sub-pixel columns, and a signal of the second lighting test signal line is supplied to a data line corresponding to an odd column of sub-pixel columns.
In an exemplary embodiment, the data lines to which the same fan-out lead is electrically connected are electrically connected to the same lighting test signal line, and the data lines to which the adjacent fan-out leads are electrically connected to different lighting test signal lines.
In an exemplary embodiment, the sub-pixel columns include a first color sub-pixel column, a second color sub-pixel column, and a third color sub-pixel column, the plurality of first control signal lines include a first sub-control signal line controlling the first switching unit connected to the data line of the first color sub-pixel column, a second sub-control signal line controlling the first switching unit connected to the data line of the second color sub-pixel column, and a third sub-control signal line controlling the first switching unit connected to the data line of the third color sub-pixel column.
In an exemplary embodiment, the lighting test unit further includes a second switch unit in one-to-one correspondence with the first switch unit, and a total control signal line, and the second switch unit is electrically connected to the first lighting test signal line or the second lighting test signal line, where:
the second switch unit is configured to supply a signal of the first lighting test signal line or the second lighting test signal line to the first switch unit under control of the total control signal line.
In an exemplary embodiment, the multiplexing unit includes: the third switch unit is in one-to-one correspondence with the sub-pixel rows, and a plurality of second control signal lines are respectively and electrically connected with the plurality of data control ends, the third switch unit is electrically connected with one fan-out lead and one second control signal line, wherein:
the third switching unit is configured to supply a signal of the fan-out lead to a data line under the control of the second control signal line.
In an exemplary embodiment, the sub-pixel columns include a first color sub-pixel column, a second color sub-pixel column, and a third color sub-pixel column, the plurality of second control signal lines include a fourth sub-control signal line controlling the third switching unit connected to the data line of the first color sub-pixel column, a fifth sub-control signal line controlling the third switching unit connected to the data line of the second color sub-pixel column, and a sixth sub-control signal line controlling the third switching unit connected to the data line of the third color sub-pixel column, and the signal of one fan-out lead is provided to the data lines corresponding to the three sub-pixel columns which are not adjacent and have different colors.
In another aspect, an embodiment of the present disclosure provides a display device, which includes the above display substrate.
In another aspect, an embodiment of the present disclosure provides a detection method applied to the display substrate, where the detection method includes:
loading a conduction control signal to the data control end to conduct the fan-out lead and the data line;
and loading a lighting test signal to the lighting test signal end, and sequentially conducting the lighting test signal end and the data line to enable the display substrate to display a gray scale picture.
In an exemplary embodiment, the lighting test signal terminal includes a first lighting test signal terminal and a second lighting test signal terminal, and the loading the lighting test signal to the lighting test signal terminal includes: and respectively loading lighting test signals with the same magnitude and opposite polarities to the first lighting test signal end and the second lighting test signal end.
The display substrate comprises a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a lighting test unit arranged on a first side of the display area, a multi-path selection unit arranged on a second side of the display area, and a sector area arranged on one side, far away from the display area, of the multi-path selection unit, the sector area comprises a plurality of fan-out leads, the first side and the second side are opposite, and the display area comprises a plurality of sub-pixel columns and a plurality of data lines in one-to-one correspondence with the sub-pixel columns; the lighting test unit is electrically connected with a plurality of test control ends, a lighting test signal end and the data line and is configured to provide a lighting test signal of the lighting test signal end to the data line under the control of the test control ends; the multiplexing unit is electrically connected with a plurality of data control terminals, fan-out leads and the data lines, and is configured to provide signals of the fan-out leads to the data lines under the control of the data control terminals, and provide signals of one fan-out lead to the data lines corresponding to at least two sub-pixel columns. According to the scheme provided by the embodiment, the lighting test unit and the multi-path selection unit are separately arranged, so that the defect of the fan-out lead can be conveniently detected during box test, and the waste of rear-end module materials is avoided; in addition, when the lighting test unit is arranged on the signal output side of the display substrate, the surface of the lighting test unit is covered with other film layers, and compared with the scheme that static electricity is led in due to the exposed state when the lighting test unit is arranged on the signal input side of the display substrate, the scheme provided by the embodiment can reduce the static electricity at the lighting test unit and improve the product yield.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic view of a display substrate according to an embodiment;
fig. 2 is a schematic plan view of a display substrate provided in an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a display substrate provided in accordance with an exemplary embodiment;
FIG. 4 is a schematic diagram of an electrical equivalent of a display substrate according to an exemplary embodiment;
FIG. 5 is a schematic diagram of an electrical equivalent of a display substrate according to an exemplary embodiment;
FIG. 6 is a schematic diagram illustrating driving timing of a display substrate according to an exemplary embodiment;
FIG. 7 is a schematic diagram illustrating an exemplary embodiment of a display substrate with a short circuit failure;
FIG. 8 is a schematic diagram illustrating a defective display panel detected by a display substrate according to an exemplary embodiment;
fig. 9 is a flowchart of a detection method according to an exemplary embodiment.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the case of conflict, the embodiments of the present disclosure and the features of the embodiments may be arbitrarily combined with each other.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, the embodiments of the present disclosure are not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or numerical values shown in the drawings.
The ordinal numbers such as "first", "second", "third", etc., in this disclosure are provided to avoid confusion among the constituent elements, and do not indicate any order, number, or importance.
In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the disclosure are not limited thereto, and may be replaced as appropriate.
In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.
In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other.
In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.
In the present disclosure, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.
The display panel can be cut, carried by personnel and detected when being formed into a box, and because Fanout wiring is exposed outside and the area is large, the Fanout area scratch is easily caused in the process, so that adjacent wiring Short circuits (Short) are connected together, the lighting of the liquid crystal box is not problematic, but poor Touch (Touch) blocks and dark lines can occur when the module is lighted.
In one solution, the MUX unit and the CT unit are designed to be shared, and in this case, the lighting of the liquid crystal cell cannot detect the defect caused by the Fanout scratch, as shown in fig. 1. When the liquid crystal box is lighted, the lighting fixture Probe (PIN) is directly pressed to the liquid crystal box, the voltage is input from a box Test (CT) unit to realize display, and the display does not pass through a sector, so that the defect caused by the sector damage cannot be detected.
Fig. 2 is a schematic plan view of a display substrate according to an embodiment of the disclosure. As shown in fig. 2, a display substrate provided by an embodiment of the present disclosure includes: the display device comprises a display area 100 and a peripheral area 200 surrounding the display area 100, wherein the peripheral area 200 comprises a lighting test unit 10 arranged on a first side of the display area 100, a multi-path selection unit 20 arranged on a second side of the display area 100, and a sector area 30 arranged on one side of the multi-path selection unit 20 far away from the display area 100, the sector area 30 comprises a plurality of fan-out leads 31, the first side and the second side are opposite sides, and the display area 100 comprises a plurality of sub-pixel columns and a plurality of data lines 101 corresponding to the sub-pixel columns one by one; the sub-pixel column includes a plurality of sub-pixels, and the data lines 101 corresponding to the sub-pixel column are configured to provide data signals to the sub-pixels of the corresponding sub-pixel column to light the sub-pixels. The sector 30 includes a binding region 40 on a side thereof away from the display region 100, and the binding region 40 can be bound to the flexible circuit board 50. The peripheral region 200 may further include a Gate On Array (GOA) circuit 60 disposed on at least one of a third side and a fourth side of the display region 100, where the GOA circuit 60 is configured to sequentially output a scan signal to the sub-pixel rows and turn on the sub-pixels row by row. The third side and the fourth side are adjacent to the first side and the second side. As can be seen, the first side may be a signal output (Data Out, DO) side of the display substrate, and the second side may be a signal input (DP) side of the display substrate.
In an exemplary embodiment, the display substrate is, for example, a liquid crystal display substrate.
Fig. 3 is a schematic circuit diagram of a display substrate according to an embodiment of the disclosure. As shown in fig. 3, the lighting test unit 10 is electrically connected to a plurality of test control terminals a1To An, lighting up a test signal terminal D and the data line 101, configured to be at the test control terminal A1Supplying a lighting test signal of a lighting test signal terminal D to the data line 101 under the control of An;
the multiplexer unit 20 is electrically connected to a plurality of data control terminals C1To CmFan-out lead Data1To DatakAnd the data line 101 configured to be at the data control terminal C1To CmUnder the control of (1), the signals of the fan-out leads Data1 to Datak of the sector area 30 are provided to the Data line 101, and the signal of one fan-out lead is provided to the Data lines corresponding to at least two sub-pixel columns. m, N may be related to the number of sub-pixels included in a pixel, for example, when a pixel includes 3 sub-pixels, m, N may be 3, and k is related to the number of data lines connected to the sub-pixel column and one fan-out lead, for example, when one fan-out lead connects 3 data lines, and the sub-pixel column is N columns, k is N/3.
According to the scheme provided by the embodiment, the lighting test unit and the multi-path selection unit are separately arranged, so that the defect of the fan-out lead can be conveniently detected during box test, and the waste of rear-end module materials is avoided; in addition, when the lighting test unit is arranged on the signal output side of the display substrate, the surface of the lighting test unit is covered with other film layers, and compared with the scheme that static electricity is led in due to the exposed state when the lighting test unit is arranged on the signal input side of the display substrate, the scheme provided by the embodiment can reduce the static electricity at the lighting test unit and improve the product yield.
In an exemplary embodiment, the number of data lines electrically connected to the same fan-out lead is not particularly limited, and may be greater than 1, for example, the number of data lines electrically connected to the same fan-out lead may be 2, 3, 6, and so on.
In an exemplary embodiment, the signal of one fan-out lead may be provided to a data line corresponding to a plurality of sub-pixel columns which are not adjacent. For example, as shown in fig. 4, fan-out lead Data1 is electrically connected to sub-pixel column B1, sub-pixel column R1, and sub-pixel column G2, where sub-pixel column B1, sub-pixel column R1, and sub-pixel column G2 are not adjacent to each other; fan-out lead Data2 is electrically connected to subpixel column G1, subpixel column B2, and subpixel column R2, wherein subpixel column G1, subpixel column B2, and subpixel column R2 are not adjacent to each other.
In an exemplary embodiment, the lighting test signal terminals D include a first lighting test signal terminal D1 and a second lighting test signal terminal D2, and the lighting test unit 10 includes a first lighting test signal line CTD _ EVEN electrically connected to the first lighting test signal terminal D1, a second lighting test signal line CTD _ ODD electrically connected to the second lighting test signal terminal D2, first switch units 11 corresponding to the sub-pixel rows one by one, and a plurality of test control terminals a and b, respectively1A plurality of first control signal lines respectively electrically connected to An, the first switch unit 11 is electrically connected to the first lighting test signal line CTD _ EVEN or the second lighting test signal line CTD _ ODD, and a first control signal line aiWherein, in the step (A),
the first switching unit 11 is configured to supply the signal of the first lighting test signal line CTD _ EVEN or the signal of the second lighting test signal line CTD _ ODD to the data line 101 under the control of the first control signal line, and the signal of the first lighting test signal line CTD _ EVEN may be supplied to the data line corresponding to the EVEN-column sub-pixel column and the signal of the second lighting test signal line CTD _ ODD may be supplied to the data line corresponding to the ODD-column sub-pixel column. That is, the first switching units 11 of the EVEN columns are electrically connected to the first lighting test signal line CTD _ EVEN, and the first switching units 11 of the ODD columns are electrically connected to the second lighting test signal line CTD _ ODD.
The sub-pixels adjacent to the liquid crystal display substrate are loaded with voltages having the same magnitude and opposite polarities, and the polarity inversion may be performed once per frame, but is not limited thereto.
As shown in fig. 4, the sub-pixel columns R1, B1, and G2 are sub-pixel columns of ODD columns connected to the second lighting test signal line CTD _ ODD through the first switching unit 11, and the sub-pixel columns G1, R2, and B2 are sub-pixel columns of EVEN columns connected to the first lighting test signal line CTD _ EVEN through the first switching unit 11.
In an exemplary implementation, the data lines to which the same fan-out lead is electrically connected are electrically connected to the same lighting test signal line, for example, both are electrically connected to the first lighting test signal line, or both are electrically connected to the second lighting test signal line.
In an exemplary embodiment, the data lines to which the adjacent fan-out leads are electrically connected to different lighting test signal lines. For example, in the data lines electrically connected to the first fan-out lead and the second fan-out lead which are adjacent to each other, the data line electrically connected to the first fan-out lead is electrically connected to the first lighting test signal line, and the data line electrically connected to the second fan-out lead is electrically connected to the second lighting test signal line. For example, the fan-out lead line Data1 is electrically connected to the Data lines corresponding to the sub-pixel columns R1, B1, and G2, and the Data lines corresponding to the sub-pixel columns R1, B1, and G2 are all electrically connected to the second lighting test signal line CTE _ ODD; namely, the data wires electrically connected with the same fan-out lead wire are electrically connected with the same lighting test signal wire; the fan-out lead Data2 is electrically connected to the Data lines corresponding to the sub-pixel columns G1, R2 and B2, and the Data lines corresponding to the sub-pixel columns G1, R2 and B2 are all electrically connected to the first dot lamp test signal line CTD _ EVEN. The data lines electrically connected to the adjacent fan-out leads are electrically connected to different lighting test signal lines.
In an exemplary embodiment, as shown in fig. 5, the first switching unit 11 may include a thin film transistor, a control electrode of which is electrically connected to the first control signal line, a first electrode of which is electrically connected to the data line, and a second electrode of which is electrically connected to the first lighting test signal line CTD _ EVEN or the second lighting test signal line CTD _ ODD. The control electrode is, for example, a gate, the first electrode may be a source or a drain, and the second electrode may be a source or a drain. The first to sixth thin film transistors T11 to T16 respectively represent 6 first switching units 11. Fig. 5 shows only an exemplary structure of the first switching unit, and the implementation of the first switching unit is not limited thereto as long as the function thereof can be implemented.
In an exemplary embodiment, the sub-pixel columns include a first color sub-pixel column, a second color sub-pixel column, and a third color sub-pixel column, the plurality of first control signal lines include a first sub-control signal line CTSWR controlling a first switching unit connected to a data line of the first color sub-pixel column, a second sub-control signal line CTSWG controlling a first switching unit connected to a data line of the second color sub-pixel column, and a third sub-control signal line CTSWB controlling a first switching unit connected to a data line of the third color sub-pixel column. As shown in fig. 4, the first color sub-pixel column may be a red sub-pixel column, the second color sub-pixel column may be a green sub-pixel column, the third color sub-pixel column may be a blue sub-pixel column, the sub-pixel columns R1 and R2 are red sub-pixel columns electrically connected to a first sub-control signal line CTSWR, the sub-pixel columns G1 and G2 are green sub-pixel columns electrically connected to a second sub-control signal line CTSWG, and the sub-pixel columns B1 and B2 are blue sub-pixel columns electrically connected to a third sub-control signal line CTSWB.
In an exemplary embodiment, the lighting test unit further includes a second switch unit 12 corresponding to the first switch unit 11 one to one, a total control signal line CTSW electrically connected to a total control signal terminal C, and the second switch unit 12 electrically connected to the first lighting test signal line CTD _ EVEN or the second lighting test signal line CTD _ ODD, where:
the second switch unit 12 is configured to supply the signal of the first lighting test signal line CTD _ EVEN or the second lighting test signal line CTD _ ODD to the first switch unit 11 under the control of the total control signal line CTSW. For example, the second switching units 12 of the EVEN-numbered columns are electrically connected to the first lighting test signal line CTD _ EVEN, and the second switching units 12 of the ODD-numbered columns are electrically connected to the second lighting test signal line CTD _ ODD. That is, it is possible to control whether to turn on the test using the total control signal line CTSW, and when the test is performed, all the second switching units 12 are turned on through the total control signal line CTSW, and when the test is not performed, all the second switching units 12 are turned off through the total control signal line CTSW.
In an exemplary embodiment, as shown in fig. 5, the second switch unit 12 may include a thin film transistor, a control electrode of which is electrically connected to the total control signal line CTSW, a first electrode of which is electrically connected to the first switch unit 11, and a second electrode of which is electrically connected to the first lighting test signal line CTD _ EVEN or the second lighting test signal line CTD _ ODD. The control electrode of the thin film transistor is, for example, a gate electrode, the first electrode may be a source electrode or a drain electrode, and the second electrode may be a drain electrode or a source electrode. The seventh to twelfth thin film transistors T21 to T26 respectively represent 6 second switching units 12. Fig. 5 shows only an exemplary structure of the second switching unit, and the implementation of the second switching unit is not limited thereto as long as the function thereof can be implemented.
In an exemplary embodiment, as shown in fig. 4, the multiplexing unit 20 includes: third switching units 21 corresponding to the sub-pixel columns one to one, a plurality of second control signal lines electrically connected to the plurality of data control terminals Cj (j is 1 to m), respectively, the third switching units 21 electrically connected to one of the fan-out leads and one of the second control signal lines, wherein:
the third switching unit 21 is configured to supply a signal of the fan-out lead to a data line under the control of the second control signal line.
In an exemplary embodiment, as shown in fig. 5, the third switching unit 21 may include a thin film transistor, a control electrode of which is electrically connected to one second control signal line, a first electrode of which is electrically connected to the data line, and a second electrode of which is electrically connected to the fan-out lead. The control electrode is, for example, a gate, the first electrode may be a source or a drain, and the second electrode may be a drain or a source. The thirteenth to eighteenth thin film transistors T31 to T36 respectively represent 6 third switching units 21. Fig. 5 shows only an exemplary structure of the third switching unit, and the implementation of the third switching unit is not limited thereto as long as the function thereof can be implemented.
In an exemplary embodiment, the subpixel columns include a first color subpixel column, a second color subpixel column, and a third color subpixel column, the plurality of second control signal lines include a fourth sub-control signal line MUXR controlling the third switching cells 21 connected to the data lines of the first color subpixel column, a fifth sub-control signal line MUXG controlling the third switching cells 21 connected to the data lines of the second color subpixel column, and a sixth sub-control signal line MUXB controlling the third switching cells 21 connected to the data lines of the third color subpixel column, and the signal of one fan-out lead may be provided to the data lines corresponding to the three subpixel columns of non-adjacent and different colors. For example, the first color sub-pixel column may be a red sub-pixel column, the second color sub-pixel column may be a green sub-pixel column, the third color sub-pixel column may be a blue sub-pixel column, the sub-pixel columns R1 and R2 are red sub-pixel columns electrically connected to the fourth sub-control signal line MUXR, the sub-pixel columns G1 and G2 are green sub-pixel columns electrically connected to the fifth sub-control signal line MUXG, and the sub-pixel columns B1 and B2 are blue sub-pixel columns electrically connected to the sixth sub-control signal line MUXB. The signal of fan-out lead Data1 is supplied to 3 sub-pixel columns R1, B1, and G2 which are not adjacent and different in color, and the signal of fan-out lead Data2 is supplied to 3 sub-pixel columns G1, R1, and B2 which are not adjacent and different in color.
Fig. 5 is a circuit diagram of a display substrate according to an embodiment. Only two fan-out leads Data1 and Data2 are illustrated in fig. 5, six sub-pixel columns R1, G1, B1, R2, G2, B2, R1 and R2 being red sub-pixel columns, G1, G2 being green sub-pixel columns, and B1 and B2 being blue sub-pixel columns. As shown in fig. 5, the display substrate provided in this embodiment includes: a first lighting test signal line CTD _ EVEN, a second lighting test signal line CTD _ ODD, a total control signal line CTSW, a first sub-control signal line CTSWR, a second sub-control signal line CTSWG, a third sub-control signal line CTSWB, a fourth sub-control signal line MUXR, a fifth sub-control signal line MUXG, and a sixth sub-control signal line MUXB, thin film transistors T11 to T16, T21 to T26, and T31 to T36, wherein,
the gates of the seventh to twelfth thin film transistors T21 to T26 are electrically connected to the total control signal line CTSW, the first poles of the seventh to eleventh thin film transistors T21, T23, T25 are electrically connected to the second lighting test signal line CTD _ ODD, the first poles of the eighth to twelfth thin film transistors T22, T24, T26 are electrically connected to the first lighting test signal line CTD _ EVEN, the second poles of the thin film transistors T21 to T26 are electrically connected to the first poles of the corresponding thin film transistors T11 to T16, respectively, wherein the seventh thin film transistor T21 corresponds to the first thin film transistor T11, the eighth thin film transistor T22 corresponds to the second thin film transistor T12, the ninth thin film transistor T23 corresponds to the third thin film transistor 46t 45, the tenth thin film transistor T24 corresponds to the fourth thin film transistor T365, the eleventh thin film transistor T25 corresponds to the fifth thin film transistor T57323, the twelfth thin film transistor T26 corresponds to the sixth thin film transistor T16;
the control electrodes of the first thin film transistor T11 and the fourth thin film transistor T14 are electrically connected to the first sub-control signal line CTSWR, and the second electrode of the first thin film transistor T11 is electrically connected to the data line corresponding to the sub-pixel column R1; a second pole of the fourth thin film transistor T14 is electrically connected to the data line corresponding to the sub-pixel column R2;
the control electrodes of the second thin film transistor T12 and the fifth thin film transistor T15 are electrically connected to the second sub-control signal line CTSWG, and the second electrode of the second thin film transistor T12 is electrically connected to the data line corresponding to the sub-pixel column G1; a second pole of the fifth thin film transistor T15 is electrically connected to the data line corresponding to the sub-pixel column G2;
the control electrodes of the third thin film transistor T13 and the sixth thin film transistor T16 are electrically connected to the third sub-control signal line CTSWB, and the second electrode of the third thin film transistor T13 is electrically connected to the data line corresponding to the sub-pixel column B1; a second pole of the sixth thin film transistor T16 is electrically connected to the data line corresponding to the sub-pixel column B2;
the second poles of the thin film transistors T31, T33 and T35 are electrically connected with a fan-out lead wire Data1, and the second poles of the thin film transistors T32, T34 and T36 are electrically connected with a fan-out lead wire Data 2;
the control electrodes of the thirteenth thin film transistor T31 and the sixteenth thin film transistor T34 are electrically connected to the fourth sub-control signal line MUXR, and the first electrode of the thirteenth thin film transistor T31 is electrically connected to the data line corresponding to the sub-pixel column R1; the first pole of the sixteenth thin film transistor T34 is electrically connected to the data line corresponding to the sub-pixel column R2;
the control electrodes of the fourteenth thin film transistor T32 and the seventeenth thin film transistor T35 are electrically connected to the fifth sub-control signal line MUXG, and the first electrode of the fourteenth thin film transistor T32 is electrically connected to the data line corresponding to the sub-pixel column G1; the first pole of the seventeenth thin film transistor T35 is electrically connected to the data line corresponding to the sub-pixel column G2;
the control electrodes of the fifteenth thin film transistor T33 and the eighteenth thin film transistor T36 are electrically connected to the 2 nd sub-control signal line MUXB, and the first electrode of the fifteenth thin film transistor T33 is electrically connected to the data line corresponding to the sub-pixel column B1; the eighteenth thin film transistor T36 has a first electrode electrically connected to the data line corresponding to the sub-pixel column B2.
Fig. 6 is a timing chart illustrating a lighting test of the display substrate shown in fig. 5. In this embodiment, the thin film transistor is turned on by applying a high level signal, but the invention is not limited thereto. The timing signals to be applied to the overall control signal line CTSW are omitted in fig. 6. As shown in fig. 6, STV is a start signal, CKB is a clock signal, CTD _ EVEN (r) is a signal applied to the first lighting test signal line CTD _ EVEN, and CTD _ dd (r) is a signal applied to the second lighting test signal line CTD _ ODD. FIG. 6 shows timing signals applied when displaying a gray-scale screen. The timing signal for performing detection of a monochrome picture or other pictures is not shown.
In this embodiment, when performing gray scale image detection, a high level signal is loaded on the total control signal line CTSW, the thin film transistors T21 to T26 are turned on, voltage signals having the same magnitude and opposite polarities are loaded on the first lighting test signal line CTD _ EVEN and the second lighting test signal line CTD _ ODD, and the polarities of each frame are switched, a high level signal is loaded on the fourth sub-control signal line MUXR, the fifth sub-control signal line MUXG, and the sixth sub-control signal line MUXB, the thin film transistors T31 to T36 are turned on, the driving signals shown in fig. 6 are loaded on the first sub-control signal line CTSWR, the second sub-control signal line CTSWG, and the third sub-control signal line CTSWB, and sub-pixel rows of different colors are sequentially turned on, so that the display substrate displays gray scale images.
When detecting a monochrome picture, for example, when detecting a red picture, the second sub-control signal line CTSWG and the third sub-control signal line CTSWB may be loaded with low-level signals, and the green sub-pixel column and the blue sub-pixel column may be turned off.
Fig. 7 is a schematic plan view of a display substrate according to an exemplary embodiment. The total control signal line CTSW and the thin film transistor electrically connected to the total control signal line CTSW are not illustrated in fig. 7. As shown in fig. 7, the first sub-control signal line CTSWR, the second sub-control signal line CTSWG, the third sub-control signal line CTSWB, the second lighting test signal line CTD _ ODD, and the first lighting test signal line CTD _ EVEN are disposed on the first side of the display area, and are sequentially arranged from the direction close to the display area to the direction away from the display area, and the fourth sub-control signal line MUXR, the fifth sub-control signal line MUXG, and the sixth sub-control signal line MUXB are disposed on the second side of the display area, and are sequentially arranged from the direction away from the display area to the direction close to the display area. When the lighting test is performed, the first lighting test signal applied to the sub-pixel columns R1, B1, and G2 is a positive voltage signal, the second lighting test signal applied to the sub-pixel columns G1, R2, and B2 is a negative voltage signal, the fan-out lead 311 and the fan-out lead 312 are shorted, the fan-out lead 311 is electrically connected to the sub-pixel columns R1, B1, and G2, the fan-out lead 312 is electrically connected to the sub-pixel columns G1, R2, and B2, after the two are shorted, the positive voltage signals applied to the sub-pixel columns R1, B1, and G2 and the negative voltage signals applied to the sub-pixel columns G1, R2, and B2 cancel each other, and the sub-pixel columns appear R1, B1, G2, G1, R2, and B2 and appear as shown in fig. 8. The scheme provided by the embodiment can effectively intercept the bad fan-out lead and avoid the waste of rear-end module materials. The present embodiment is described by taking a short circuit between two adjacent fan-out leads as an example. Similarly, when there are more fan-out lead shorts, no further description is given.
The embodiment of the disclosure also provides a display device, which includes the display substrate of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
Fig. 9 is a flowchart of a detection method provided in the embodiment of the present disclosure. As shown in fig. 9, an embodiment of the present disclosure provides a detection method applied to the display substrate, where the detection method includes:
step 901, loading a conduction control signal to the data control end, and conducting the fan-out lead and the data line;
and 902, loading a lighting test signal to the lighting test signal end, and sequentially conducting the lighting test signal end and the data line to enable the display substrate to display a gray scale picture.
According to the scheme provided by the embodiment, the fan-out lead and the data line are conducted during lighting test, when the adjacent fan-out lead is in short circuit, the adjacent data line is in short circuit, and the display pictures of the display substrate are different, so that the short circuit failure of the fan-out lead can be detected.
In an exemplary embodiment, the lighting test signal terminal includes a first lighting test signal terminal and a second lighting test signal terminal, and the loading the lighting test signal to the lighting test signal terminal includes: and respectively loading lighting test signals with the same magnitude and opposite polarities to the first lighting test signal end and the second lighting test signal end. According to the scheme provided by the embodiment, when the adjacent fan-out leads are in short circuit, the adjacent data lines are in short circuit, when the adjacent data lines respectively load the signals of the first lighting test signal end and the second lighting test signal end, the signals are mutually offset due to the same size and opposite polarities, the sub-pixel columns electrically connected with the fan-out leads in short circuit generate dark lines, and the short circuit failure of the fan-out leads can be conveniently detected.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A display substrate is characterized by comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a lighting test unit arranged on a first side of the display area, a multi-path selection unit arranged on a second side of the display area, and a fan-shaped area arranged on one side, far away from the display area, of the multi-path selection unit, the fan-shaped area comprises a plurality of fan-out leads, the first side and the second side are opposite, and the display area comprises a plurality of sub-pixel columns and a plurality of data lines in one-to-one correspondence with the sub-pixel columns;
the lighting test unit is electrically connected with a plurality of test control ends, a lighting test signal end and the data line and is configured to provide a lighting test signal of the lighting test signal end to the data line under the control of the test control ends;
the multiplexing unit is electrically connected with a plurality of data control terminals, fan-out leads and the data lines, and is configured to provide signals of the fan-out leads to the data lines under the control of the data control terminals, and provide signals of one fan-out lead to the data lines corresponding to at least two sub-pixel columns.
2. The display substrate according to claim 1, wherein the lighting test signal terminals include a first lighting test signal terminal and a second lighting test signal terminal, the lighting test unit includes a first lighting test signal line electrically connected to the first lighting test signal terminal, a second lighting test signal line electrically connected to the second lighting test signal terminal, first switch units corresponding to the sub-pixel rows one by one, a plurality of first control signal lines electrically connected to the plurality of test control terminals, respectively, the first switch units electrically connected to the first lighting test signal line or the second lighting test signal line, and one first control signal line, wherein,
the first switch unit is configured to supply a signal of the first lighting test signal line or the second lighting test signal line to a data line under control of the first control signal line, and a signal of the first lighting test signal line is supplied to a data line corresponding to an even column of sub-pixel columns, and a signal of the second lighting test signal line is supplied to a data line corresponding to an odd column of sub-pixel columns.
3. The display substrate according to claim 2, wherein the data lines to which the same fan-out lead is electrically connected are electrically connected to the same lighting test signal line, and the data lines to which the adjacent fan-out leads are electrically connected to different lighting test signal lines.
4. The display substrate of claim 2, wherein the sub-pixel columns comprise a first color sub-pixel column, a second color sub-pixel column, and a third color sub-pixel column, the plurality of first control signal lines comprise a first sub-control signal line, a second sub-control signal line, and a third sub-control signal line, the first sub-control signal line controls the first switching unit connected to the data line of the first color sub-pixel column, the second control sub-control signal line controls the first switching unit connected to the data line of the second color sub-pixel column, and the third sub-control signal line controls the first switching unit connected to the data line of the third color sub-pixel column.
5. The display substrate according to claim 2, wherein the lighting test unit further includes a second switch unit corresponding to the first switch unit one to one, and a total control signal line, the second switch unit being electrically connected to the first lighting test signal line or the second lighting test signal line, wherein:
the second switch unit is configured to supply a signal of the first lighting test signal line or the second lighting test signal line to the first switch unit under control of the total control signal line.
6. The display substrate according to any one of claims 1 to 5, wherein the multiplexing unit comprises: the third switch unit is in one-to-one correspondence with the sub-pixel rows, and a plurality of second control signal lines are respectively and electrically connected with the plurality of data control ends, the third switch unit is electrically connected with one fan-out lead and one second control signal line, wherein:
the third switching unit is configured to supply a signal of the fan-out lead to a data line under the control of the second control signal line.
7. The display substrate according to claim 6, wherein the sub-pixel columns include a first color sub-pixel column, a second color sub-pixel column, and a third color sub-pixel column, the plurality of second control signal lines include a fourth sub-control signal line, a fifth sub-control signal line, and a sixth sub-control signal line, the fourth sub-control signal line controls the third switching unit connected to the data line of the first color sub-pixel column, the fifth control signal line controls the third switching unit connected to the data line of the second color sub-pixel column, the sixth sub-control signal line controls the third switching unit connected to the data line of the third color sub-pixel column, and a signal of one fan-out lead is supplied to the data line corresponding to three sub-pixel columns which are not adjacent and are different colors.
8. A display device comprising the display substrate according to any one of claims 1 to 7.
9. A method of inspection applied to the display substrate of any one of claims 1 to 7, the method comprising:
loading a conduction control signal to the data control end to conduct the fan-out lead and the data line;
and loading a lighting test signal to the lighting test signal end, and sequentially conducting the lighting test signal end and the data line to enable the display substrate to display a gray scale picture.
10. The method according to claim 9, wherein the lighting test signal terminals include a first lighting test signal terminal and a second lighting test signal terminal, and the loading the lighting test signal to the lighting test signal terminals includes: and respectively loading lighting test signals with the same magnitude and opposite polarities to the first lighting test signal end and the second lighting test signal end.
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