CN113109856A - CT detector dynamic sampling method and system based on time division multiplexing technology and computer readable storage medium - Google Patents
CT detector dynamic sampling method and system based on time division multiplexing technology and computer readable storage medium Download PDFInfo
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- CN113109856A CN113109856A CN202110368180.9A CN202110368180A CN113109856A CN 113109856 A CN113109856 A CN 113109856A CN 202110368180 A CN202110368180 A CN 202110368180A CN 113109856 A CN113109856 A CN 113109856A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/20—Measuring radiation intensity with scintillation detectors
- G01T1/202—Measuring radiation intensity with scintillation detectors the detector being a crystal
- G01T1/2026—Well-type detectors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/20—Measuring radiation intensity with scintillation detectors
- G01T1/208—Circuits specially adapted for scintillation detectors, e.g. for the photo-multiplier section
Abstract
The invention provides a CT detector dynamic sampling method, a system and a computer readable storage medium based on time division multiplexing technology, the integrating circuit module is added between the detector crystal and the ADC chip, a plurality of pixel channels are connected to a processing channel of the ADC chip, two pixel channels are controlled by a circuit in the middle to realize integration of an analog signal and output the analog signal integrated in the previous period at the same time, dynamic continuous integration output is realized, and then high-speed real-time switching of a plurality of integrated signals is realized by the analog signal selection module, when the CT device scans, the data can be transmitted to the rear end FPGA module only through one ADC channel by dynamically switching the data acquisition among a plurality of pixels, the number of ADC chips can be reduced to at least half of that of the prior art, cost is effectively reduced, and space of a sampling system of CT equipment is saved.
Description
Technical Field
The invention relates to the technical field of electronic computer tomography display equipment, in particular to a CT detector dynamic sampling method and system based on time division multiplexing technology and a computer readable storage medium.
Background
The CT detector is a core component of a CT system, and the core of a CT detector module mainly comprises a crystal, a photodiode module (PD), an ADC chip and the like. The crystal is used for converting received X-rays into visible light, then converting the visible light into analog electric signals through a Photodiode (PD), and an ADC (analog-to-digital converter) is designed on a substrate to convert the analog electric signals transmitted by the photodiode into digital electric signals and finally transmit the digital electric signals to a back-end digital circuit.
In a conventional CT detector module, a fixed mode is adopted between an ADC chip and a crystal in a data acquisition process, that is, each time data is acquired, one channel of the ADC is fixed to correspond to a pixel or a plurality of pixels in a crystal array. This means that the number of channels of the ADC chip must be matched to the number of crystal arrays when scanning for the thinnest layer. When the size of a detector module is small, the number of pixels is large, and the size of the pixels is small, the layout of a detector substrate is difficult, the power consumption is increased, and the design difficulty is increased; the ADC chip is high in price, the price is higher when the number of channels is larger, and the cost of the detector module is increased.
Disclosure of Invention
In order to overcome the above technical defects, an object of the present invention is to provide a time division multiplexing-based dynamic sampling method, system and computer readable storage medium for a CT detector, wherein one processing channel of an ADC chip can correspondingly process a plurality of crystal array pixels.
The invention discloses a CT detector dynamic sampling system based on time division multiplexing technology, which comprises an integrating circuit module, an analog-to-digital conversion chip and an FPGA module; in a sampling period, the FPGA module controls the integration circuit module to integrate analog electric signals of a plurality of detector pixel points simultaneously; controlling the integration circuit module to output the analog electric signals of the plurality of detector pixel points after integration in the last sampling period;
the FPGA module controls the analog signal selection module to select one of the integrated analog electric signals of the plurality of detector pixel points, and transmits the selected one to the analog-to-digital conversion chip to convert the selected one into a digital signal and output the digital signal; and the FPGA module controls the analog signal selection module and the analog-to-digital conversion chip to continuously select and convert the integrated analog electrical signals of the plurality of detector pixel points until the analog electrical signals of all the detector pixel points of the analog electrical signals of the plurality of detector pixel points are converted into digital signals.
Preferably, the integrating circuit module comprises a plurality of integrating circuit units, and the number of the plurality of integrating circuit units is consistent with the number of the plurality of detector pixel points; the integration circuit unit comprises a first integration capacitor, a second integration capacitor, a first switch, a second switch, a third switch and a fourth switch, wherein the front end of the first integration capacitor is connected with the first switch, the rear end of the first integration capacitor is connected with the second switch, the front end of the second integration capacitor is connected with the third switch, and the rear end of the second integration capacitor is connected with the fourth switch; the first switch and the third switch are connected with the input end of an analog signal to be integrated, and the second switch and the fourth switch are connected with the output end of the integrated analog signal; closing the first switch or the third switch to integrate an analog signal, and closing the second switch or the fourth switch to output the integrated analog signal;
and simultaneously closing the first switch, the second switch, the third switch and the fourth switch of the plurality of integration circuit units, or opening the first switch, closing the second switch, closing the third switch and opening the fourth switch, so that the analog electric signals which are being integrated are not output when the analog electric signals of the plurality of detector pixel points are integrated, and the integration of the analog electric signals of the plurality of detector pixel points in the last sampling period is stopped.
Preferably, the first integrating capacitor and the second integrating capacitor have different integration parameters; and the analog electric signals of the plurality of detector pixel points which are integrated at the same time are integrated through the same integration capacitor.
Preferably, the number of the integration circuit units included in the integration circuit module is a multiple of 2.
The invention also discloses a CT detector dynamic sampling method based on time division multiplexing technology, which comprises the following steps in a sampling period: integrating the analog electric signals of a plurality of detector pixel points at the same time, and outputting the integrated analog electric signals of the plurality of detector pixel points in the last sampling period; selecting one of the integrated analog electric signals of the plurality of detector pixel points, converting the selected analog electric signal into a digital signal and outputting the digital signal; and continuously selecting and converting the integrated analog electric signals of the plurality of detector pixel points until the analog electric signals of all the detector pixel points of the analog electric signals of the plurality of detector pixel points are converted into digital signals.
Preferably, the simultaneously integrating the analog electrical signals of the plurality of detector pixel points and outputting the integrated analog electrical signals of the plurality of detector pixel points in the previous sampling period includes: and meanwhile, when the analog electric signals of the plurality of detector pixel points are integrated, the integrated analog electric signals are not output, and the integration of the analog electric signals of the plurality of detector pixel points in the previous sampling period is stopped.
Preferably, said simultaneously integrating the analog electrical signals of the plurality of detector pixels comprises: and simultaneously integrating the analog electric signals of the plurality of detector pixel points by adopting the same integration parameter.
Preferably, said simultaneously integrating the analog electrical signals of the plurality of detector pixels comprises: the number of the plurality of detector pixel points is a multiple of 2.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method for dynamic sampling of a CT detector.
After the technical scheme is adopted, compared with the prior art, the method has the following beneficial effects:
1. the invention adds the integrating circuit module between the detector crystal and the ADC chip, connects a plurality of pixel channels to the processing channel of the ADC chip, controls two pixel channels through a circuit to realize integration of analog signals and output the analog signals integrated in the previous period at the same time, realizes dynamic continuous integration output, and realizes high-speed real-time switching of a plurality of integration signals through the analog signal selection module, thereby realizing real-time switching of the positions of the acquired pixels in the data acquisition process of the analog signals, so that one processing channel of the ADC chip can correspondingly process a plurality of crystal array pixels, when CT equipment scans, the number can be transmitted to a rear-end FPGA module only through one ADC channel by dynamically switching the number among a plurality of pixels, and the number of the ADC chip can be reduced to at least half of the prior art, the cost is effectively reduced, and the space of a data acquisition system of the CT equipment is saved.
Drawings
FIG. 1 is a schematic diagram of a prior art data acquisition of a CT detector;
fig. 2 is a schematic structural diagram of a dynamic sampling system of a CT detector based on time division multiplexing technology provided by the present invention.
FIG. 3 is a flow chart of a dynamic sampling method for a CT detector based on time division multiplexing technology according to the present invention;
description of the drawings: the device comprises an integration circuit module 1, an analog signal selection module 2, an analog-to-digital conversion chip 3 and an FPGA module 4.
Detailed Description
The advantages of the invention are further illustrated in the following description of specific embodiments in conjunction with the accompanying drawings.
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, a communication between two elements, a direct connection, or an indirect connection via an intermediate medium, and specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in themselves. Thus, "module" and "component" may be used in a mixture.
Referring to fig. 1, a data acquisition architecture of a typical conventional energy integrating CT detector is shown. Taking 256 rows of CT detectors as an example, the detector has 221184(256 × 864) pixels, and each pixel corresponds to one analog signal processing channel of the ADC chip. 256 analog channels are provided in one ADC chip, and 864 ADC chips are required for this type of CT detector. The use amount of such a large number of chips has two major disadvantages in engineering implementation: firstly, the cost is very high; secondly, because the space of the CT detector is limited, a plurality of difficulties exist in the layout and wiring of the ADC chip on the circuit board.
The disadvantages of the prior art described above can be overcome by reducing the use of ADC chips. The work of the ADC chip in one sampling period is mainly divided into two parts: integration and conversion of the analog signal. The conversion takes a short time, so the invention can realize that the integration process is moved out of the chip and realized by a structure outside the ADC chip, and can finish multiple conversions in the original one-time sampling period, thereby realizing the requirement that the analog channel of one ADC corresponds to 2 or even more pixels, and further reducing the using number of the ADC chip.
Referring to fig. 2, the present invention discloses a dynamic sampling system of a CT detector based on time division multiplexing technology, which comprises:
an integrating circuit module 1 for integrating the analog signal converted from the X-ray to perform the subsequent conversion of the digital signal;
an analog signal selection module 2, configured to select a plurality of integrated analog signals, and select one of the integrated analog signals for analog-to-digital conversion;
an analog-to-digital conversion chip 3, configured to perform analog-to-digital conversion on the integrated analog signal, and convert the analog signal into a digital signal;
an FPGA module 4 for controlling the operation of the integrating circuit module 1 and the analog-to-digital conversion chip 3.
An X-ray corresponding to one pixel point is captured by the scintillation crystal and converted into visible light, and then the visible light is converted into an analog signal by the light emitting diode (PD). In a sampling period, the FPGA module 4 controls the integrating circuit module 1 to integrate the analog electrical signals of the plurality of pixel points of the plurality of detectors at the same time, and controls the integrating circuit module 1 to output the integrated analog electrical signals of the plurality of detector pixel points in the previous sampling period, so that the integrating process of the analog signal at the current moment and the outputting process of the analog signal at the previous moment after integration are simultaneously and continuously performed.
The FPGA module 4 controls the analog signal selection module 2 to select one of the integrated analog electric signals of the plurality of detector pixel points, and transmits the selected analog electric signal to the analog-to-digital conversion chip 3 to be converted into a digital signal and outputs the digital signal to the FPGA module 4.
The FPGA module 4 controls the analog signal selection module 2 and the analog-to-digital conversion chip 3 to continuously select and convert the integrated analog electrical signals of the plurality of detector pixel points in real time until the analog electrical signals of all the detector pixel points of the analog electrical signals of the plurality of detector pixel points are converted into digital signals, so that the integration process and the analog-to-digital conversion in the period are completed.
It should be noted that, because the conversion process takes a short time and the integration process takes a long time, the analog-to-digital conversion chip 3 can completely realize the analog-to-digital conversion of a plurality of analog signals of the previous period in the process of performing the integration of the analog signal of the current period by the integration circuit, and one period of the present invention is approximately equal to one period of the prior art. That is, the present invention achieves the purpose that one analog-to-digital conversion chip 3 can process a plurality of analog signals correspondingly within the duration of one period in the prior art, thereby reducing the use of the analog-to-digital conversion chip 3, reducing the cost, and reducing the difficulty of layout and wiring of the detector.
Preferably, the integrating circuit module 1 includes a plurality of integrating circuit units, the number of the plurality of integrating circuit units is equal to the number of the plurality of detector pixel points, and the analog signal corresponding to each pixel point is integrated by a corresponding integrating circuit unit.
Each integration circuit unit comprises two integration capacitors to realize an integration process that processes two cycles simultaneously. The front end and the rear end of each integrating capacitor are respectively provided with a switch, the switch at the front end of each integrating capacitor is closed to integrate the analog signal, the switch at the rear end of each integrating capacitor is closed to output the integrated analog signal, and the four switches used for controlling the two integrating capacitors are used for realizing the synchronous operation of the integrating process of the analog signal of the current period and the outputting process of the integrated analog signal of the previous period.
Simultaneously, a switch at the front end of one of the two integrating capacitors of the plurality of integrating circuit units is closed, and a switch at the rear end of the integrating capacitor is opened, so that the analog electric signals of the pixel points of the plurality of detectors are integrated without outputting the integrated analog electric signals; and the switch at the front end of the other integration capacitor is switched off, and the switch at the rear end is switched on, so that the analog electric signals of a plurality of detector pixel points in the last sampling period are stopped from being integrated.
Specifically, the integrating circuit unit comprises a first integrating capacitor (C1a, C2a), a second integrating capacitor (C1b, C2b), a first switch (SW1-1, SW2-1), a second switch (SW1-2, SW2-2), a third switch (SW1-3, SW2-3) and a fourth switch (SW1-4, SW2-4), wherein the front end of the first integrating capacitor (C1a, C2a) is connected with the first switch (SW1-1, SW2-1), the rear end of the first integrating capacitor (C1b, C2a) is connected with the second switch (SW1-2, SW2-2), the front end of the second integrating capacitor (C1b, C2 9) is connected with the third switch (SW1-3, SW2-3), and the rear end of the second integrating capacitor (SW 1b, SW 2) is connected with the fourth switch (SW1-4, SW 2-4). The first switch (SW1-1, SW2-1) and the third switch (SW1-3, SW2-3) are connected with the input end of the analog signal to be integrated, and the second switch (SW1-2, SW2-2) and the fourth switch (SW1-4, SW2-4) are connected with the output end of the integrated analog signal. The first switch (SW1-1, SW2-1) or the third switch (SW1-3, SW2-3) is closed to integrate the analog signal, and the second switch (SW1-2, SW2-2) or the fourth switch (SW1-4, SW2-4) is closed to output the integrated analog signal.
By reasonably switching the four switches, the integrated analog electrical signal is not output when the analog electrical signals of the detector pixel points are integrated, and the integration is stopped when the integrated analog electrical signals of the plurality of detector pixel points in the previous sampling period are output.
Specifically, the first switches (SW1-1 and SW2-1) of the integration circuit unit are closed, the second switches (SW1-2 and SW2-2) are opened, the third switches (SW1-3 and SW2-3) are opened, and the fourth switches (SW1-4 and SW2-4) are closed, so that the analog signals are integrated through the first integration capacitors (C1a and C2a), and the integrated analog signals are output through the second integration capacitors (C1b and C2 b). The method comprises the steps of opening first switches (SW1-1, SW2-1), closing second switches (SW1-2, SW2-2), closing third switches (SW1-3, SW2-3) and opening fourth switches (SW1-4, SW2-4) of an integrating circuit unit so as to integrate analog signals through second integrating capacitors (C1b, C2b) and output the analog signals integrated through the first integrating capacitors (C1a, C2 a).
The switching of the integration circuit unit is controlled by the FPGA module 4.
Preferably, the first integrating capacitor (C1a, C2a) and the second integrating capacitor (C1b, C2b) have different integration parameters, and the parameters of the analog signal integrated by the integrating capacitors with different parameters are different. In order to facilitate the selection work of the analog signal selection module 2, the analog electrical signals of the plurality of detector pixel points which are simultaneously integrated are integrated through the same integration capacitor, so that the integration parameters of the plurality of analog signals which are simultaneously integrated are consistent.
Preferably, the number of the integrating circuit units included in the integrating circuit module 1 is a multiple of 2, and preferably the number is 2 or 4, and the analog signals of 2 or 4 detector pixels can be processed simultaneously.
The invention also discloses a CT detector dynamic sampling method based on time division multiplexing technology, which comprises the following steps in a sampling period:
s1, integrating the analog electric signals of the plurality of detector pixel points simultaneously, and outputting the integrated analog electric signals of the plurality of detector pixel points in the last sampling period;
s2, selecting one of the integrated analog electric signals of the plurality of detector pixel points, converting the selected analog electric signal into a digital signal and outputting the digital signal;
and S3, continuously selecting and converting the integrated analog electric signals of the plurality of detector pixel points until the analog electric signals of all the detector pixel points of the analog electric signals of the plurality of detector pixel points are converted into digital signals.
Preferably, when the analog electrical signals of the plurality of detector pixel points are integrated at the same time, the integrated analog electrical signal is not output, and when the integrated analog electrical signals of the plurality of detector pixel points in the previous sampling period are output, the integration is stopped.
Preferably, the analog electrical signals of the plurality of detector pixels integrated at the same time are integrated by using the same integration parameter.
Preferably, the number of detector pixels is a multiple of 2, preferably 2 or 4.
A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned method for dynamic sampling of a CT detector.
It should be noted that the embodiments of the present invention have been described in terms of preferred embodiments, and not by way of limitation, and that those skilled in the art can make modifications and variations of the embodiments described above without departing from the spirit of the invention.
Claims (9)
1. A CT detector dynamic sampling system based on time division multiplexing technology is characterized by comprising an integrating circuit module, an analog-to-digital conversion chip and an FPGA module;
in a sampling period, the FPGA module controls the integration circuit module to integrate analog electric signals of a plurality of detector pixel points simultaneously; controlling the integration circuit module to output the analog electric signals of the plurality of detector pixel points after integration in the last sampling period;
the FPGA module controls the analog signal selection module to select one of the integrated analog electric signals of the plurality of detector pixel points, and transmits the selected one to the analog-to-digital conversion chip to convert the selected one into a digital signal and output the digital signal;
and the FPGA module controls the analog signal selection module and the analog-to-digital conversion chip to continuously select and convert the integrated analog electrical signals of the plurality of detector pixel points until the analog electrical signals of all the detector pixel points of the analog electrical signals of the plurality of detector pixel points are converted into digital signals.
2. The dynamic CT detector sampling system as claimed in claim 1, wherein the integrator circuit module comprises a plurality of integrator circuit units, and the number of the integrator circuit units is equal to the number of the detector pixel points;
the integration circuit unit comprises a first integration capacitor, a second integration capacitor, a first switch, a second switch, a third switch and a fourth switch, wherein the front end of the first integration capacitor is connected with the first switch, the rear end of the first integration capacitor is connected with the second switch, the front end of the second integration capacitor is connected with the third switch, and the rear end of the second integration capacitor is connected with the fourth switch; the first switch and the third switch are connected with the input end of an analog signal to be integrated, and the second switch and the fourth switch are connected with the output end of the integrated analog signal; closing the first switch or the third switch to integrate an analog signal, and closing the second switch or the fourth switch to output the integrated analog signal;
and simultaneously closing the first switch, the second switch, the third switch and the fourth switch of the plurality of integration circuit units, or opening the first switch, closing the second switch, closing the third switch and opening the fourth switch, so that the analog electric signals which are being integrated are not output when the analog electric signals of the plurality of detector pixel points are integrated, and the integration of the analog electric signals of the plurality of detector pixel points in the last sampling period is stopped.
3. The CT detector dynamic sampling system of claim 1, wherein the first integrating capacitance and the second integrating capacitance have different integration parameters;
and the analog electric signals of the plurality of detector pixel points which are integrated at the same time are integrated through the same integration capacitor.
4. The dynamic CT detector sampling system of claim 1, wherein the number of the integrator circuit units included in the integrator circuit module is a multiple of 2.
5. A CT detector dynamic sampling method based on time division multiplexing technology is characterized in that in a sampling period, the method comprises the following steps:
integrating the analog electric signals of a plurality of detector pixel points at the same time, and outputting the integrated analog electric signals of the plurality of detector pixel points in the last sampling period;
selecting one of the integrated analog electric signals of the plurality of detector pixel points, converting the selected analog electric signal into a digital signal and outputting the digital signal;
and continuously selecting and converting the integrated analog electric signals of the plurality of detector pixel points until the analog electric signals of all the detector pixel points of the analog electric signals of the plurality of detector pixel points are converted into digital signals.
6. The dynamic sampling method for the CT detector according to claim 5, wherein the simultaneously integrating the analog electrical signals of the plurality of detector pixels and outputting the integrated analog electrical signals of the plurality of detector pixels for the previous sampling period comprises:
and meanwhile, when the analog electric signals of the plurality of detector pixel points are integrated, the integrated analog electric signals are not output, and the integration of the analog electric signals of the plurality of detector pixel points in the previous sampling period is stopped.
7. The dynamic sampling method for the CT detector according to claim 5, wherein the simultaneously integrating the analog electrical signals of the plurality of detector pixels comprises:
and simultaneously integrating the analog electric signals of the plurality of detector pixel points by adopting the same integration parameter.
8. The dynamic sampling method for the CT detector according to claim 5, wherein the simultaneously integrating the analog electrical signals of the plurality of detector pixels comprises:
the number of the plurality of detector pixel points is a multiple of 2.
9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method for dynamic sampling of a CT detector according to any one of claims 5 to 8.
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| CN107613871A (en) * | 2015-08-24 | 2018-01-19 | 株式会社日立制作所 | Radiate line detector and medical imaging camera device |
| CN105720985A (en) * | 2016-01-18 | 2016-06-29 | 清华大学 | Variable compression ratio sampling circuit used for compression and sampling analog-to-digital converter |
| CN111614353A (en) * | 2019-02-26 | 2020-09-01 | 北京知存科技有限公司 | Digital-to-analog conversion circuit and analog-to-digital conversion circuit multiplexing device in storage and calculation integrated chip |
| CN111817717A (en) * | 2020-06-12 | 2020-10-23 | 中国科学院上海微系统与信息技术研究所 | Multichannel data reading circuit |
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