CN108200357A - Video signal processing system based on multiple DSP processors - Google Patents
Video signal processing system based on multiple DSP processors Download PDFInfo
- Publication number
- CN108200357A CN108200357A CN201810169845.1A CN201810169845A CN108200357A CN 108200357 A CN108200357 A CN 108200357A CN 201810169845 A CN201810169845 A CN 201810169845A CN 108200357 A CN108200357 A CN 108200357A
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- China
- Prior art keywords
- processor
- dsp
- dsp processor
- fpga
- signal processing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Processing (AREA)
Abstract
The invention discloses the video signal processing systems based on multiple dsp processors,Dsp processor unit and FPGA processor including interconnection,The FPGA processor is connected with digital signal circuit and analogue signal circuit,The FPGA processor connects analogue signal circuit by video separation chip,The analogue signal circuit is also associated with correcting circuit,The correcting circuit is connected with A/D conversion circuits,The FPGA processor is connect with A/D conversion circuits,The dsp processor unit is connected with PC machine,The PC machine is connect with FPGA processor,The present invention uses and the digital video data and analog video data of video data is acquired,PC machine is transmitted to by pci bus after the processing of multiple dsp processors,Whole system can be efficiently completed the identification of video object and tracking and at low cost,Autgmentability is strong.
Description
Technical field
The present invention relates to video image processing system fields, are the vision signals based on multiple dsp processors specifically
Processing system.
Background technology
Video image is that people obtain information and exchange the main source of information, and the main source as people's vision accounts for about
It has arrived and has obtained more than the 60% of information content, the related application of video processing also influences the every aspect of people's live and work；Number
Video processing technique is constantly improved, efficient video processing technique this earliest be applied to military commanding and control aspect
Technology, the combination for having become many traditional subjects and emerging engineering field is developed so far, with human lives' informationization
The continuous intensification of degree, video information increasingly embody its powerful packet as the carrier format for containing bulk information
Containing ability, what is thus caused is exactly the high request to video treatment effeciency, in practical application, the video data of system acquisition
It is frequently not perfect, can be usually interfered by the external world, image capturing system is the subdivision of processing system for video, is video
Other parts in processing system, which provide, adequately to be supported, can performance quality is directly related to subsequent processing correctly efficient,
The influence of the factors such as error, illumination of the video data in transmission process can all lead to the of low quality of video data, it is difficult into
Row deeper into research and processing, in recent years, great development has been obtained for the sensor of Image Acquisition, be image high score
Resolution, which is shown, provides possibility, meanwhile, with image processing techniques, fast-developing and perfect, all kinds of use of compression coding technology
It is also continuously emerged in the system of video processing.
In recent years, with computer and other each rapid developments in relation to field, such as in image appearance, multi-media processing
The development of technology etc., video processing have become one in scientific research and man-machine interface from a particular study field
Kind commonly used tool, and due to the video equipment in Communication Engineering or monitoring device need that target is identified and with
Track, some current video data processing systems only carry out analog video data when carrying out video data processing cannot be efficient
Completion data analysis and transmission and cost it is higher, can not ensure video equipment acquisition information normally handle display.
Invention content
The purpose of the present invention is to provide the video signal processing system based on multiple dsp processors, using to video counts
According to digital video data and analog video data be acquired, by multiple dsp processors processing after be transmitted to PC machine, entirely
System can be efficiently completed the identification of video object and tracking and at low cost, and autgmentability is strong.
The present invention is achieved through the following technical solutions：Based on the video signal processing system of multiple dsp processors, including phase
The dsp processor unit and FPGA processor to connect, the FPGA processor are connected with digital signal circuit, at the FPGA
It manages device and analogue signal circuit is connected by video separation chip, the analogue signal circuit is also associated with correcting circuit, the school
Positive circuit is connected with A/D conversion circuits, and the FPGA processor is connect with A/D conversion circuits, the dsp processor unit connection
There is PC machine, the PC machine is connect with FPGA processor.
Further is that the present invention is better achieved, especially using following setting structures：The dsp processor unit includes
The first dsp processor, the second dsp processor and the third dsp processor being connected with each other, second dsp processor are connected with
FLASH memory, the FLASH memory connect FPGA processor.
Further is that the present invention is better achieved, especially using following setting structures：The third dsp processor connection
There is dual port RAM, the dual port RAM connects PC machine by pci interface chip.
Further is that the present invention is better achieved, especially using following setting structures：The first dsp processor connection
There is the first SRAM, second dsp processor is connected with the 2nd SRAM, and the third dsp processor is connected with the 3rd SRAM.
Further is that the present invention is better achieved, especially using following setting structures：The pci interface chip connection
FPGA processor.
Further is that the present invention is better achieved, especially using following setting structures：First dsp processor,
Be both provided with link port in two dsp processors and third dsp processor, first dsp processor, the second dsp processor and
It is connected between third dsp processor by link port.
Further is that the present invention is better achieved, especially using following setting structures：The FPGA processor uses
EPC2LC20 chips, the A/D conversion circuits use AD9050 converters.
Compared with prior art, the present invention haing the following advantages and advantageous effect：
The present invention is acquired simultaneously by the analog signal to video data and digital signal, is controlled it by FPGA processor
Dsp processor unit is transmitted to after selection output mode to be further analyzed and handle, finally by pci bus in PC machine
Upper display can realize the high speed processing of video data, complete the target following in the real-time display and video of video, and work
It is relatively low to stablize cost.
Description of the drawings
Fig. 1 is the structural diagram of the present invention.
Specific embodiment
The embodiment of the present invention is described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function, below with reference to attached
The embodiment of figure description is exemplary, it is intended to for explaining the present invention, and is not considered as limiting the invention.
Embodiment 1：
As shown in Figure 1, the video signal processing system based on multiple dsp processors, the dsp processor unit including interconnection
And FPGA processor, the FPGA processor are connected with digital signal circuit, the FPGA processor passes through video separation chip
Analogue signal circuit is connected, the analogue signal circuit is also associated with correcting circuit, and the correcting circuit is connected with A/D conversion electricity
Road, the FPGA processor are connect with A/D conversion circuits, and the dsp processor unit is connected with PC machine, the PC machine and FPGA
Processor connects, and entire video signal processing system is completed right to the acquisition of head end video data by video signal collection module
Afterwards by pci bus module transfer to PC machine after DSP video processing modules carry out video processing, so as to fulfill video object
Identification and the signal processing of tracking, and analog video data and digital video data are carried out at the same time in video data acquiring and adopted
Collection, analog video signal is transmitted to correcting circuit by analogue signal circuit, is corrected and enhanced processing, and analog video is believed
It number is transmitted to A/D conversion circuits and does A/D conversion process, complete vision signal after being latched again by FPGA processor after A/D conversions
The second dsp processor is sent to, the synchronizing signal for the analog video isolated by video separation chip feeds back to FPGA processing
Device, for controlling the acquisition of video data that the processing of video image is rapidly completed to the second dsp processor.
Embodiment 2：
The present embodiment is further optimized based on the above embodiments, as shown in Figure 1, further for this is better achieved
Invention, especially using following setting structures：The dsp processor unit includes the first dsp processor being connected with each other, second
Dsp processor and third dsp processor, second dsp processor are connected with FLASH memory, and the FLASH memory connects
Connect FPGA processor；The vision signal transmitted into FPGA processor is exported by selection to the data/address bus of the second dsp processor
In, it is read in by the second dsp processor, data rate and analog signal rate and data signal rate all same；Dsp processor
The second dsp processor is for arranging collected vision signal in unit, and is pre-processed accordingly, then sends out data
It send to the first dsp processor and third dsp processor and is further processed, FLASH memory is used to complete at the 2nd DSP
The data loading of device is managed, vision signal is carried out by the data signal transmission that the second dsp processor arranges to the first dsp processor
It calculates.
Further is that the present invention is better achieved, especially using following setting structures：The third dsp processor connection
There is dual port RAM, the dual port RAM connects PC machine by pci interface chip, and third dsp processor receives the first dsp processor hair
After the data sent are further processed, the data finally handled are sent to dual port RAM, twoport passes through pci interface chip again
Send data to PC machine.
Further is that the present invention is better achieved, especially using following setting structures：The first dsp processor connection
There is the first SRAM, second dsp processor is connected with the 2nd SRAM, and the third dsp processor is connected with the 3rd SRAM, point
Not She Zhi SRAM memory with ensure the data of different processor store.
Further is that the present invention is better achieved, especially using following setting structures：The pci interface chip connection
FPGA processor, when carrying out data processing, working control switch accesses FPGA processor by pci interface chip.
Further is that the present invention is better achieved, especially using following setting structures：First dsp processor,
Be both provided with link port in two dsp processors and third dsp processor, first dsp processor, the second dsp processor and
It is connected between third dsp processor by link port.
Further is that the present invention is better achieved, especially using following setting structures：The FPGA processor uses
EPC2LC20 chips, the A/D conversion circuits use AD9050 converters, and AD9050 converters are 10 A/D converters, are adopted
The sampling clock of sample clock and digital video signal is 12MHz.
The above is only presently preferred embodiments of the present invention, not does limitation in any form to the present invention, it is every according to
According to the present invention technical spirit above example is made any simple modification, equivalent variations, each fall within the present invention protection
Within the scope of.
Claims (7)
1. the video signal processing system based on multiple dsp processors, it is characterised in that：Dsp processor including interconnection
Unit and FPGA processor, the FPGA processor are connected with digital signal circuit, and the FPGA processor passes through video separation
Chip connects analogue signal circuit, and the analogue signal circuit is also associated with correcting circuit, and the correcting circuit is connected with A/D and turns
Change circuit, the FPGA processor is connect with A/D conversion circuits, and the dsp processor unit is connected with PC machine, the PC machine with
FPGA processor connects.
2. the video signal processing system according to claim 1 based on multiple dsp processors, it is characterised in that：It is described
Dsp processor unit includes the first dsp processor, the second dsp processor and the third dsp processor that are connected with each other, and described the
Two dsp processors are connected with FLASH memory, and the FLASH memory connects FPGA processor.
3. the video signal processing system according to claim 2 based on multiple dsp processors, it is characterised in that：It is described
Third dsp processor is connected with dual port RAM, and the dual port RAM connects PC machine by pci interface chip.
4. the video signal processing system according to claim 2 based on multiple dsp processors, it is characterised in that：It is described
First dsp processor is connected with the first SRAM, and second dsp processor is connected with the 2nd SRAM, the third dsp processor
It is connected with the 3rd SRAM.
5. according to the arbitrary video signal processing systems based on multiple dsp processors of claim 1-4, feature exists
In：The pci interface chip connects FPGA processor.
6. according to the arbitrary video signal processing systems based on multiple dsp processors of claim 1-4, feature exists
In：Link port, the first DSP are both provided in first dsp processor, the second dsp processor and third dsp processor
It is connected between processor, the second dsp processor and third dsp processor by link port.
7. according to the arbitrary video signal processing systems based on multiple dsp processors of claim 1-4, feature exists
In：The FPGA processor uses EPC2LC20 chips, and the A/D conversion circuits use AD9050 converters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810169845.1A CN108200357A (en) | 2018-03-01 | 2018-03-01 | Video signal processing system based on multiple DSP processors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810169845.1A CN108200357A (en) | 2018-03-01 | 2018-03-01 | Video signal processing system based on multiple DSP processors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108200357A true CN108200357A (en) | 2018-06-22 |
Family
ID=62594302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810169845.1A Withdrawn CN108200357A (en) | 2018-03-01 | 2018-03-01 | Video signal processing system based on multiple DSP processors |
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| CN (1) | CN108200357A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109036263A (en) * | 2018-09-13 | 2018-12-18 | 天长市辉盛电子有限公司 | LED display image processing apparatus and its processing method |
-
2018
- 2018-03-01 CN CN201810169845.1A patent/CN108200357A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109036263A (en) * | 2018-09-13 | 2018-12-18 | 天长市辉盛电子有限公司 | LED display image processing apparatus and its processing method |
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Application publication date: 20180622 |