CN113098463A - Power gating circuit and storage chip - Google Patents
Power gating circuit and storage chip Download PDFInfo
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- CN113098463A CN113098463A CN202010021410.XA CN202010021410A CN113098463A CN 113098463 A CN113098463 A CN 113098463A CN 202010021410 A CN202010021410 A CN 202010021410A CN 113098463 A CN113098463 A CN 113098463A
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- power
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- gating circuit
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- gate switch
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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Abstract
The invention provides a power gating circuit and a storage chip, wherein the power gating circuit comprises: a power gate switch, the first end of which is connected with the power voltage and the second end of which is connected with the functional module; and the delay module is connected with the control end of the power supply brake switch, and a control signal is input to the control end of the power supply brake switch through the delay module so as to reduce the opening or closing speed of the power supply brake switch. The invention has the advantages that the rising rate and the falling rate of the signal of the control end of the power gate switch are reduced by the delay module, so that the opening and closing speed of the power gate switch can be delayed, and the effects of reducing the peak current and the peak voltage of the power voltage are achieved.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a power gate control circuit and a storage chip.
Background
In integrated circuit chips, how to reduce the power consumption of products has become a very important issue at present.
One method of reducing the power consumption of the circuit is to use a power gating circuit (power gating circuit). The power gating circuit can control the power supply condition of the power supply circuit to the functional circuit. The power gating circuit may couple various functional modules with a terminal to which a power voltage is applied to apply the power voltage to the various functional modules, and may cut off the coupling of the power voltage to the functional modules, thereby reducing overall power consumption.
Disclosure of Invention
The invention provides a power gating circuit and a memory chip.
In order to solve the above problem, the present invention provides a power gating circuit, which includes: a power gate switch, the first end of which is connected with the power voltage and the second end of which is connected with the functional module; and the delay module is connected with the control end of the power supply brake switch, and a control signal is input to the control end of the power supply brake switch through the delay module so as to reduce the opening or closing speed of the power supply brake switch.
Furthermore, the delay module comprises a resistor and a capacitor, wherein the first end of the resistor is connected with the control signal, the second end of the resistor is connected with the first end of the capacitor, the second end of the capacitor is grounded, and the control end of the power gate switch is connected with the first end of the capacitor.
Further, the resistor is selected from one or a combination of polycrystalline resistor, metal resistor or doped resistor.
Further, the capacitor is selected from one or a combination of a MOS capacitor, a PIP capacitor, a MIM capacitor or a MOM capacitor.
Furthermore, the power gate control circuit further comprises a buffer module, and the control signal is sequentially input to the control end of the power gate switch through the buffer module and the delay module.
Further, the buffer module is formed by connecting an even number or an odd number of inverters in series.
Further, the delay module comprises a phase inverter, a first current source, a second current source and a capacitor, the first current source is connected with the first end of the phase inverter, the second current source is connected with the second end of the phase inverter, the control signal is input to the input end of the phase inverter, the output end of the phase inverter is connected to the control end of the power gate switch, the first end of the capacitor is connected to the control end of the power gate switch, and the second end of the capacitor is grounded.
Further, the first current source is a PMOS current source, and the second current source is an NMOS current source.
Furthermore, the power gate switch is a PMOS tube or an NMOS tube.
Further, the power supply voltage is a power supply potential or a ground potential.
Further, the functional module is one or a combination of a digital module and an analog module.
The invention also provides a memory chip which comprises the power gating circuit.
Further, in a sleep mode of the memory chip, the power gate switch of the voltage gate control circuit is turned off.
The invention has the advantages that the rising rate and the falling rate of the signal of the control end of the power gate switch are reduced by the delay module, so that the opening and closing speed of the power gate switch can be delayed, and the effects of reducing the peak current and the peak voltage of the power voltage are achieved.
Drawings
FIG. 1A is a schematic diagram of a conventional power gating circuit;
FIG. 1B is a schematic diagram of the generation of spike currents at an input power source and ground potential;
FIG. 1C is a schematic diagram of the generation of spike voltages on the input power supply and ground potential;
FIG. 2 is a schematic diagram of a first embodiment of the power gating circuit according to the present invention;
FIG. 3 is a timing diagram of the control terminal of the power gate switch according to the present invention;
FIG. 4 is a schematic diagram of a second embodiment of the power gating circuit according to the present invention;
fig. 5 is a timing diagram of the control terminal of the power gate switch according to the present invention.
Detailed Description
The following describes in detail embodiments of the power gating circuit and the memory chip according to the present invention with reference to the accompanying drawings.
Fig. 1A is a schematic diagram of an application of a conventional power gating circuit, please refer to fig. 1A, in which a control signal Sleep controls a transmission module 11 to be turned on and off to realize a control function. A large-sized PMOS transistor may be disposed in the transmission module 11 to implement a switching function. When the control signal is at a low level, the transmission module 11 is turned on to supply power to the functional module; when the control signal is at a high level, the transmission module 11 is turned off, the functional module does not work, and power consumption is saved.
The conventional power gating circuit has the disadvantage that a parasitic resistor R and a parasitic inductor L exist between the power chip PIN VDD PIN and the chip PAD VDD PAD, and when the functional module 10 is switched from the sleep state to the normal operation state, i.e., the transmission module 11 is rapidly switched between the high impedance state and the low impedance state, the initial voltage at the input terminal of the functional module 10 is low, which results in large spike currents at the input power supply and the ground potential (fig. 1B is a schematic diagram of spike currents at the input power supply and the ground potential), the divided voltage of the parasitic resistor R and the parasitic inductor L may cause a voltage drop on the PAD VDD PAD of the chip, resulting in a large spike voltage (fig. 1C is a schematic diagram of the spike voltage generated on the input power source and the ground), which may affect the timing of other functional modules powered by the input power source and the ground. Similarly, when the functional module 10 is switched from the normal operating state to the sleep state, the current on the input power supply and the ground potential decreases instantaneously, which may also cause the voltage on the PAD VDD PAD of the chip to fluctuate, and may also affect the timing of other functional modules powered by the input power supply and the ground potential.
In addition, in the prior art, for the normal operation of the functional module 10, when the functional module 10 is switched from the sleep mode to the normal operation mode, the potential at the input terminal of the functional module 10 is increased to increase the response speed of the functional module 10, so that the functional module 10 can be quickly switched from the sleep mode to the normal operation mode, and the operation inevitably generates the spike voltage.
In view of the above, the present invention provides a new power gating circuit, which can avoid generating large peak current on the input power and the ground potential, and further avoid generating large peak voltage on the input power and the ground potential, so as not to affect the timing of other functional modules powered by the input power and the ground potential. The functional module 10 is one or a combination of a digital module and an analog module.
Fig. 2 is a schematic diagram of a first embodiment of the power gating circuit according to the present invention, referring to fig. 2, the power gating circuit includes a power gate switch M1 and a delay module 20.
The power gate switch M1 has a first terminal, a second terminal and a control terminal. The first end is connected with a power supply voltage VDD, the second end is connected with the functional module 10, and the control end is used for accessing a control signal Sleep. The functional module 10 is connected with a power supply through the power supply gate control circuit.
In this embodiment, the power gate switch M1 is a PMOS transistor, and the power voltage VDD is a power potential. The source end of the PMOS tube is a first end and is connected with a power supply voltage VDD; the drain end of the PMOS transistor is a second end, and is connected with the functional module 10; the grid end of the PMOS tube is a control end and is used for inputting a control signal Sleep. In another embodiment of the present invention, the power gate switch M1 is an NMOS transistor, and the power voltage VDD is a ground potential.
The delay module 20 is connected to a control terminal of the power gate switch M1, and a control signal Sleep is input to the control terminal of the power gate switch M1 through the delay module 20 to reduce the speed of turning on or off the power gate switch M1.
Specifically, in the present embodiment, the delay module 20 is an RC circuit, which includes a resistor R and a capacitor C. The first end of the resistor R is connected with a control signal Sleep, the second end of the resistor R is connected with the first end of the capacitor C, the second end of the capacitor C is grounded, and the control end of the power gate switch M1 is connected with the first end of the capacitor C.
Fig. 3 is a timing diagram of the control terminal of the power gate switch M1. Referring to fig. 2 and 3, when the control signal Sleep is at a high level, at the control terminal of the power gate switch M1 (e.g., point a in the figure), first, the capacitor C needs to be charged, which slows down the rising speed of the voltage at point a, so that the rising speed of the signal VG at the control terminal of the power gate switch M1 changes from a low level to a high level, and when the voltage at point a rises to reach the turn-off voltage of the power gate switch M1, the power gate switch M1 is turned off; when the control signal Sleep is low, the capacitor C discharges at the control terminal of the power gate switch M1 (shown as point a in the figure), which slows down the voltage drop at point a, so that the falling rate of the signal VG at the control terminal of the power gate switch M1 changes from high to low, and the power gate switch M1 turns on when the voltage drop at point a reaches the turn-on voltage of the power gate switch M1.
In this embodiment, the delay function of the delay module 20 is utilized to reduce the rising rate and the falling rate of the signal VG at the control terminal of the power gate switch M1, so as to delay the on/off speed of the power gate switch M1, thereby achieving the effects of reducing the peak current and the peak voltage of the power voltage, and avoiding affecting the timing of other functional modules (e.g., the functional module 30) powered by the input power and the ground potential.
Further, the resistor R is selected from one or a combination of a polycrystalline resistor, a metal resistor or a doped resistor, and the capacitor C is selected from one or a combination of a MOS capacitor, a PIP capacitor, an MIM capacitor or an MOM capacitor. The sizes of the resistor R and the capacitor C can be set according to the peak voltage which can be tolerated by the power supply gating circuit, and the product of the resistor R and the capacitor C can meet the requirement.
Further, in this embodiment, the power gating circuit further includes a buffer module 21. The control signal Sleep is sequentially input to the control end of the power gate switch M1 through the buffer module 21 and the delay module 20. The buffer module 21 may be formed by connecting an even number of inverters in series. For example, as shown in fig. 2, the buffer module 21 is formed by connecting two inverters in series.
The invention also provides a second embodiment of the power gating circuit. The second embodiment differs from the first embodiment in the structure of the delay module 20 of the power gating circuit. In the first embodiment, the delay module 20 is an RC circuit, which uses the delay effect of the RC circuit to reduce the rising and falling rates of the signal VG at the control terminal of the power gate switch M1; in the second embodiment, the delay module 20 controls the charging/discharging speed of the control terminal of the power gate switch M1 to reduce the rising and falling rate of the signal VG at the control terminal of the power gate switch M1.
Specifically, fig. 4 is an application diagram of a power gating circuit according to a second embodiment of the present invention, and referring to fig. 4, in the second embodiment, the delay module 20 includes an inverter a1, a first current source I1, a second current source I2, and a capacitor C.
The control signal Sleep is input to an input end of the inverter A1, and an output end of the inverter A1 is connected to a control end of the power gate switch M1.
The first current source I1 is connected with a first terminal of the inverter A1. Namely, the first current source I1 is connected to the PMOS transistor of the inverter a 1. When the PMOS transistor is turned on, the first current source I1 is connected to the control terminal of the power gate switch M1, so as to charge the power gate switch. In this embodiment, the first current source I1 is a PMOS current source.
The second current source I2 is connected to the second terminal of the inverter a 1. I.e. the second current source I2 is connected to the NMOS terminal of the inverter a 1. When the NMOS transistor is turned on, the second current source I2 is connected to the control terminal of the power gate switch M1, discharging it. In this embodiment, the second current source I2 is an NMOS current source.
The first terminal of the capacitor C is connected to the control terminal of the power gate switch M1, and the second terminal of the capacitor C is grounded. In this embodiment, the first current source I1 and the second current source I2 control the magnitude of the current for charging and discharging the control terminal of the power gate switch M1, and the capacitor C controls the amount of electricity for charging and discharging the control terminal of the power gate switch M1.
Further, in this embodiment, the power gating circuit further includes a buffer module 21. The control signal Sleep is sequentially input to the control end of the power gate switch M1 through the buffer module 21 and the delay module 20. The buffering module 21 may be formed by connecting odd inverters in series. For example, as shown in fig. 4, the buffer module 21 is formed by an inverter.
Fig. 5 is a timing diagram of the control terminal of the power gate switch M1. Please refer to fig. 4 and 5:
when the control signal Sleep is at a high level, after passing through the buffer module 21, the control signal changes to a low level and is input to the input terminal of the inverter a1, the PMOS transistor of the inverter a1 is turned on, the output terminal of the inverter a1 outputs a high level, the signal VG at the control terminal of the power gate switch M1 (equivalent to point a in the figure) changes from a low level to a high level, the PMOS transistor is turned on, the first current source I1 is connected to the control terminal of the power gate switch M1, the first current source I1 charges the control terminal of the power gate switch M1, the first current source I1 controls the charging current, the capacitor C controls the charging amount, and the rate of the signal VG at the control terminal of the power gate switch M1 changing from a low level to a high level is slowed down, that is, the rising rate of the signal VG at the control terminal of the power gate switch M1 changes from a low level to a high level, when the voltage of the control terminal of the power gate switch M1 rises to reach the turn-off voltage of the power gate switch M1, the power gate switch M1 is turned off.
When the control signal Sleep is at a low level, after passing through the buffer module 21, the control signal changes to a high level and is input to the input terminal of the inverter a1, the NMOS transistor of the inverter a1 is turned on, the output terminal of the inverter a1 outputs a low level, the signal VG at the control terminal of the power gate switch M1 changes from the high level to the low level, because the NMOS transistor is turned on, the second current source I2 is connected to the control terminal of the power gate switch M1, the second current source I2 discharges the control terminal of the power gate switch M1, the second current source I2 controls a discharging current, the capacitor C controls a discharging electric quantity, a rate of the signal VG at the control terminal of the power gate switch M1 changing from the high level to the low level is slowed, that is, that a rate of the signal VG at the control terminal of the power gate switch M1 changing from the high level to the low level is slowed down, and when a voltage at the control terminal of the power gate switch M1 rises and falls to reach a turn-on voltage of the power gate switch M1 The power gate switch M1 is turned on.
In the present embodiment, the charging and discharging actions of the first current source I1 and the second current source I2 of the delay module 20 are utilized to reduce the rising rate and the falling rate of the signal VG at the control terminal of the power gate switch M1, so as to delay the on-off speed of the power gate switch M1, thereby achieving the effects of reducing the peak current and reducing the peak voltage of the power voltage. In addition, compared to the first embodiment, the second embodiment does not use a resistor with a larger area, but uses a transistor (i.e., a current source) with a smaller size, so that the occupied area is smaller.
The invention also provides a memory chip which comprises the power supply gate control circuit. In a sleep mode of the memory chip, the power gate switch of the voltage gate control circuit is turned off to save power consumption. Through the design of the power gating circuit, when the working state of one functional module changes (for example, the working state is changed from a sleep state to the working state, or the working state is changed to the sleep state), the voltage drop on other functional modules is not influenced.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (13)
1. A power gating circuit, comprising:
a power gate switch, the first end of which is connected with the power voltage and the second end of which is connected with the functional module;
and the delay module is connected with the control end of the power supply brake switch, and a control signal is input to the control end of the power supply brake switch through the delay module so as to reduce the opening or closing speed of the power supply brake switch.
2. The power gating circuit of claim 1, wherein the delay module comprises a resistor and a capacitor, a first terminal of the resistor is connected to the control signal, a second terminal of the resistor is connected to a first terminal of the capacitor, a second terminal of the capacitor is connected to ground, and a control terminal of the power gating switch is connected to the first terminal of the capacitor.
3. The power gating circuit of claim 2, wherein the resistor is selected from one or a combination of a poly resistor, a metal resistor, or a doped resistor.
4. The power gating circuit of claim 2, wherein the capacitor is selected from one or a combination of a MOS capacitor, a PIP capacitor, a MIM capacitor, or a MOM capacitor.
5. The power gating circuit of claim 1, further comprising a buffer module, wherein the control signal is sequentially input to the control terminal of the power gate switch through the buffer module and the delay module.
6. The power gating circuit of claim 5, wherein the buffer module is formed by an even number or an odd number of inverters connected in series.
7. The power gating circuit of claim 1, wherein the delay module comprises an inverter, a first current source, a second current source and a capacitor, the first current source is connected to a first terminal of the inverter, the second current source is connected to a second terminal of the inverter, the control signal is input to an input terminal of the inverter, an output terminal of the inverter is connected to a control terminal of the power gate switch, a first terminal of the capacitor is connected to the control terminal of the power gate switch, and a second terminal of the capacitor is connected to ground.
8. The power gating circuit of claim 7, wherein the first current source is a PMOS current source and the second current source is an NMOS current source.
9. The power gating circuit of claim 1, wherein the power gate switch is a PMOS transistor or an NMOS transistor.
10. The power gating circuit of claim 1, wherein the power supply voltage is a power supply potential or a ground potential.
11. The power gating circuit of claim 1, wherein the functional module is one or a combination of a digital module and an analog module.
12. A memory chip comprising the power gating circuit of any one of claims 1 to 11.
13. The memory chip of claim 12, wherein the power gate switch of the voltage gating circuit is turned off in a sleep mode of the memory chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010021410.XA CN113098463A (en) | 2020-01-09 | 2020-01-09 | Power gating circuit and storage chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010021410.XA CN113098463A (en) | 2020-01-09 | 2020-01-09 | Power gating circuit and storage chip |
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| CN113098463A true CN113098463A (en) | 2021-07-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010021410.XA Pending CN113098463A (en) | 2020-01-09 | 2020-01-09 | Power gating circuit and storage chip |
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| US20040085700A1 (en) * | 2002-04-08 | 2004-05-06 | Exar Corporation | Delay line and transistor with RC delay gate |
| CN101867358A (en) * | 2009-01-13 | 2010-10-20 | 精工电子有限公司 | Delay circuit |
| TW201232981A (en) * | 2011-01-26 | 2012-08-01 | Global Unichip Corp | A power gating for in-rush current mitigation |
| CN104102316A (en) * | 2013-04-07 | 2014-10-15 | 鸿富锦精密电子(天津)有限公司 | Surge current regulating circuit |
| CN109672434A (en) * | 2018-12-24 | 2019-04-23 | 优数通（北京）科技有限公司 | A kind of automobile electronic controller supply voltage delay unlatching protection circuit |
| CN109742937A (en) * | 2019-01-23 | 2019-05-10 | 电子科技大学 | A kind of soft starting circuit with Digital Logic multiplexing control |
| TWI690160B (en) * | 2019-06-13 | 2020-04-01 | 瑞昱半導體股份有限公司 | Delay circuit |
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2020
- 2020-01-09 CN CN202010021410.XA patent/CN113098463A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040085700A1 (en) * | 2002-04-08 | 2004-05-06 | Exar Corporation | Delay line and transistor with RC delay gate |
| CN101867358A (en) * | 2009-01-13 | 2010-10-20 | 精工电子有限公司 | Delay circuit |
| TW201232981A (en) * | 2011-01-26 | 2012-08-01 | Global Unichip Corp | A power gating for in-rush current mitigation |
| CN104102316A (en) * | 2013-04-07 | 2014-10-15 | 鸿富锦精密电子(天津)有限公司 | Surge current regulating circuit |
| CN109672434A (en) * | 2018-12-24 | 2019-04-23 | 优数通（北京）科技有限公司 | A kind of automobile electronic controller supply voltage delay unlatching protection circuit |
| CN109742937A (en) * | 2019-01-23 | 2019-05-10 | 电子科技大学 | A kind of soft starting circuit with Digital Logic multiplexing control |
| TWI690160B (en) * | 2019-06-13 | 2020-04-01 | 瑞昱半導體股份有限公司 | Delay circuit |
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Application publication date: 20210709 |