CN113098092A

CN113098092A - Power supply method and charging method of super capacitor

Info

Publication number: CN113098092A
Application number: CN202110362938.8A
Authority: CN
Inventors: 崔伟; 沈皓
Original assignee: Shanghai Chuangmi Technology Co ltd
Current assignee: Shanghai Chuangmi Technology Co ltd
Priority date: 2021-04-02
Filing date: 2021-04-02
Publication date: 2021-07-09

Abstract

The scheme of the application provides a power supply method and a charging method of a super capacitor. The power supply method comprises the following steps: the constant power supply input voltage is reduced to obtain a charging matching voltage of the super capacitor; selecting a higher voltage of the emergency charging voltage and the charging matching voltage of the super capacitor as a charging power supply voltage of the super capacitor; charging the super capacitor by adopting a super capacitor charging chip, and controlling the charging current of the super capacitor charging chip for charging the super capacitor by using a quick charging control voltage or the emergency charging voltage; boosting the output voltage of the charged super capacitor to obtain MCU power supply matching voltage; and selecting a higher voltage of the charging matching voltage of the super capacitor and the power supply matching voltage of the MCU for voltage reduction so as to obtain the power supply voltage of the MCU. The problem of current use ultracapacitor system as the back-up source of intelligence door that charge time is long, energy consumption is big, and charge efficiency is low, back-up source loss height has been solved to this application scheme.

Description

Power supply method and charging method of super capacitor

Technical Field

The application relates to the field of intelligent door power supply control, in particular to a power supply method and a charging method of a super capacitor.

Background

Most of intelligent doors in the market at present adopt lithium batteries as a backup power supply of a door power supply system, but the lithium batteries are easy to cause major safety problems such as liquid leakage, fire and the like and are always the downspout of the industry; in addition, the normal service life of the lithium battery is 3 to 5 years, the service life of the lithium battery is not matched with that of the lithium battery which needs to be used for a long time, the battery is frequently required to be replaced, and the matched battery is difficult to buy in the market; at last, the lithium battery is limited by the charging and discharging times, so that the existing intelligent door is mostly required to be pulled out of the battery for charging and then is installed on the door, and the intelligent door is extremely inconvenient to use.

Based on this, at present, a scheme of using a super capacitor is considered by a small number of manufacturers as a backup power supply of the intelligent door, but the super capacitor is almost charged by adopting a resistance current-limiting method at present, so that the charging time is long, the energy consumption on a resistor is large, and the charging efficiency is extremely low; in addition, the circuit loss is large, the backup power loss is high, and the standby time and the number of times of opening the door can be greatly reduced.

Disclosure of Invention

The technical problem to be solved by the application scheme is that the existing scheme using the super capacitor is used as a backup power supply of the intelligent door, the charging time is long, the energy consumption on a resistor is large, and the charging efficiency is low; in addition, the circuit loss is large, the backup power loss is high, and the standby time and the number of times of opening the door can be greatly reduced.

In order to solve the technical problem, the present application discloses a charging method for a super capacitor, including:

selecting a higher voltage of an emergency charging voltage and a super-capacitor charging matching voltage as a super-capacitor charging power supply voltage, wherein the emergency charging voltage is output by an emergency charging interface, and the super-capacitor charging matching voltage is obtained by converting a normal power supply input voltage;

the super capacitor charging method comprises the steps that a super capacitor charging chip is adopted to charge a super capacitor, wherein the charging power supply voltage of the super capacitor is input into a voltage input pin of the super capacitor charging chip, the charging current of the super capacitor charging chip for charging the super capacitor is controlled through a quick charging control voltage or an emergency charging voltage, and the quick charging control voltage is controlled by an MCU.

Optionally, the selection of the charging power supply voltage of the super capacitor is realized by adopting a first schottky diode, a first MOS transistor, a first current-limiting resistor, a first pull-down resistor, a first capacitor and a second capacitor; the anode of the first Schottky diode is connected with a charging matching voltage end of the super capacitor, and the cathode of the first Schottky diode is connected with a charging power supply end of the super capacitor; the first capacitor and the second capacitor are connected in parallel between the charging power supply end and the grounding end of the super capacitor; the first current limiting resistor and the first pull-down resistor are connected in series between the charging matching voltage end of the super capacitor and the grounding end; the drain electrode of the first MOS tube is connected with an emergency charging voltage end, the grid electrode of the first MOS tube is connected with the connection point of the first current-limiting resistor and the first pull-down resistor, and the source electrode of the first MOS tube is connected with a charging power supply end of the super capacitor; the charging power supply end of the super capacitor outputs the charging power supply voltage of the super capacitor, the charging matching voltage end of the super capacitor inputs the charging matching voltage of the super capacitor, and the emergency charging voltage end inputs the emergency charging voltage.

Optionally, the control of the charging current is realized by using a first diode, a second MOS transistor, a second current-limiting resistor, a second pull-down resistor, a first voltage-dividing resistor and a second voltage-dividing resistor; the anode of the first diode is connected with an emergency charging voltage end, and the cathode of the first diode is connected with one end of the second current-limiting resistor; the anode of the second diode is connected with the quick charge control end, and the cathode of the second diode is connected with one end of the second current-limiting resistor; the other end of the second current limiting resistor is connected with one end of the second pull-down resistor and the grid electrode of the second MOS tube, and the other end of the second pull-down resistor is connected with a grounding end and the source electrode of the second MOS tube; one end of the first voltage dividing resistor is connected with a charging current input pin of the super capacitor charging chip, and the other end of the first voltage dividing resistor is connected with a grounding end; one end of the second voltage-dividing resistor is connected with a charging current input pin of the super capacitor charging chip, and the other end of the second voltage-dividing resistor is connected with a drain electrode of the second MOS tube; the emergency charging voltage is input by the emergency charging voltage end, and the quick charging control voltage is input by the quick charging control end.

Optionally, the super capacitor charging chip charges the two stages of super capacitors connected in series.

In order to solve the above technical problem, the present application further discloses a power supply method, including the above charging method, further including: the constant power supply input voltage is reduced to obtain the charging matching voltage of the super capacitor; boosting the output voltage of the charged super capacitor to obtain MCU power supply matching voltage; and selecting a higher voltage of the charging matching voltage of the super capacitor and the power supply matching voltage of the MCU for voltage reduction so as to obtain the power supply voltage of the MCU.

Optionally, the voltage reduction of the constant power supply input voltage is realized by using a first voltage reduction chip and a peripheral circuit matched with the first voltage reduction chip.

Optionally, the emergency charging voltage is output by using a USB emergency charging interface.

Optionally, the power supply method further includes dividing the emergency charging voltage to enable the MCU to detect access of the emergency charging interface.

Optionally, the first boost chip and the peripheral circuit matched with the first boost chip are used for boosting the output voltage of the charged super capacitor to obtain the power supply matching voltage of the MCU.

Optionally, selecting a higher voltage of the super capacitor charging matching voltage and the MCU power supply matching voltage is implemented by using a third diode and a fourth diode, and implementing voltage reduction by using a second voltage reduction chip and a peripheral circuit matched therewith to obtain the MCU power supply voltage; the anode of the third diode is connected with an MCU power supply matching voltage end, and the anode of the fourth diode is connected with a super capacitor charging matching voltage end; a voltage input pin of the second buck chip is connected with the cathode of the third diode and the cathode of the fourth diode; the MCU power supply matching voltage end inputs the MCU power supply matching voltage, and the super capacitor charging matching voltage end inputs the super capacitor charging matching voltage.

Optionally, the power supply method further includes: boosting the output voltage of the charged super capacitor to obtain a lock body power supply matching voltage; and selecting a higher voltage in the normally-supplied input voltage and the lock body power supply matching voltage as a lock body power supply voltage to be output, wherein the lock body power supply voltage is used for controlling a lock body motor of the intelligent door.

Optionally, the output voltage of the super capacitor after charging is boosted by using a second boost chip and a peripheral circuit matched with the second boost chip to obtain a lock body power supply matching voltage; the second boost chip comprises a control pin connected with a lock body motor control enabling end, and the lock body motor control enabling end is controlled by the MCU.

Optionally, selecting a higher voltage of the input voltage of the normally-supplied power supply and the lock body power supply matching voltage is realized by adopting a second schottky diode, a third MOS transistor, a third current-limiting resistor, a third pull-down resistor, a third capacitor and a fourth capacitor; the anode of the second Schottky diode is connected with a constant power supply input voltage end, and the cathode of the second Schottky diode is connected with a power supply end of the lock body; the third capacitor and the fourth capacitor are connected between the power supply end and the grounding end of the lock body in parallel; the third current limiting resistor and the third pull-down resistor are connected in series between the input voltage end of the normal power supply and the grounding end; the drain electrode of the third MOS tube is connected with a lock body power supply matching voltage end, the grid electrode of the third MOS tube is connected with the connection point of the third current limiting resistor and the third pull-down resistor, and the source electrode of the third MOS tube is connected with the lock body power supply end; the lock power supply matching voltage end inputs the lock power supply matching voltage, and the lock power supply end outputs the lock power supply voltage.

Optionally, when the normal power supply system supplies power normally, the charging matching voltage of the super capacitor is greater than the emergency charging voltage.

Optionally, when the normal power supply system supplies power normally, the MCU power supply matching voltage is greater than the maximum output voltage of the fully charged super capacitor and less than the super capacitor charging matching voltage.

Optionally, when the normal power supply system supplies power normally, the power supply matching voltage of the lock body is smaller than the input voltage of the normal power supply.

Compared with the prior art, the technical scheme of the application has at least the following beneficial effects:

the emergency charging voltage of the emergency charging voltage end is applied, so that the super capacitor can be charged by the emergency charging interface; and the charging current for charging the super capacitor by the super capacitor charging chip is controlled by the rapid charging control voltage controlled by the MCU or the emergency charging voltage of the emergency charging voltage end, so that the rapid charging and emergency charging interface of the super capacitor can be configured by software to rapidly charge the super capacitor.

Under the condition that a normal power supply system supplies power, the emergency charging interface is not connected, the quick charging control end outputs low level, the super capacitor can be charged by low current, and the purpose of prolonging the service life of the super capacitor is achieved.

The charging management chip special for the super capacitor with configurable charging current supports balanced charging of the super capacitors connected in series, a power supply scheme adopting series connection of two stages of super capacitors is realized, the super capacitors adopt a two-stage series connection mode, output voltage can be effectively improved, capacity cannot be reduced in a multiplied mode due to multi-stage series connection in capacity, the size and the application cost of the super capacitors are favorably reduced, and meanwhile charging balance of a single capacitor can be well achieved.

Under the power supply mode of the super capacitor for the MCU, the boost chip adopts a DC-DC chip with light load and high efficiency, and the buck LDO chip also adopts an LDO chip with low quiescent current, so that the power consumption can be guaranteed to be lowest under the condition of using the super capacitor for power supply, the service time of the super capacitor is prolonged, the effective door opening times are increased, and the super-long standby under the power supply mode of the super capacitor is realized.

The scheme breaks the dependence of the backup power supply on the lithium battery after the automatic lock body, the super capacitor supports the charging and discharging times for tens of thousands of times, the super capacitor can be used as the backup power supply on the intelligent door, and the replacement of the backup power supply cannot be carried out due to the service life problem.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a charging circuit for implementing a charging method according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a power supply system for implementing a power supply method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of the constant power input circuit shown in FIG. 2;

fig. 4 is a schematic structural diagram of the emergency charging input circuit shown in fig. 2;

FIG. 5 is a schematic structural diagram of the MCU power supply input circuit shown in FIG. 2;

FIG. 6 is a schematic diagram of the MCU power supply selection circuit shown in FIG. 2;

FIG. 7 is a schematic diagram of the power input circuit of the lock body shown in FIG. 2;

fig. 8 is a schematic structural diagram of the lock body power supply selection circuit shown in fig. 2.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

The inventor analyzes that the existing power supply mode using a super capacitor as a backup power supply of an intelligent door mainly has the following problems:

because the resistance current-limiting charging is adopted, no matter the emergency charging port outside the door or the normal power supply system is directly charged, the heating is serious, the charging efficiency is low, the charging time is long, and the user experience is influenced.

Because the charging circuit and the discharging circuit (power supply circuit) cannot be well isolated, the loss of the super capacitor is large, the standby time of the system is shortened, and the effective door opening times are reduced.

The conventional super capacitor scheme adopts a plurality of capacitors connected in series to improve the power supply voltage, but the capacity of the super capacitors is reduced after the super capacitors are connected in series, so that the capacity of a single capacitor needs to be increased to ensure the normal required capacity, and the whole capacitor pack is large in size, high in cost and inconvenient to install.

After the super capacitors are connected in series in multiple stages, charging is uncontrollable, the charging voltage balance of each capacitor is difficult to achieve, the situation that one capacitor exceeds the withstand voltage value and other capacitors are not fully charged is easily caused, and the service life and the safety of the capacitors cannot be guaranteed.

In addition, the traditional circuit does not realize emergency charging outside the door to improve charging current, and ensures that the door can be opened in the shortest time of charging; meanwhile, a common power supply system is charged at low current, and the service life of the capacitor is prolonged. The conventional circuit does not achieve the effect that after the super capacitor reaches the preset charging voltage, the charging circuit is directly powered off, but can continuously charge the capacitor with very small current, and certain influence is caused on the service life of the capacitor.

Based on the above problems in the prior art, an embodiment of the present application provides a method for charging a super capacitor, including:

The method may be implemented by using a circuit, and correspondingly, an embodiment of the present application provides a charging circuit for implementing the charging method for a super capacitor, as shown in fig. 1, the charging circuit includes: a super capacitor power supply selection circuit A1 and a super capacitor charging circuit A2.

The super-capacitor power supply selection circuit A1 comprises an emergency charging voltage end VCC _ BUS, a super-capacitor charging matching voltage end VCC _6V and a super-capacitor charging power supply end VCC _ IN, wherein the super-capacitor charging power supply end VCC _ IN selects the voltage output of the end with higher voltage IN the emergency charging voltage end VCC _ BUS and the super-capacitor charging matching voltage end VCC _ 6V;

the super-capacitor charging circuit A2 comprises a super-capacitor charging chip U1, a super-capacitor charging power supply terminal VCC _ IN, an emergency charging voltage terminal VCC _ BUS, a quick charging control terminal FAST _ CHARGE _ EN and a super-capacitor charging output voltage terminal VBAT, wherein the super-capacitor charging power supply terminal VCC _ IN is connected with a voltage input pin VIN of the super-capacitor charging chip U1, and the emergency charging voltage terminal VCC _ BUS or the quick charging control terminal FAST _ CHARGE _ EN controls the charging current of the super-capacitor charging chip U1 for charging the super-capacitor.

Further, as for the super capacitor power supply selection circuit a1 shown in fig. 1, the selection of the super capacitor charging supply voltage is realized by using a first schottky diode D1, a first MOS transistor Q1, a first current limiting resistor R17, a first pull-down resistor R2, a first capacitor C1, and a second capacitor C2. The anode of the first schottky diode D1 is connected to a super capacitor charging matching voltage terminal VCC _6V, and the cathode is connected to a super capacitor charging power supply terminal VCC _ IN; the first capacitor C1 and the second capacitor C2 are connected between the charging power supply terminal VCC _ IN of the super capacitor and the grounding terminal D _ GND IN parallel; the first current limiting resistor R17 and the first pull-down resistor R2 are connected in series between a charging matching voltage end VCC _6V of the super capacitor and a grounding end D _ GND; the Drain (Drain) of the first MOS transistor Q1 is connected with an emergency charging voltage terminal VCC _ BUS, the Gate (Gate) is connected with the connection point of the first current limiting resistor R17 and the first pull-down resistor R2, and the Source (Source) is connected with a super capacitor charging power supply terminal VCC _ IN; the super capacitor charging power supply terminal VCC _ IN outputs the super capacitor charging power supply voltage, the super capacitor charging matching voltage terminal VCC _6V inputs the super capacitor charging matching voltage, and the emergency charging voltage terminal VCC _ BUS inputs the emergency charging voltage.

In this embodiment, in the super capacitor power supply selection circuit a1, the emergency charging voltage of the emergency charging voltage terminal VCC _ BUS may be a voltage provided by the USB interface, and the voltage of the USB interface is generally between 4.5V and 5.5V. The first MOS transistor Q1 is a PMOS transistor, and the first pull-down resistor R2 is a gate pull-down resistor of the first MOS transistor Q1. One end of the first current limiting resistor R17 is connected with a super capacitor charging matching voltage end VCC _6V, the other end is connected with one end of a first pull-down resistor R2 and the grid of the first MOS transistor Q1, and the other end of the first pull-down resistor R2 is connected with the ground end D _ GND. The resistance value of the first current limiting resistor R17 is much smaller than that of the first pull-down resistor R2, so as to ensure that when the charging matching voltage terminal VCC _6V of the super capacitor is normally powered, the gate voltage of the first MOS transistor Q1 is approximately equal to the voltage of the charging matching voltage terminal VCC _6V of the super capacitor (since the voltage dividing relationship between R17 and R2 is slightly smaller than 6V). D1 is a Schottky diode, and has large overcurrent and small forward voltage drop.

When the charging matching voltage end VCC _6V of the super capacitor is normally powered, and the emergency charging voltage end VCC _ BUS is not powered, the charging matching voltage end VCC _6V of the super capacitor supplies power to the charging power supply end VCC _ IN of the super capacitor after passing through the first Schottky diode D1, at the moment, the first MOS tube Q1 is not conducted, and the MOS tube diode is reversely cut off.

When the super capacitor charging matching voltage end VCC _6V is abnormally powered off, the USB input voltage such as treasured that charges can be accessed through the emergency charging port, the first MOS pipe Q1 is switched on at this moment, the emergency charging voltage end VCC _ BUS supplies power to the super capacitor charging power supply end VCC _ IN through the first MOS pipe Q1, the first Schottky diode D1 is reversely cut off, and the super capacitor charging power supply end VCC _ IN does not influence the super capacitor charging matching voltage end VCC _6V and the circuit connected with the same.

When the super capacitor charging matching voltage end VCC _6V supplies power, and simultaneously, the USB input voltage (the emergency charging voltage end VCC _ BUS supplies power) is accessed, because the grid voltage of the first MOS tube is slightly lower than the super capacitor charging matching voltage and is larger than the emergency charging voltage, the first MOS tube Q1 is not conducted, the super capacitor charging matching voltage end VCC _6V supplies power to the super capacitor charging power supply end VCC _ IN through the first Schottky diode D1, because the first MOS tube Q1 is not conducted and the MOS tube diode is reversely cut off, the super capacitor charging power supply end VCC _ IN can not influence the emergency charging voltage end VCC _ BUS and the circuit connected with the same, thereby realizing the coexistence of the super capacitor charging matching voltage end VCC _6V and the emergency charging voltage end VCC _ BUS IN double power supply without mutual influence.

If because super capacitor charges the current demand of supply terminal VCC _ IN comparatively big, lead to super capacitor to charge the voltage that matches voltage terminal VCC _6V and fall IN the twinkling of an eye, be less than emergent charging voltage terminal VCC _ BUS, emergent charging voltage terminal VCC _ BUS will be through the body diode for super capacitor charges the supply terminal VCC _ IN power supply this moment, guarantee that super capacitor charges the voltage of supply terminal VCC _ IN and can not fall too badly.

The function of the super capacitor power supply selection circuit a1 is to compare which end of the super capacitor charging matching voltage end VCC _6V and the emergency charging voltage end VCC _ BUS has higher voltage, select the end input with higher voltage as the power supply output of the super capacitor charging power supply end VCC _ IN, and the two power supply inputs are not interfered with each other. The voltage 6V of the super-capacitor charging matching voltage terminal VCC _6V is a suggested value of the circuit of the embodiment, and is matched with the voltage input of the super-capacitor charging chip U1, and the variation range of the voltage is within the minimum and maximum voltage input requirement values of the super-capacitor charging chip U1.

In this embodiment, when the normal power supply system supplies power normally, the charging matching voltage of the super capacitor is greater than the emergency charging voltage. That is to say, under the condition that the normal power supply system normally provides the normal power supply input voltage, the voltage of the charging matching voltage terminal VCC _6V of the super capacitor of the normal power supply is greater than the voltage of the emergency charging voltage terminal VCC _ BUS, so that the voltage provided by the normal power supply system can be preferentially selected under the condition of the normal power supply.

Still referring to fig. 1, in the super capacitor charging circuit a2, a first diode D5, a second diode D6, a second MOS transistor Q2, a second current limiting resistor R8, a second pull-down resistor R20, a first voltage dividing resistor R3, and a second voltage dividing resistor R7 are used to control the charging current. The anode of the first diode D5 is connected to an emergency charging voltage terminal VCC _ BUS, and the cathode is connected to one end of the second current limiting resistor R8; the anode of the second diode D6 is connected to a FAST CHARGE control terminal FAST _ CHARGE _ EN, and the cathode is connected to one end of the second current limiting resistor R8; the other end of the second current limiting resistor R8 is connected to one end of the second pull-down resistor R20 and the Gate (Gate) of the second MOS transistor Q2, and the other end of the second pull-down resistor R20 is connected to the ground terminal D _ GND and the Source (Source) of the second MOS transistor Q2; one end of the first voltage dividing resistor R3 is connected with a charging current input pin IREF of the super capacitor charging chip U1, and the other end of the first voltage dividing resistor R3 is connected with a ground terminal D _ GND; one end of the second voltage-dividing resistor R7 is connected to the charging current input pin IREF of the super capacitor charging chip U1, and the other end is connected to the Drain (Drain) of the second MOS transistor Q2; the FAST charging control end FAST _ CHARGE _ EN inputs the FAST charging control voltage, and the emergency charging voltage end VCC _ BUS inputs the emergency charging voltage.

In this embodiment, the second MOS transistor Q2 is an NMOS transistor, and the second pull-down resistor R20 is a gate pull-down resistor of the second MOS transistor Q2, so as to ensure that the gate level is low when no preceding stage driving is performed. The resistance value of the second current limiting resistor R8 is much smaller than that of the second pull-down resistor R20, so that the second MOS transistor Q2 can be normally turned on after voltage division is performed by the second current limiting resistor R8 and the second pull-down resistor R20 when voltage is input at the front stage of the second current limiting resistor R8. The super capacitor charging circuit A2 further comprises a bypass capacitor C6, which is used as a bypass capacitor of the super capacitor charging chip U1 and plays a role in filtering.

In this embodiment, as shown in fig. 1, the super capacitor charging chip U1 charges two stages of super capacitors C4 and C5 connected in series, and the super capacitors C4 and C5 are connected in series between the super capacitor charging output voltage terminal VBAT and the ground terminal D _ GND. The super capacitor charging chip U1 adopts a super capacitor dedicated charging management chip capable of configuring charging current, for example, an SGM40560 chip, which is a chip capable of charging a super capacitor, and the charging current can be externally connected with different resistances through a pin IREF to realize different charging currents, and the smaller the resistance of the external resistor is, the larger the charging current for the super capacitor is. The SGM40560 chip supports balanced charging of double-section series super capacitors. The super capacitor charging chip is replaceable, for example, the super capacitor charging chip can be a linear charging chip or a switch charging chip, and the charging current is required to be configurable. The connection mode of the super capacitors C4 and C5 and the super capacitor charging chip U1 is determined according to the connection mode of the adopted chips.

The first diode D5, the second diode D6, the second MOS transistor Q2, the second current limiting resistor R8, the second pull-down resistor R20, the first voltage dividing resistor R3 and the second voltage dividing resistor R7 form a selection circuit, and the or relation is realized, wherein the FAST CHARGE control end FAST _ CHARGE _ EN is controlled by the MCU, and can output a high level or a low level through software control.

Specifically, when the emergency charging is performed, the emergency charging voltage terminal VCC _ BUS has a voltage, which is a high level, and the FAST charging control terminal FAST _ CHARGE _ EN is a low level, the emergency charging voltage terminal VCC _ BUS supplies power to the second MOS transistor Q2 after voltage division is performed by the first diode D5, the second current limiting resistor R8 and the second pull-down resistor R20, and at this time, the second MOS transistor Q2 is turned on, so that the first voltage dividing resistor R3 and the second voltage dividing resistor R7 are connected in parallel. After parallel connection, the equivalent resistance value is reduced, and the charging current of the super capacitor charging chip U1 to the super capacitors C4 and C5 is increased. At this time, the second diode D6 is turned off in the reverse direction, and the emergency charging voltage terminal VCC _ BUS does not affect the FAST charging control terminal FAST _ CHARGE _ EN and the connection circuit thereof.

When the emergency charging is not connected, the emergency charging voltage end VCC _ BUS is at a low level, and the MCU controls the FAST charging control end FAST _ CHARGE _ EN to output a high level, the FAST charging control end FAST _ CHARGE _ EN supplies power to the second MOS tube Q2 through the second diode D6, the second current limiting resistor R8 and the second pull-down resistor R20 after voltage division, and the second MOS tube Q2 is turned on at this time, so that the first voltage dividing resistor R3 and the second voltage dividing resistor R7 are connected in parallel. After parallel connection, the equivalent resistance value is reduced, and the charging current of the super capacitor charging chip U1 to the super capacitors C4 and C5 is increased. At this time, the first diode D5 is turned off in the reverse direction, and the FAST CHARGE control terminal FAST _ CHARGE _ EN does not affect the emergency CHARGE voltage terminal VCC _ BUS and the connection circuit thereof.

When the MCU controls the FAST CHARGE control terminal FAST _ CHARGE _ EN to output a high level and the emergency CHARGE voltage terminal VCC _ BUS is a high level (emergency CHARGE access), both supply power to the back end at the same time, the voltage value of the common connection terminal of the first diode D5 and the second diode D6 is raised by the input terminal with higher voltage (high voltage power supply side), resulting in the reverse cut-off of the diode of the input terminal with lower voltage (low voltage power supply side) without supplying power. At this time, the high-voltage power supply side supplies power to the rear-end second MOS transistor Q2, and at this time, the second Q2 is turned on, so that the first voltage-dividing resistor R3 and the second voltage-dividing resistor R7 are connected in parallel. After parallel connection, the equivalent resistance value is reduced, and the charging current of the super capacitor charging chip U1 to the super capacitors C4 and C5 is increased. Due to the existence of the diodes D5 and D6, two paths of inputs can coexist without mutual influence.

When the FAST CHARGE control terminal FAST _ CHARGE _ EN inputs a low level and the emergency CHARGE is not connected (the emergency CHARGE voltage terminal VCC _ BUS inputs a low level), the second MOS transistor Q2 is not turned on, the CHARGE connection resistor is the first divider resistor R3, the resistance is larger than that when the first divider resistor R3 and the second divider resistor R7 are connected in parallel, the CHARGE current is small, and the slow CHARGE of the current is realized.

The resistances of the first divider resistor R3 and the second divider resistor R7 need to be adapted according to different charging chips, and the resistors needed to be configured for different super capacitor charging chips are different.

The super capacitor can be charged by a normal power supply system and an emergency charging interface through the super capacitor power supply selection circuit A1 and the super capacitor charging circuit A2, and the charging current can be controlled through the emergency charging interface and the MCU to carry out quick charging.

The embodiment of the present application further provides a power supply method including the charging method for the super capacitor, where the power supply method further includes: the constant power supply input voltage is reduced to obtain the charging matching voltage of the super capacitor; boosting the output voltage of the charged super capacitor to obtain MCU power supply matching voltage; and selecting a higher voltage of the charging matching voltage of the super capacitor and the power supply matching voltage of the MCU for voltage reduction so as to obtain the power supply voltage of the MCU.

Correspondingly, referring to fig. 2, an embodiment of the present application provides a power supply system for implementing the power supply method, where the power supply system includes: the emergency charging circuit comprises a normal power supply input circuit A3, an emergency charging input circuit A4, a charging circuit, an MCU power supply input circuit A5 and an MCU power supply selection circuit A6. The charging circuit comprises a super capacitor power supply selection circuit A1 and a super capacitor charging circuit A2, and the super capacitor power supply selection circuit A1 and the super capacitor charging circuit A2 can be in circuit structures as shown in FIG. 1.

Referring to fig. 3, the constant power supply input circuit A3 includes a constant power supply input voltage terminal VCC _ NORMAL, a super capacitor charging matching voltage terminal VCC _6V, and a first voltage dropping circuit a31, where the first voltage dropping circuit a31 drops the voltage of the constant power supply input voltage terminal VCC _ NORMAL to obtain the voltage of the super capacitor charging matching voltage terminal VCC _ 6V.

In the first voltage reduction circuit a31, the voltage reduction of the normally-supplied input voltage is realized by using a first voltage reduction chip U2 and a peripheral circuit matched with the first voltage reduction chip U2. In this embodiment, the constant power supply system provides an output voltage of 8V to 16V, that is, the constant power supply input voltage provided by the constant power supply input voltage terminal VCC _ NORMAL is 8V to 16V. J3 is used as input interface of normal power supply input voltage, and is connected with terminal base, 1 pin is connected with positive pole of voltage input, 2 pin is connected with negative pole of voltage input. And ensuring that the power supply equipment can be connected to the system to supply power to the system.

First step-down chip U2 cooperation outlying resistance, electric capacity and inductance constitute the step-down circuit, step down the input NORMAL power supply input voltage to 6V, and under the NORMAL circumstances of supplying power of input voltage end VCC _ NORMAL NORMAL power supply promptly often, the super capacitor that super capacitor charges the output of matching voltage end VCC _6V charges the matching voltage and is 6V.

The first buck chip U2 may be a DC-DC buck chip, for example, a SY8120B1ABC chip, resistors R4, R5, R6, capacitors C7, C8, C9, C10, C11, C12, and an inductor L1, and the matching SY8120B1ABC chip jointly form a standard DC-DC buck circuit, the design of the peripheral circuit is determined by the reference design of the SY8120B1ABC chip, and the peripheral design circuits of different buck chips are slightly different. In addition, P1 is a circuit test point.

Referring to fig. 4, the emergency charging input circuit a4 includes an emergency charging voltage terminal VCC _ BUS. In this embodiment, the emergency charging voltage is output by using the USB emergency charging interface J1, and the USB emergency charging interface J1 may be connected to a USB charging line. Specifically, the emergency charging input circuit a4 includes a USB emergency charging interface J1, and the emergency charging voltage terminal VCC _ BUS is connected to a voltage output pin VBUS of the USB emergency charging interface J1.

Further, the emergency charging input circuit a4 may further include a resistor voltage dividing circuit a41 for dividing the voltage of the emergency charging voltage terminal VCC _ BUS. And dividing the emergency charging voltage, so that the MCU can detect the access of an emergency charging interface J1. Because the MCU that the system used is the system of 3.3V or lower voltage, and the USB input is 5V input generally, divider resistor R19 and R1 constitute resistance bleeder circuit A41, the voltage of meeting an urgent need charging voltage end VCC _ BUS is dropped to the voltage value that matches with MCU power supply, bleeder voltage end VBUS _ IN outputs the partial pressure voltage of meeting an urgent need charging voltage, partial pressure end VBUS _ IN connects MCU, MCU can discern through discerning the voltage value of partial pressure voltage end VBUS _ IN has USB power supply to insert dynamically, thereby control the charge speed of ultracapacitor system dynamically. The capacitor C3 is a filtering bypass capacitor connected to the USB, so as to prevent the voltage overshoot at the moment of USB insertion and influence the circuit powered by the power supply at the rear end.

Referring to fig. 5, the MCU power supply input circuit a5 includes a super capacitor charging output voltage terminal VBAT, an MCU power supply matching voltage terminal VCC _5V5, and a first voltage boost circuit a51, where the first voltage boost circuit a51 boosts the voltage of the super capacitor charging output voltage terminal VBAT to obtain the voltage of the MCU power supply matching voltage terminal VCC _5V5, that is, the MCU power supply matching voltage.

In this embodiment, the first boost chip U3 and the peripheral circuit matched therewith are used to boost the output voltage of the charged super capacitor to obtain the MCU power supply matching voltage. Specifically, the first boost circuit a51 includes a first boost chip U3 and its matched peripheral circuits.

The first boost chip U3 may be a DC-DC boost chip with light load and high efficiency, for example, an SGM6603 chip, and the design of the peripheral circuits is determined by the reference design of the SGM6603 chip, and the peripheral design circuits of different boost chips are slightly different. The resistors R9 and R10, the capacitors C13, C14, C15 and the inductor L2 are matched with an SGM6603 chip to jointly form a standard DC-DC boost circuit, the output voltage of the super capacitor, which is provided by a super capacitor charging output voltage end VBAT, is boosted to 5.5V, namely the MCU power supply matching voltage output by an MCU power supply matching voltage end VCC _5V5 is 5.5V, the boosted voltage value can be changed as required, and when a normal power supply system supplies power normally, the MCU power supply matching voltage is larger than the maximum output voltage of the super capacitor (the super capacitor with two stages connected in series in the embodiment) after being fully charged and is smaller than the super capacitor charging matching voltage.

Referring to fig. 6, the MCU power supply selection circuit a6 includes a super capacitor charging matching voltage terminal VCC _6V, MCU power supply matching voltage terminal VCC _5V5, a voltage selection circuit a61, a second voltage reduction circuit a62 and an MCU power supply terminal VCC _ MCU _3V3, the voltage selection circuit a61 selects the voltage of the higher voltage end of the super capacitor charging matching voltage terminal VCC _6V and the MCU power supply matching voltage terminal VCC _5V5 to be provided to the second voltage reduction circuit a62, and the second voltage reduction circuit a62 reduces the voltage provided by the voltage selection circuit a61 to obtain the voltage of the MCU power supply terminal VCC _ MCU _3V 3.

In this embodiment, the higher voltage of the super capacitor charging matching voltage and the MCU power supply matching voltage is selected by using the third diode D2 and the fourth diode D3, and the second buck chip U4 and its matched peripheral circuit are used to implement buck to obtain the MCU power supply voltage.

Specifically, the voltage selection circuit a61 includes a third diode D2 and a fourth diode D3, an anode of the third diode D2 is connected to the MCU supply matching voltage terminal VCC _5V5, and an anode of the fourth diode D3 is connected to the super capacitor charging matching voltage terminal VCC _ 6V; the second buck circuit a62 includes a second buck chip U4 and its matched peripheral circuits, and the voltage input pin IN of the second buck chip U4 is connected to the cathode of the third diode D2 and the cathode of the fourth diode D3. The MCU power supply matching voltage end VCC _5V5 inputs the MCU power supply matching voltage, and the super capacitor charging matching voltage end VCC _6V inputs the super capacitor charging matching voltage.

The third diode D2 and the fourth diode D3 have the same functions as the first diode D5 and the second diode D6, and the end with higher voltage in the MCU power supply matching voltage end VCC _5V5 and the super capacitor charging matching voltage end VCC _6V is selected to supply power for the rear-end second buck chip U4. The super capacitor is used as a reserve power supply after normal power supply and power failure, the voltage value of the MCU power supply matching voltage end VCC _5V boosted by the first boosting chip U3 is smaller than the voltage value of the super capacitor charging matching voltage end VCC _6V, and the storage electric quantity of the super capacitor is not used in the normal power supply using process of a normal power supply system.

The second buck chip U4 may be an LDO chip with low quiescent current, and the design of its matched peripheral circuits is determined by the reference design of the LDO chip, and the peripheral design circuits of different buck chips are slightly different. Capacitors C16 and C17 match the LDO chip and jointly constitute LDO step-down circuit, step-down the voltage of MCU power supply matching voltage end VCC _5V5 and super capacitor charging matching voltage end VCC _6V after the selection to 3.3V, MCU power supply voltage that MCU power supply end VCC _ MCU _3V3 output is 3.3V promptly, the MCU adaptation that this voltage value can adopt according to actual need changes.

Further, the power supply method of the embodiment of the application further includes: boosting the output voltage of the charged super capacitor to obtain a lock body power supply matching voltage; and selecting a higher voltage in the normally-supplied input voltage and the lock body power supply matching voltage as a lock body power supply voltage to be output, wherein the lock body power supply voltage is used for controlling a lock body motor of the intelligent door.

Correspondingly, referring to fig. 2, the power supply system of the embodiment of the present application further includes: lock body power supply input circuit a7 and lock body power supply selection circuit A8. The lock body power supply input circuit A7 and the lock body power supply selection circuit A8 can be applied to power supply of a full-automatic lock body, and for application of a non-full-automatic lock body, the lock body power supply input circuit A7 and the lock body power supply selection circuit A8 are not needed, and power supply of the non-full-automatic lock body and power supply of the MCU use the same power supply.

Referring to fig. 7, the lock body power supply input circuit a7 includes a super capacitor charging output voltage terminal VBAT, a lock body power supply matching voltage terminal VCC _8V, and a second voltage boost circuit a71, where the second voltage boost circuit a71 boosts the voltage of the super capacitor charging output voltage terminal VBAT to obtain the voltage of the lock body power supply matching voltage terminal VCC _ 8V.

In this embodiment, the output voltage of the super capacitor after charging is boosted by using the second boost chip U5 and a peripheral circuit matched with the second boost chip U5 to obtain a lock body power supply matching voltage; the second boost chip U5 comprises a control pin EN connected with a lock body motor control enabling end PW _ EN, and the lock body motor control enabling end PW _ EN is controlled by the MCU.

Specifically, the second boost circuit a71 includes a second boost chip U5 and its matched peripheral circuits. The second boost chip U5 may be a DC-DC boost chip capable of providing a large current, such as an SGM6611C chip, and the design of its peripheral circuit is determined by the reference design of the SGM6611C chip, and the design of the peripheral circuits of different boost chips are slightly different. The resistors R13, R14, R15, R16 and R18, the capacitors C20, C21, C22, C23, C24, C25 and the inductor L3 are matched with an SGM6611C chip to jointly form a standard DC-DC boost circuit, the output voltage of the super capacitor after charging provided by a super capacitor charging output voltage end VBAT is boosted to 8V, namely the lock body power supply matching voltage output by a lock body power supply matching voltage end VCC _8V is 8V, the voltage 8V of the lock body power supply matching voltage end VCC _8V is the proposed value of the circuit of the embodiment and is matched with a lock body motor, the boosted voltage value can be changed according to needs, and when a normal power supply system normally supplies power, the lock body power supply matching voltage is smaller than the normal power supply input voltage.

Because the lock body is controlled by the motor, generally, the required current is large, so the DC-DC boost chip can be selected to have a DC-DC boost chip with a current limiting function, for example, a pin ILIM of the second boost chip U5 in fig. 7 can be configured by an external resistor, so that the DC-DC output current limitation is realized, and the danger caused by the overlarge motor current when an accident occurs is prevented.

Because the DC-DC boost chip with large output current is difficult to achieve low power consumption, if the chip is always in operation, the electric quantity of the super capacitor serving as a reserve power supply can be consumed quickly. Therefore, the chip needs to be provided with an enabling end, an enabling pin EN of a second boosting chip U5 is controlled by a lock body motor control enabling end PW _ EN connected with the MCU, when the motor does not need to work, the MCU pulls down the lock body motor control enabling end PW _ EN, the second boosting chip U5 does not work, and the chip is approximately considered not to consume power; when the motor action is needed, the lock body motor control enabling end PW _ EN is pulled high through the MCU, the second voltage boosting chip U5 starts to work, voltage can be output to the motor, and therefore the motor is driven to work. Therefore, the capacity of the super capacitor can be effectively reduced, the scheme cost is reduced, and meanwhile, the service life of the super capacitor can be prolonged under the condition of the same capacity.

Referring to fig. 8, the LOCK body power supply selection circuit A8 includes a constant power supply input voltage terminal VCC _ NORMAL, a LOCK body power supply matching voltage terminal VCC _8V, and a LOCK body power supply terminal VCC _ LOCK, where the LOCK body power supply terminal VCC _ LOCK selects a voltage output of a higher voltage terminal of the constant power supply input voltage terminal VCC _ NORMAL and the LOCK body power supply matching voltage terminal VCC _ 8V.

In this embodiment, the selection of the higher voltage of the input voltage of the constant power supply and the matching voltage of the lock power supply is implemented by using a second schottky diode D4, a third MOS transistor Q3, a third current-limiting resistor R12, a third pull-down resistor R11, a third capacitor C18, and a fourth capacitor C19.

Specifically, the lock body power supply selection circuit A8 further includes: the circuit comprises a second Schottky diode D4, a third MOS transistor Q3, a third current limiting resistor R12, a third pull-down resistor R11, a third capacitor C18 and a fourth capacitor C19.

The anode of the second Schottky diode D4 is connected with a normally-supplied input voltage terminal VCC _ NORMAL, and the cathode of the second Schottky diode D4 is connected with a LOCK body power supply terminal VCC _ LOCK; the third capacitor C18 and the fourth capacitor C19 are connected between the power supply terminal VCC _ LOCK of the LOCK body and the ground terminal D _ GND in parallel; the third current limiting resistor R12 and the third pull-down resistor R11 are connected in series between the normally-supplied input voltage terminal VCC _ NORMAL and the ground terminal D _ GND; the Drain (Drain) of the third MOS transistor Q3 is connected with a LOCK body power supply matching voltage end VCC _8V, the grid (Gate) is connected with the connection point of the third current limiting resistor R12 and the third pull-down resistor R11, and the Source (Source) is connected with a LOCK body power supply end VCC _ LOCK; the input voltage that supplies power frequently end VCC _ NORMAL input the input voltage that supplies power frequently, LOCK body power supply matching voltage end VCC _8V inputs the LOCK body power supply matching voltage, LOCK body power supply end VCC _ LOCK exports LOCK body power supply voltage.

The third MOS transistor Q3 is a PMOS transistor, and the third pull-down resistor R11 is a gate pull-down resistor of the third MOS transistor Q3. One end of the third current limiting resistor R12 is connected to the normally-supplied input voltage terminal VCC _ NORMAL, the other end is connected to one end of the third pull-down resistor R11 and the gate of the third MOS transistor Q3, and the other end of the third pull-down resistor R11 is connected to the ground terminal D _ GND. The resistance of the third current-limiting resistor R12 is much smaller than the resistance of the third pull-down resistor R11, so as to ensure that when the normally-powered input voltage terminal VCC _ NORMAL supplies power, the gate voltage of the third MOS transistor Q3 is approximately equal to the voltage of the normally-powered input voltage terminal VCC _ NORMAL (since the voltage dividing relationship between the resistors R12 and R11 is slightly smaller). D4 is a Schottky diode, and has large overcurrent and small forward voltage drop.

The circuit structure of the lock body power supply selection circuit A8 is substantially the same as that of the super capacitor power supply selection circuit a1, and the operation principle thereof can refer to the description of the super capacitor power supply selection circuit a 1. The LOCK body power supply selection circuit A8 mainly has the functions that the voltage of the end of the normally-supplied input voltage end VCC _ NORMAL is higher than that of the LOCK body power supply matching voltage end VCC _8V, the end with higher voltage is selected as the power supply output of the LOCK body power supply end VCC _ LOCK, and the two power supply inputs are not interfered with each other. J2 in fig. 8 is a connection terminal for connecting the lock body, supplying power to the lock body, and supplying power to the output terminal base. The third capacitor C18 and the fourth capacitor C19 are capacitors with large capacitance values, the motor can generate large current consumption at the starting moment, the voltage of an input end is easy to pull down, and voltage drop can be effectively reduced through the two large capacitors of the third capacitor C18 and the fourth capacitor C19.

Because the super capacitor is used as a reserve power supply after the NORMAL power supply and outage, when the NORMAL power supply system supplies power normally, the lock body power supply matching voltage of the lock body power supply matching voltage terminal VCC _8V boosted by the second boosting chip U5 is less than the lowest power supply voltage (NORMAL power supply input voltage) provided by the NORMAL power supply input voltage terminal VCC _ NORMAL, so that the stored electric quantity of the super capacitor is not used in the NORMAL use process of the NORMAL power supply system.

The operation of the power supply system of the present embodiment in practical application will be described with reference to the drawings, and for simplicity of description, the signal terminal symbol directly represents the terminal voltage.

In the case of only the constant power supply system supplying power:

referring to fig. 3, VCC _ NORMAL output by the constant power supply system converts a voltage of 8V to 16V of constant power supply into an output voltage VCC _6V of 6V through a DC-DC voltage reduction chip U2, wherein voltage reduction is mainly for compatibility with a linear super capacitor charging chip U1, and it is avoided that a heating value is increased and charging efficiency is reduced due to too large voltage difference between an input stage and an output stage of the linear super capacitor charging chip.

Referring to fig. 1, a 6V input voltage is provided to VCC _ IN to charge the super capacitor, at this time, the MOS transistor Q2 IN the circuit is not turned on, the charging current is controlled by the resistance of the resistor R3, and the larger the resistance of the resistor R3 is, the smaller the charging current is, so that the super capacitor can be charged with a small current under the condition of normal power supply, and the purpose of prolonging the service life of the super capacitor is achieved.

If a user needs to fully CHARGE the super capacitor as soon as possible, then a power-off action of a normal power supply system is executed, the MCU can be informed through configuration parameters, the MCU can control FAST _ CHARGE _ EN in a circuit to output a high level, and control the conduction of an MOS tube Q2, so that resistors R7 and R3 are connected in parallel, according to a parallel formula, the parallel equivalent resistor is (R7R 3)/(R7+ R3), and the formula shows that the parallel equivalent resistor is lower than the resistance of any one of the resistors, the smaller the equivalent resistor connected to an IREF pin of a U1 chip is, the larger the charging current is, and the purpose of software-controlled quick charging is achieved.

When the super capacitor is charged to a preset charging voltage, the charging chip U1 enters a rollback supply holding state, the situation that the super capacitor is charged all the time and the service life of the super capacitor is influenced is avoided, and when the voltage of the super capacitor is reduced to a threshold voltage, the charging chip U1 can start a new round of charging circulation to ensure the electric quantity of the super capacitor.

The super capacitor adopts a two-stage series connection mode, so that the output voltage can be effectively improved, the capacity can not be reduced by times due to multi-stage series connection in capacity, the size and the application cost of the super capacitor can be reduced, and the charge balance of a single capacitor can be well realized.

In the normal power mode, due to the MCU power selection circuit a6 and the lock power selection circuit A8, referring to fig. 6 and 8, the output of the super capacitor is not actually powered in the circuit. However, once the normal power supply system has power failure or other faults, the output circuit of the super capacitor can realize seamless switching, and the subsequent system cannot be powered off.

When the normal power supply system is powered off and the emergency charging interface is not input:

the system is powered by a super capacitor, the output voltage of the super capacitor is greatly changed under different capacities, the change range of the output voltage VBAT of the super capacitor with two stages connected in series is about 0V to 5.4V, the MCU power supply system is 3.3V, and in order to ensure the normal work of the MCU, the DC-DC voltage is firstly boosted to 5.5V, and then reference is made to the graph 5; then the voltage is reduced to 3.3V by the LDO to supply power for the MCU, and refer to FIG. 6. The boost chip U3 adopts a DC-DC with light load and high efficiency, and the buck LDO chip U4 also adopts an LDO with low quiescent current, so that the power consumption can be guaranteed to be the lowest under the condition of using a super capacitor for power supply, and the service time and the effective door opening times of the super capacitor are prolonged.

The full-automatic lock body is supplied with power by the super capacitor, because the full-automatic lock body needs the action that great electric current could realize the switch lock, and the chip that steps up that can provide heavy current is generally quiescent current than great, if work in the circuit for a long time, can consume a large amount of electric energy of super capacitor, for this reason, MCU power supply and lock body power supply adopt the mode of dividing the chip and supplying power alone. Referring to fig. 7, when unlocking and locking actions are required, the MCU enables the boost chip U5 through the control terminal PW _ EN, and VBAT boosts to VCC _8V, and then supplies power to VCC _ LOCK to control the LOCK body to perform opening and closing actions; after the switching action is executed, the MCU closes the boost chip U5 through the control terminal PW _ EN, the boost chip U5 does not consume the electric quantity of the super capacitor any more, VCC _8V outputs low level, and the requirements of prolonging the service time of the super capacitor and effectively opening and closing the door are also met.

When the super capacitor is dead and the normal power supply system is powered off:

under the conditions that the super capacitor is in a power failure state and the constant power supply system is in a power failure state, the intelligent door cannot normally work, the super capacitor needs to be charged through the emergency charging interface at the moment, and a user wants to charge the super capacitor at the fastest speed, so that the door can be opened and closed in the shortest time. This system adopts the dynamic circuit, refers to fig. 1, and when charging from the emergent interface that charges, VCC _ BUS supplies power for VCC _ IN charges for super capacitor to MOS pipe Q2 switches on, and charging current grow has realized the purpose that can quick charge through the emergent interface that charges.

When the total voltage of the super capacitor is higher than the starting threshold voltage of the boost chip U3 in fig. 5, the MCU can work normally, and the switching of the gate can be controlled normally by the system software.

When a normal power supply system is electrified, the super capacitor is charged through the emergency charging port:

due to the super capacitor power supply selection circuit A1, even if the emergency charging interface has voltage access, the electric quantity of the emergency charging interface is not consumed. The system can detect that the emergency charging interface is connected, and an MOS tube Q2 in the charging circuit of fig. 1 is conducted, so that the super capacitor can be rapidly charged.

In summary, in a conventional situation, the system circuit is powered by the constant power supply system, and the constant power supply system always charges the super capacitor, the selection circuit is used for ensuring that all power supplies are provided by the constant power supply system in the constant power supply mode, and when the constant power supply system is powered off, the system can be seamlessly switched to be powered by the super capacitor without generating a power supply interruption phenomenon.

Before the user needs to actively cut off the constant power supply, in order to ensure that the super capacitor can be in a standby state in a maximized mode, the MCU can be informed to be switched to a quick charging mode before the constant power supply is cut off, the super capacitor is charged as soon as possible, the charging voltage can be accessed through the emergency charging interface, the quick charging is started, and the electric quantity of the super capacitor is charged as soon as possible. Under the condition that the normal power supply is not interrupted, the charging is not carried out from the emergency charging interface, and the emergency charging interface only plays a role in starting the quick charging.

Under the circumstances that the power supply outage often and super capacitor do not have the electricity, can charge for super capacitor fast through the emergent interface that charges, after super capacitor charged certain voltage, entire system just can normally work, guarantees that the system can normal operating.

In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.

Claims

1. A charging method of a super capacitor is characterized by comprising the following steps:

2. The charging method of the super capacitor as claimed in claim 1, wherein the selection of the charging supply voltage of the super capacitor is realized by using a first schottky diode, a first MOS transistor, a first current limiting resistor, a first pull-down resistor, a first capacitor and a second capacitor; wherein the content of the first and second substances,

the anode of the first Schottky diode is connected with a charging matching voltage end of the super capacitor, and the cathode of the first Schottky diode is connected with a charging power supply end of the super capacitor; the first capacitor and the second capacitor are connected in parallel between the charging power supply end and the grounding end of the super capacitor; the first current limiting resistor and the first pull-down resistor are connected in series between the charging matching voltage end of the super capacitor and the grounding end; the drain electrode of the first MOS tube is connected with an emergency charging voltage end, the grid electrode of the first MOS tube is connected with the connection point of the first current-limiting resistor and the first pull-down resistor, and the source electrode of the first MOS tube is connected with a charging power supply end of the super capacitor; the charging power supply end of the super capacitor outputs the charging power supply voltage of the super capacitor, the charging matching voltage end of the super capacitor inputs the charging matching voltage of the super capacitor, and the emergency charging voltage end inputs the emergency charging voltage.

3. The charging method of the super capacitor as claimed in claim 1 or 2, wherein the control of the charging current is realized by using a first diode, a second MOS transistor, a second current limiting resistor, a second pull-down resistor, a first voltage dividing resistor and a second voltage dividing resistor; wherein the content of the first and second substances,

the anode of the first diode is connected with an emergency charging voltage end, and the cathode of the first diode is connected with one end of the second current-limiting resistor; the anode of the second diode is connected with the quick charge control end, and the cathode of the second diode is connected with one end of the second current-limiting resistor; the other end of the second current limiting resistor is connected with one end of the second pull-down resistor and the grid electrode of the second MOS tube, and the other end of the second pull-down resistor is connected with a grounding end and the source electrode of the second MOS tube; one end of the first voltage dividing resistor is connected with a charging current input pin of the super capacitor charging chip, and the other end of the first voltage dividing resistor is connected with a grounding end; one end of the second voltage-dividing resistor is connected with a charging current input pin of the super capacitor charging chip, and the other end of the second voltage-dividing resistor is connected with a drain electrode of the second MOS tube; the emergency charging voltage is input by the emergency charging voltage end, and the quick charging control voltage is input by the quick charging control end.

4. The method for charging the super capacitor as claimed in claim 1, wherein the super capacitor charging chip charges the super capacitors connected in series in two stages.

5. A method of supplying power, comprising: the charging method of any one of claims 1 to 4, further comprising:

the constant power supply input voltage is reduced to obtain the charging matching voltage of the super capacitor;

boosting the output voltage of the charged super capacitor to obtain MCU power supply matching voltage;

and selecting a higher voltage of the charging matching voltage of the super capacitor and the power supply matching voltage of the MCU for voltage reduction so as to obtain the power supply voltage of the MCU.

6. The power supply method according to claim 5, wherein the step-down of the normally-supplied input voltage is implemented by using a first step-down chip and a matched peripheral circuit thereof.

7. The power supply method according to claim 5, wherein the emergency charging voltage is output using a USB emergency charging interface.

8. The power supply method according to claim 5, further comprising dividing the emergency charging voltage for the MCU to detect access of an emergency charging interface.

9. The power supply method according to claim 5, wherein the step-up of the output voltage after the charging of the super capacitor is realized by adopting a first step-up chip and a peripheral circuit matched with the first step-up chip to obtain the MCU power supply matching voltage.

10. The power supply method according to claim 5, wherein the selection of the higher one of the super capacitor charging matching voltage and the MCU power supply matching voltage is realized by using a third diode and a fourth diode, and the step-down is realized by using a second step-down chip and a peripheral circuit matched with the second step-down chip to obtain the MCU power supply voltage; wherein the content of the first and second substances,

the anode of the third diode is connected with the MCU power supply matching voltage end, and the anode of the fourth diode is connected with the super capacitor charging matching voltage end; a voltage input pin of the second buck chip is connected with the cathode of the third diode and the cathode of the fourth diode; the MCU power supply matching voltage end inputs the MCU power supply matching voltage, and the super capacitor charging matching voltage end inputs the super capacitor charging matching voltage.

11. The power supply method of claim 5, further comprising:

boosting the output voltage of the charged super capacitor to obtain a lock body power supply matching voltage;

and selecting a higher voltage in the normally-supplied input voltage and the lock body power supply matching voltage as a lock body power supply voltage to be output, wherein the lock body power supply voltage is used for controlling a lock body motor of the intelligent door.

12. The power supply method according to claim 11, wherein the step-up of the output voltage after the charging of the super capacitor is implemented by using a second step-up chip and a peripheral circuit matched with the second step-up chip to obtain a lock body power supply matching voltage; the second boost chip comprises a control pin connected with a lock body motor control enabling end, and the lock body motor control enabling end is controlled by the MCU.

13. The power supply method according to claim 11, wherein the selection of the higher voltage of the constant power supply input voltage and the lock body power supply matching voltage is implemented by using a second schottky diode, a third MOS transistor, a third current limiting resistor, a third pull-down resistor, a third capacitor and a fourth capacitor; wherein the content of the first and second substances,

the anode of the second Schottky diode is connected with a constant power supply input voltage end, and the cathode of the second Schottky diode is connected with a lock body power supply end; the third capacitor and the fourth capacitor are connected between the power supply end and the grounding end of the lock body in parallel; the third current limiting resistor and the third pull-down resistor are connected in series between the input voltage end of the normal power supply and the grounding end; the drain electrode of the third MOS tube is connected with a lock body power supply matching voltage end, the grid electrode of the third MOS tube is connected with the connection point of the third current limiting resistor and the third pull-down resistor, and the source electrode of the third MOS tube is connected with the lock body power supply end; the lock power supply matching voltage end inputs the lock power supply matching voltage, and the lock power supply end outputs the lock power supply voltage.

14. The power supply method according to claim 5, wherein the charging matching voltage of the super capacitor is larger than the emergency charging voltage when the normal power supply system supplies power normally.

15. The power supply method according to claim 5, wherein when the normal power supply system supplies power normally, the MCU power supply matching voltage is greater than the maximum output voltage of the super capacitor after being fully charged and is less than the super capacitor charging matching voltage.

16. The power supply method of claim 11, wherein the lock body power supply matching voltage is less than the constant power supply input voltage when a constant power supply system is normally powered.