CN113097302B - Transistor and manufacturing method thereof - Google Patents
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- CN113097302B CN113097302B CN202010022665.8A CN202010022665A CN113097302B CN 113097302 B CN113097302 B CN 113097302B CN 202010022665 A CN202010022665 A CN 202010022665A CN 113097302 B CN113097302 B CN 113097302B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
The invention relates to a transistor and a manufacturing method thereof, wherein the manufacturing method of the transistor comprises the following steps: providing a substrate, wherein an active region, an isolation structure, a word line groove and a gate oxide layer are formed in the substrate, sequentially forming a work function layer and a word line metal layer in the word line groove, testing the depth of a grid groove, filling an insulating layer in the word line groove, finally selecting corresponding ion implantation process parameters according to the depth of the grid groove, and implanting ions with set conductivity types into the substrate on two sides of the word line groove. The invention adjusts the depth of ion implantation in the source region and the drain region and the carrier concentration of the implantation region by changing the process parameters of the ion implantation, thereby reducing the influence of the depth of a grid groove on the driving current of the transistor, avoiding the driving current error caused by the fluctuation of the word line processing process parameters and forming the transistor with stable performance.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a transistor and a manufacturing method thereof.
Background
The dynamic random access memory is a semiconductor memory device commonly used by computers, and comprises a plurality of repeated memory units, each memory unit comprises a transistor and a memory capacitor connected with the transistor, the memory units are arranged in an array mode, and each memory unit is electrically connected with a bit line through a word line. With the continuous development of electronic products, the dynamic random access memory is also continuously developed to the requirements of high integration and high density, so that the word line embedded dynamic random access memory is derived.
For the word line embedded dram, in the process of back etching the word line metal of the transistor, due to the influence of environmental factors such as voltage, temperature, gas source, etc., variations in process parameters such as etching gas ratio, etching time, etc. inevitably occur, so that the actual depth of the word line metal is not the same as the design depth, and the variation in depth of the word line metal causes the variation in the conductive channel of the transistor, thereby affecting the performance stability of the transistor and the dram.
Disclosure of Invention
Therefore, it is necessary to provide a transistor and a method for manufacturing the same, in which the device performance is less affected by the variation of the process parameters and has stable performance, in order to solve the problem that the variation of the process parameters causes the variation of the conductive channel, which further affects the device performance stability of the transistor and the dram.
In order to realize the purpose of the invention, the invention adopts the following technical scheme:
a method of fabricating a transistor, comprising:
providing a substrate, wherein an active region, an isolation structure, a word line groove and a gate oxide layer are formed in the substrate;
sequentially forming a work function layer and a word line metal layer in the word line groove;
obtaining the depth of a grid groove;
filling an insulating layer in the word line groove;
and implanting ions into the substrate on two sides of the word line groove according to the depth of the grid electrode groove.
In one embodiment, the step of implanting ions into the substrate on both sides of the word line trench according to the depth of the gate recess includes:
acquiring the ion implantation depth according to the depth of the grid groove;
acquiring the energy and the dose of ion implantation according to the ion implantation depth;
implanting ions in the substrate according to the energy and dose of the ion implantation.
In one embodiment, the energy of the ion implantation is related to the gate recess depth.
In one embodiment, the ion implantation dose is related to the gate recess depth.
In one embodiment, the step of implanting ions into the substrate includes:
forming a light resistance layer on the surface of the substrate;
exposing and developing the photoresist layer to expose a device region in the substrate;
performing ion implantation on the device region;
and removing the residual photoresist layer.
In one embodiment, the step of sequentially forming a work function layer and a word line metal layer in the word line trench includes:
forming a work function layer at the bottom and the side wall of the word line groove;
filling a word line metal layer in the word line groove;
and etching back the work function layer and the word line metal layer with set depth.
In one embodiment, the step of filling the insulating layer in the word line trench includes;
depositing an insulating material layer in the word line groove and on the surface of the substrate;
removing part of the insulating material layer by using a chemical mechanical polishing or dry etching process, keeping the insulating material layer with a set thickness on the surface of the substrate, and taking the rest insulating material layer as an initial insulating layer;
and removing the initial insulating layer on the surface of the substrate by using a wet etching process, wherein the rest initial insulating layer is used as the insulating layer.
In one embodiment, before the step of filling the insulating layer in the word line trench, the method further includes: and forming a leakage restraining layer with a set thickness in the word line groove.
In one embodiment, after the step of implanting ions into the substrate on both sides of the word line trench, the method further includes:
forming a gate oxide layer in the peripheral circuit region;
and forming a grid polycrystalline silicon layer on the surface of the substrate.
The technical scheme of the invention also provides a transistor which is formed by adopting the transistor manufacturing method, and the doping depth and dosage of a source region and a drain region of the transistor are related to the depth of a grid groove.
The transistor manufacturing method comprises the steps of forming a work function layer and a word line metal layer in a word line groove of a substrate, testing the depth of a grid electrode groove, filling an insulating layer in the word line groove, and finally selecting corresponding ion implantation process parameters according to the depth of the grid electrode groove. The invention adjusts the ion implantation depth in the source region and the drain region and the carrier concentration of the implantation region by changing the ion implantation process parameters, thereby reducing the influence of the depth of the grid electrode groove on the drive current of the transistor, avoiding the drive current error caused by the fluctuation of the word line processing process parameters and improving the performance stability of the transistors in different batches.
Drawings
FIG. 1 is a flow diagram of a method of fabricating a transistor in one embodiment;
FIG. 2 is a schematic top view of a substrate with active regions and isolation structures formed therein in one embodiment;
FIG. 3 is a schematic cross-sectional view of the substrate along the A-A direction in the embodiment of FIG. 2;
FIG. 4 is a schematic top view of a substrate after formation of a gate oxide layer in one embodiment;
FIG. 5 is a schematic cross-sectional view of the substrate in the embodiment of FIG. 4 along the direction B-B;
FIG. 6 is a schematic diagram illustrating a transistor structure after an etch-back process in one embodiment;
FIG. 7 is an enlarged partial schematic view of a transistor in an embodiment;
FIG. 8 is an enlarged partial schematic view of a transistor in another embodiment;
FIG. 9 is an enlarged partial view of a transistor in a further embodiment;
FIG. 10 is a graph of gate recess depth measurements for a plurality of batches of transistors;
FIG. 11 is a graph of driving current versus gate recess depth in one embodiment;
FIG. 12 is a schematic diagram illustrating a transistor structure after depositing a layer of insulating material in one embodiment;
FIG. 13 is a schematic diagram illustrating the structure of a transistor after formation of an initial insulating layer in one embodiment;
FIG. 14 is a schematic diagram of a transistor structure after an insulating layer is formed in an embodiment;
FIG. 15 is a schematic diagram of a transistor structure including a leakage suppression layer in an embodiment;
FIG. 16 is a graph of drive current versus ion implant energy for arsenic doping in one embodiment;
fig. 17 is a schematic diagram of a transistor structure after ion implantation in an embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Fig. 1 is a flowchart of a method for manufacturing a transistor according to an embodiment, and as shown in fig. 1, the method for manufacturing a transistor includes:
s100: providing a substrate 100 in which an active region 110, an isolation structure 120, a word line trench 200 and a gate oxide layer 210 have been formed;
s200: sequentially forming a work function layer 220 and a word line metal layer 230 in the word line trench 200;
s300: obtaining the depth of a grid groove;
s400: filling an insulating layer 240 in the word line trench 200;
s500: ions are implanted into the substrate 100 at both sides of the word line trench 200 according to the depth of the gate recess.
The transistor manufacturing method provided in this embodiment can effectively improve the device degradation problem caused by the conventional manufacturing method, because in the conventional transistor manufacturing method, it is necessary to form the source region and the drain region in the substrate 100, and then form the word line trench 200, the gate oxide layer 210, the work function layer 220, and the word line metal layer 230, and the fluctuation of the process parameters when the work function layer 220 and the word line metal layer 230 are etched back can cause the change of the driving current, for example, the depth of the gate recess is increased by over-etching the word line metal layer 230, the length of the transistor conductive channel is shortened, and the driving current is reduced, and vice versa. Therefore, no matter whether the word line is over-etched or under-etched due to the fluctuation of the process parameters, the driving current of the transistor is changed, so that the threshold voltage and the switching characteristic of the transistor are influenced, and the performance of the transistor in different batches is unstable, deteriorated and even failed.
In this embodiment, the corresponding ion implantation process parameters are set according to the depth of the gate recess. In an example, if the depth of the gate recess is large, which indicates that the word line metal layer 230 is over-etched, the ion implantation parameters are adjusted, and the ion implantation depth in the source region and the drain region is increased or the carrier concentration in the implantation region is increased, so that the driving current of the transistor is increased, and the reduction of the driving current caused by over-etching is compensated, so that the driving current is stable and approaches to a set value, and the driving current error caused by the fluctuation of the word line preparation process parameters is avoided, thereby improving the performance stability of the transistors in different batches.
In step S100, the material of the substrate 100 may be monocrystalline silicon or polycrystalline silicon, and in this embodiment, the substrate 100 is a P-type doped polycrystalline silicon substrate 100. In this embodiment, as shown in fig. 2 to fig. 3, an active region 110 and an isolation structure 120 are first formed in the substrate, where the active region 110 is used to form a transistor device in a subsequent process, and the isolation structure 120 is used to separate adjacent active regions 110, so as to prevent a leakage current from being generated between the adjacent active regions 110.
After the isolation structure 120 is formed, a patterned hard mask layer 300 as shown in fig. 4 to 5 may be formed on the substrate surface by deposition, exposure, etching, and other process processes, and the substrate 100 is etched through the patterned hard mask layer 300 to form the word line trench 200, in an example, the hard mask layer 300 is made of silicon nitride. As shown in fig. 4, the word line trenches 200 are arranged in parallel and at equal intervals, each of the active regions is divided into three parts by two word line trenches 200 for forming a drain and two sources, respectively, each of the word line trenches 200 is used for accommodating a word line metal layer 230 to form a gate of a transistor, and the depth of the word line trench 200 in the active region 110 is smaller than the depth of the word line trench 200 in the isolation structure 120. After the word line trench 200 is formed, the gate oxide layer 210 covers the bottom and the side wall of the word line trench 200, a U-shaped structure as shown in fig. 5 is formed, and the material of the gate oxide layer 210 includes, but is not limited to, one of silicon dioxide and silicon nitride. It should be noted that, in this embodiment, the process for forming the active region 110, the isolation structure 120, the word line trench 200 and the gate oxide layer 210 is not specifically limited, and the substrate 100 of the above structure formed by any method can be used in the transistor manufacturing method in this embodiment.
In step S200, in an embodiment, the step of sequentially forming the work function layer 220 and the word line metal layer 230 in the word line trench 200 includes:
forming a work function layer 220 on the bottom and sidewalls of the word line trench 200;
filling a word line metal layer 230 in the word line trench 200;
the work function layer 220 and the word line metal layer 230 are etched back to a set depth.
The work function layer 220 has a U-shaped structure covering the bottom and the sidewall of the word line trench 200, a groove for accommodating the word line metal layer 230 is disposed inside the work function layer 220, in an example, the work function layer 220 is made of titanium nitride, and the word line metal layer 230 is made of one of conductive metal materials such as tungsten, titanium, and nickel. Alternatively, the work function layer 220 and the word line metal layer 230 may be formed by an atomic layer deposition process or a plasma enhanced vapor deposition process.
Further, in the step of etching back the work function layer 220 and the word line metal layer 230 with a set depth, the hard mask layer 300 patterned on the surface of the substrate is used to etch back the work function layer 220 and the word line metal layer 230, and the work function layer 220 and the word line metal layer 230 deposited on the surface of the hard mask layer 300 are sufficiently removed in the etching back process.
As shown in fig. 6, which is a schematic diagram of a transistor structure after etching back, in this embodiment, a dry etching process is used to etch back the work function layer 220 and the word line metal layer 230, etching gases used in the dry etching process include, but are not limited to, chlorine, sulfur hexafluoride, and argon, the chlorine is mainly used to etch the work function layer 220, the sulfur hexafluoride is mainly used to etch the word line metal layer 230, the argon is a protective gas, and an etching speed of the dry etching process can be adjusted.
Further, since the etching rates of the chlorine gas and the sulfur hexafluoride to different materials are different, the etching selection ratio of the etching gas can be changed by adjusting the gas flow rates of the chlorine gas and the sulfur hexafluoride, so as to realize the work function layer 220 and the word line metal layer 230 with different shapes, in this embodiment, the top of the word line metal layer 230 after etching back is arc-shaped and higher than the top of the work function layer 220, thereby improving the electrical performance of the transistor device. Meanwhile, due to the selectivity of the etching gas, the hard mask layer 300 is not etched in the dry etching process, so that the hard mask layer 300 is prevented from falling off, and the substrate 100 is prevented from being damaged by the etching gas.
Before step S300, if the material of the hard mask layer 300 is different from the material of the insulating layer 240 to be filled, the method further includes a step of removing the hard mask layer 300, because the etching methods of different materials are different, the method of removing the hard mask layer 300 first is adopted, so that the process difficulty in subsequently etching the insulating layer 240 can be reduced; if the material of the hard mask layer 300 is the same as the material of the insulating layer 240 to be filled, the hard mask layer 300 may not be removed, thereby reducing one process and improving the manufacturing efficiency.
In step S300, an optical proximity dimension (opc) machine manufactured by kola corporation is used to obtain a distance between the top of the word line metal layer 230 and the surface of the substrate 100, which is defined as a depth of the gate recess. Fig. 7-9 are enlarged partial views of the structure within the dashed line box of fig. 6, and fig. 7 is an enlarged partial view of a transistor structure with a proper gate recess depth Z0; FIG. 8 is an enlarged view of a portion of an underetched transistor structure with a gate recess depth Z1; fig. 9 is an enlarged view of a portion of the over-etched transistor structure, with the gate recess depth Z2.
In transistor design, the depth of the gate recess needs to be matched with the doping depth of the drain region 500 and the source region 600 to obtain the required driving current performance, and as known from the foregoing background art, the fluctuation of the process parameters in the transistor manufacturing process can cause the depth of the gate recess to change, so that there is a certain deviation between the actual driving current and the designed driving current. For example, using a conventional processing method of forming a source/drain doped region first and then forming a word line metal layer 230, if transistor devices with a design depth of 64.5nm are manufactured in batches, a test result of testing an actual depth of a gate recess using an optical proximity dimension (OPC) tool is shown in fig. 10, the actual depths of the gate recesses of the transistor devices in batches are distributed in a range of 58nm to 72nm, and approximately Gaussian distribution is obeyed by taking 64.5nm as a central axis, and a standard deviation of the depths of the gate recesses of the transistor devices in batches is 2nm according to a data statistics result. Under the premise of this standard deviation, if the transistor is continuously manufactured with the doping depths of the drain region 500 and the source region 600 kept unchanged, the driving current of the device has an error of 6% (about 0.66uA) at one standard deviation (2nm), and has an error of at least 10% (about 1.1uA) at two standard deviations (4nm), as shown in fig. 11, which is a graph of the driving current of the device versus the depth of the gate recess. Since the conventional manufacturing method may cause a large error in the driving current of the device, which may affect the electrical performance of the transistor device, an optical proximity dimension (opc) machine is required to obtain the accurate depth of the gate recess, so as to obtain the more accurate doping depths of the drain region 500 and the source region 600 according to the depth of the gate recess in the subsequent steps, and perform corresponding ion implantation.
In step S400, the step of filling the word line trench 200 with the insulating layer 240 includes;
depositing an insulating material layer 241 in the word line trench 200 and on the surface of the substrate;
removing part of the insulating material layer 241 by using a chemical mechanical polishing or dry etching process, so that the insulating material layer 241 with a set thickness is remained on the surface of the substrate 100, and the remaining insulating material layer 241 is used as an initial insulating layer 242;
a wet etching process is used to remove the initial insulating layer 242 on the surface of the substrate 100, and the remaining initial insulating layer 242 serves as the insulating layer 240.
The insulating layer 240 is used to reduce leakage current of the device and improve electrical performance of the transistor, as shown in fig. 12, which is a schematic structural diagram of the transistor after an insulating material layer 241 is deposited in the word line trench 200 and on the substrate surface. As shown in fig. 13, in this embodiment, a portion of the insulating material 241 is removed by a chemical mechanical polishing or dry etching process, so that the thickness of the insulating material layer 241 on the surface of the substrate 100 is reduced, and the insulating material layer 241 with a thickness of 5nm to 10nm is remained as the initial insulating layer 242. Finally, as shown in fig. 14, the initial insulating layer 242 on the surface of the substrate 100 is removed by using a wet etching process to form the insulating layer 240. The method of the present embodiment can ensure the etching speed, and at the same time, prevent the structure on the surface of the substrate 100 from being damaged by the chemical mechanical polishing or the plasma etching, and avoid the device structure from being defective or even failing, thereby improving the processing yield of the transistor device. In one example, the material of the insulating layer 240 is silicon nitride.
In an embodiment, before the step of filling the insulating layer 240 in the word line trench 200, the method further includes: a leakage suppression layer 250 of a set thickness is formed within the word line trench 200 (as shown in fig. 15). In the conventional transistor device structure, the work function difference between the Drain region 500, the source region 600 and the word line metal is large, and when the transistor is in an off state, an excessive band bending exists on the interface of the Drain region 500, the source region 600 and the Gate, so that tunneling easily occurs to form a Drain Leakage current, i.e., a Gate-Induced Drain Leakage current (GIDL) effect. In the present embodiment, by providing the leakage current suppressing layer 250 with a low work function, the leakage current caused by the high potential barrier between the drain region 500, the source region 600 and the word line metal layer 230 is suppressed, so that not only the signal reading error caused by the GIDL effect can be reduced, but also the operating speed of the memory cell can be effectively increased. In one example, the leakage current suppressing layer 250 is made of polysilicon and has a thickness of 5nm to 30 nm.
In step S500, the step of implanting ions into the substrate 100 on both sides of the word line trench 200 according to the depth of the gate recess includes:
acquiring the ion implantation depth according to the depth of the grid groove;
acquiring the energy and the dose of ion implantation according to the ion implantation depth;
implanting ions in the substrate according to the energy and dose of the ion implantation.
The depth threshold is the designed value Z0 of the gate recess depth, in this embodiment, the optimal gate recess depth and the designed value of the doping depth of the drain region 500 and the source region 600 are determined, and obtaining proper actual ion implantation depth according to the depth of the gate groove, selecting corresponding ion implantation energy and dose, thereby obtaining the best driving current compensation effect, for example, when the design value of the depth of the gate groove Z0 is 64.5nm, the corresponding driving current is 11.3uA, but the actual depth of the gate recess is 65nm, the corresponding drive current is about 11.2uA, 0.1uA less than the design value of drive current, in this embodiment, the driving current can be compensated by adjusting the actual doping depth of the drain region 500 and the source region 600, so that the driving current is increased by 0.1uA to 11.3uA, therefore, the error of the driving current is reduced, and the transistors in different batches can obtain stable driving current performance.
In one example, the conductivity type of the substrate 100 is P-type, the implanted ions are arsenic ions, and further, the step of implanting ions in the substrate 100 includes:
forming a photoresist layer on the surface of the substrate 100;
exposing and developing the photoresist layer to expose a device region in the substrate 100;
carrying out ion implantation on the device region;
and removing the residual photoresist layer.
In this embodiment, a device region in the substrate 100, i.e., a region to be ion-implanted, is opened, and the substrate 100 is ion-implanted in a direction perpendicular to the substrate 100. When the substrate 100 is subjected to ion implantation, the energy of the ion implantation is related to the depth of the gate recess, that is, when the depth of the gate recess is smaller than the depth threshold, the actual driving current is larger than the designed value of the driving current, and the actual driving current needs to be reduced by an ion implantation compensation method, so that the energy or dose of the ion implantation is reduced, and the doping concentration or doping depth of the drain region 500 and the source region 600 is reduced; when the depth of the gate recess is greater than the depth threshold, the actual driving current is smaller than the design value of the driving current, and the actual driving current needs to be increased by an ion implantation compensation method, so that the ion implantation energy or dose is increased, and the doping concentration or doping depth of the drain region 500 and the source region 600 is increased, thereby achieving the purpose of compensating the driving current.
Further, fig. 16 is a graph of the driving current-ion implantation energy using arsenic doping in the present embodiment, and as shown in fig. 16, the driving current and the ion implantation energy satisfy the following relationship: for every 1KeV increase of the energy of arsenic ion implantation, the driving current is correspondingly increased by about 0.3 uA; as can be seen from the foregoing discussion of the gate recess depth and the driving current, the driving current and the gate recess depth satisfy the following relationship: for every 1nm increase in gate recess depth, the drive current decreases by about 0.2 uA. Therefore, in this embodiment, for each 1nm change in the depth of the gate recess, the energy of the ion implantation changes by 0.67KeV accordingly, which is a preferred ion implantation parameter, so as to obtain the best driving current compensation effect, and fig. 17 is a schematic diagram of the transistor structure after the ion implantation in one embodiment.
In an embodiment, after the step of implanting ions into the substrate 100 on both sides of the word line trench 200, the method further includes:
forming a gate oxide layer in the peripheral circuit region;
a gate polysilicon layer is formed on the surface of the substrate 100.
The gate oxide layer and the gate polysilicon layer of the peripheral circuit are used for connecting bit line regions of transistor devices of the memory unit so as to control data stored/fetched by the memory unit.
In one embodiment, there is also provided a transistor having a device structure as shown in fig. 17, which is formed by the method for manufacturing the transistor as described above, and the doping depth of the drain region 500 and the source region 600 of the transistor is related to the depth of the gate recess. The influence of the depth of the grid electrode groove on the driving current of the transistor in the embodiment is small, the fluctuation of the word line processing technological parameters cannot cause the change of the driving current, and the transistor is stable in performance.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for manufacturing a transistor is characterized by comprising the following steps:
providing a substrate, wherein an active region, an isolation structure, a word line groove and a gate oxide layer are formed in the substrate;
sequentially forming a work function layer and a word line metal layer in the word line groove;
obtaining the depth of a grid electrode groove, wherein the depth of the grid electrode groove is the distance between the top of the word line metal layer and the surface of the substrate;
filling an insulating layer in the word line groove;
when the depth of the grid electrode groove is smaller than a set value, reducing the energy or dosage of ion implantation, and implanting ions into the substrate on two sides of the word line groove to form a source electrode region and/or a drain electrode region; and when the depth of the grid electrode groove is greater than a set value, improving the energy or dosage of ion implantation, and implanting ions into the substrate at two sides of the word line groove to form a source electrode region and/or a drain electrode region.
2. The method for fabricating a transistor according to claim 1, wherein the step of implanting ions into the substrate on both sides of the word line trench comprises:
acquiring the ion implantation depth according to the depth of the grid groove;
acquiring the energy and/or dose of ion implantation according to the ion implantation depth;
implanting ions in the substrate according to the energy and/or dose of the ion implantation.
3. The method of claim 2, wherein an energy of said ion implantation is related to a depth of said gate recess.
4. The method of claim 2, wherein a dose of said ion implantation is related to a depth of said gate recess.
5. The method of claim 2, wherein the step of implanting ions into the substrate comprises:
forming a light resistance layer on the surface of the substrate;
exposing and developing the photoresist layer to expose a device region in the substrate;
performing ion implantation on the device region;
and removing the residual photoresist layer.
6. The method of claim 1, wherein the step of sequentially forming a work function layer and a word line metal layer in the word line trench comprises:
forming a work function layer at the bottom and the side wall of the word line groove;
filling a word line metal layer in the word line groove;
and etching back the work function layer and the word line metal layer with set depth.
7. The method for manufacturing a transistor according to claim 1, wherein the step of filling the word line trench with an insulating layer comprises;
depositing an insulating material layer in the word line groove and on the surface of the substrate;
removing part of the insulating material layer by using a chemical mechanical polishing or dry etching process, keeping the insulating material layer with a set thickness on the surface of the substrate, and taking the rest insulating material layer as an initial insulating layer;
and removing the initial insulating layer on the surface of the substrate by using a wet etching process, wherein the rest initial insulating layer is used as the insulating layer.
8. The method of claim 1, further comprising, before the step of filling the word line trench with an insulating layer: and forming a leakage restraining layer with a set thickness in the word line groove.
9. The method for fabricating a transistor according to claim 1, wherein after the step of implanting ions into the substrate on both sides of the word line trench, the method further comprises:
forming a gate oxide layer in the peripheral circuit region;
and forming a grid polycrystalline silicon layer on the surface of the substrate.
10. A transistor formed by the method of any one of claims 1 to 9, wherein the doping depth and dose of the source and drain regions of the transistor are related to the depth of the gate recess.
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| CN104617140A (en) * | 2013-11-04 | 2015-05-13 | 南亚科技股份有限公司 | Recessed channel access transistor device and fabrication method thereof |
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| CN103872129A (en) * | 2012-12-18 | 2014-06-18 | 爱思开海力士有限公司 | Semiconductor device and fabrication method thereof |
| CN104617140A (en) * | 2013-11-04 | 2015-05-13 | 南亚科技股份有限公司 | Recessed channel access transistor device and fabrication method thereof |
| CN104810390A (en) * | 2014-01-29 | 2015-07-29 | 爱思开海力士有限公司 | Transistor having dual work function buried gate electrode and method for fabricating the same |
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