CN113097265B - Display panel and preparation method thereof - Google Patents
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- CN113097265B CN113097265B CN202110331143.0A CN202110331143A CN113097265B CN 113097265 B CN113097265 B CN 113097265B CN 202110331143 A CN202110331143 A CN 202110331143A CN 113097265 B CN113097265 B CN 113097265B
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 409
- 239000011229 interlayer Substances 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 230000001154 acute effect Effects 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 230000003028 elevating effect Effects 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000005192 partition Methods 0.000 claims description 24
- 238000002161 passivation Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 17
- 239000011810 insulating material Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 239000007769 metal material Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 18
- 239000010408 film Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 10
- 238000000926 separation method Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
Abstract
The invention provides a display panel and a preparation method thereof, wherein the display panel comprises: a substrate, a thin film transistor layer, a spacer layer, an interlayer insulating layer, a spacer layer, an OLED device, and a cathode. According to the invention, the isolation layer is prepared by arranging the raised layer in the non-display area and arranging the first groove, and the side of the isolation layer, which is far away from the raised layer, is provided with the first inverted acute angle area, so that the isolation layer can isolate the OLED device, and the OLED device is prevented from contacting the auxiliary cathode, so that the OLED device is regionalized. And the pad layer and the isolation layer are prepared together with the existing film layer, so that unnecessary preparation procedures are avoided.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
For organic light-Emitting Diode (OLED) devices, microcavity structures are used in order to improve the light-Emitting efficiency of the OLED, but most of them use a semitransparent cathode structure. However, semitransparent cathodes have a large resistance and can cause a severe voltage Drop (IR Drop), which affects the uniformity of the overall screen display, especially for large-size OLEDs.
To improve the IR Drop of an OLED display, it is common practice to manufacture an auxiliary cathode, and to contact the semi-transparent cathode with the auxiliary cathode to reduce the cathode area resistance. For the vapor deposition process, the vapor deposition angular deviation is utilized to achieve that the vapor deposition OLED material cannot cover the auxiliary cathode contact area by preparing a special auxiliary cathode structure. However, it is difficult to realize the OLED material regionalization for the printing process. .
Therefore, there is an urgent need to develop a new display panel to maintain the positive effects of the existing display panel while eliminating the negative effects of the existing display panel.
Disclosure of Invention
The invention aims to provide a display panel and a preparation method thereof, wherein a separation layer is prepared in a non-display area, and a first inverted acute angle area is arranged on one side of the separation layer far away from a pad layer, so that the separation layer can separate an OLED device and prevent the OLED device from contacting an auxiliary cathode.
In order to achieve the above object, the present invention provides a display panel defining a display area and a non-display area, wherein the display panel includes: a substrate; the thin film transistor layer is arranged on the substrate and corresponds to the display area; the pad layer is arranged on the substrate and corresponds to the non-display area; the interlayer insulating layer is arranged on the pad layer and provided with a first groove; a partition layer which is arranged on the interlayer insulating layer and fills the first groove, wherein one side of the partition layer, which is far away from the pad layer, is provided with a first reverse acute angle area; the OLED devices are arranged on the thin film transistor layer and the isolation layer, the OLED devices are isolated by the isolation layer, and part of the OLED devices are arranged between the display area and the non-display area; and a cathode disposed on the OLED device and connected to the auxiliary cathode of the non-display region.
Further, the elevating layer includes: a first elevating block; the second heightening block is arranged on the first heightening block; and the third heightening block is arranged on the second heightening block.
Further, the partition layer is provided with a second groove corresponding to the first groove; the display panel further includes: the protective layer is arranged on the pad layer and fills the second groove, and the protective layer is provided with a third groove corresponding to the second groove; and a first planarization layer disposed between the protection layer and the OLED device and filling the third recess.
Further, a side of the protective layer away from the isolating layer is provided with a second reverse acute angle area.
Further, the partition layer and the third elevating block are the auxiliary cathode; the partition layer and the third elevating block are made of metal conductive materials.
Further, the thin film transistor layer includes: a light shielding layer disposed on the substrate; the buffer layer is arranged on the shading layer and the substrate; a semiconductor layer disposed on the buffer layer; a gate insulating layer disposed on the semiconductor layer; the grid electrode layer is arranged on the grid electrode insulating layer; the interlayer insulating layer extends to the display area and is arranged on the buffer layer, and the semiconductor layer and the grid layer are covered by the interlayer insulating layer of the display area; a source-drain electrode layer provided on the interlayer insulating layer; a passivation layer disposed on the interlayer insulating layer and covering the source/drain electrode layer; and the flattening layer is arranged on the passivation layer.
Further, the first elevating block and the light shielding layer are arranged on the same layer, and the first elevating block and the light shielding layer are made of the same material; and/or the second elevating block and the gate insulating layer are arranged on the same layer, and the second elevating block and the gate insulating layer are made of the same material; and/or the third elevating block and the gate layer are arranged in the same layer, and the third elevating block and the gate layer are made of the same material; and/or the isolation layer is arranged on the same layer as the source-drain electrode layer, and the isolation layer is made of the same material as the source-drain electrode layer.
Further, the first planarization layer and the planarization layer are arranged in the same layer, and the first planarization layer and the planarization layer are made of the same material; and/or the passivation layer and the protective layer are arranged on the same layer, and the passivation layer and the protective layer are made of the same material.
Further, the buffer layer extends to the non-display area and covers the first elevating block, and the buffer layer of the non-display area is arranged between the first elevating block and the second elevating block.
The invention provides a preparation method of a display panel, which comprises the following steps: providing a substrate, which is defined with a display area and a non-display area; forming a shading layer and a first raising block on the substrate through the same photomask; forming a buffer layer on the substrate, the shading layer and the first elevating block; forming a semiconductor layer on the buffer layer of the display area; firstly, depositing an insulating material on the buffer layer and the semiconductor layer, then depositing a first metal material on the insulating material, and forming a grid electrode and a third pad through the same photomask; finally, etching the insulating material to form the gate insulating layer and the second heightening block by taking the gate and the third heightening block as patterns; forming an interlayer insulating layer on the buffer layer, the grid electrode and the third elevating block, and forming a first groove corresponding to the third elevating block on the interlayer insulating layer, wherein the first groove is recessed to the upper surface of the third elevating block; and depositing a second metal material on the interlayer insulating layer, and forming a source-drain electrode layer and a partition layer through the same photomask, wherein the partition layer fills the first groove, and one side of the partition layer, which is far away from the third pad block, is provided with a first inverted acute angle area.
The invention has the beneficial effects that: according to the display panel and the preparation method thereof, the raised layer is arranged in the non-display area, the first groove is formed, the isolation layer is further prepared, the first inverted acute angle area is formed on one side of the isolation layer away from the raised layer, the OLED device can be isolated by the isolation layer, the OLED device is prevented from contacting the auxiliary cathode, and the OLED device is regionalized. And the pad layer and the isolation layer are prepared together with the existing film layer, so that unnecessary preparation procedures are avoided.
Drawings
The technical solution and other advantageous effects of the present invention will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of steps S1-S2 of a display panel manufacturing method according to another embodiment of the present invention;
FIG. 3 is a schematic structural diagram of steps S3-S5 of a display panel manufacturing method according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of step S6 of a method for manufacturing a display panel according to another embodiment of the invention;
fig. 5 is a schematic structural diagram of step S7 of a method for manufacturing a display panel according to another embodiment of the invention;
fig. 6 is a schematic structural diagram of step S8 of a method for manufacturing a display panel according to another embodiment of the invention;
fig. 7 is a schematic structural diagram of step S9 of a method for manufacturing a display panel according to another embodiment of the invention;
fig. 8 is a schematic structural diagram of steps S10 and S11 of a method for manufacturing a display panel according to another embodiment of the invention;
fig. 9 is a schematic structural diagram of step S12 of a method for manufacturing a display panel according to another embodiment of the invention;
fig. 10 is a schematic structural diagram of step S13 of a method for manufacturing a display panel according to another embodiment of the invention.
A substrate 101; a cathode 115; a raising layer 12;
an interlayer insulating layer 105; a barrier layer 124; an OLED device 114;
a light shielding layer 102; a buffer layer 103; a semiconductor layer 104;
a gate insulating layer 106; a gate layer 107; a display panel 100;
a source-drain electrode layer 109; a passivation layer 108; a planarization layer 111;
a first elevating block 121; a second elevating block 122; a third elevating block 123;
a first recess 1051; a first acute angle region 10; a second groove 1241;
a protective layer 125; a first planarization layer 126; a third groove 1251;
a display area 110; a non-display area 120; an isolation layer 113; slots 1131;
a first through hole 1052; a second through hole 1053; a third through hole 1054;
a first metal line 1091; a second metal line 1092; a second acute angle region 20.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
As shown in fig. 1, the present invention provides a display panel 100, which defines a display area 110 and a non-display area 120, wherein the display panel 100 includes: a substrate 101, a thin film transistor layer (not shown), a spacer layer 12, an interlayer insulating layer 105, a barrier layer 124, an OLED device 114, and a cathode 115.
The thin film transistor layer is disposed on the substrate 101 and corresponds to the display area 110; the pad layer 12 is disposed on the substrate 101 and corresponds to the non-display area 120; the interlayer insulating layer 105 is disposed on the pad layer 12 and has a first groove 1051; the partition layer 124 is disposed on the interlayer insulating layer 105 and fills the first groove 1051, and a side of the partition layer 124 away from the pad layer 12 has a first acute angle region 10; the OLED device 114 is disposed on the thin film transistor layer and the isolation layer 124, and the OLED device 114 is isolated by the isolation layer 124, and a portion of the OLED device 114 is disposed between the thin film transistor layer and the isolation layer 124; the cathode 115 is disposed on the OLED device 114 and is connected to an auxiliary cathode of the non-display region 120.
The present invention provides a display panel 100, wherein a spacer layer 12 is disposed in a non-display area 120, and a first groove 1051 is formed, so as to obtain a spacer layer 124, and a side of the spacer layer 124 away from the spacer layer 12 has a first inverted acute angle region 10, so that the spacer layer 124 can separate an OLED device 114, prevent the OLED device 114 from contacting an auxiliary cathode, and regionalize the OLED device 114 (i.e., three positions 114 in fig. 1 are marked). The first acute angle region 10 is a chamfer region formed between the upper surface of the partition layer 124 (i.e., the side away from the raised layer 12) and the side surface of the partition layer 124. Furthermore, the overall shape between the upper surface and the side surface of the first acute-angled region 10 can also be regarded as an inverted trapezoid structure.
Specifically, an embodiment of the present invention provides a display panel 100, which defines a display area 110 and a non-display area 120, wherein the display panel 100 includes: a substrate 101, a thin film transistor layer, a spacer layer 12, an interlayer insulating layer 105, a barrier layer 124, an anode, an OLED device 114, and a cathode 115.
The thin film transistor layer is disposed on the substrate 101 and corresponds to the display area 110; in one embodiment, the thin film transistor layer includes: a light shielding layer 102, a buffer layer 103, a semiconductor layer 104, a gate insulating layer 106, a gate layer 107, an interlayer insulating layer 105, a source-drain electrode layer 109, a passivation layer 108, and a planarization layer 111.
The light shielding layer 102 is disposed on the substrate 101, and the light shielding layer 102 is generally made of metal for preventing leakage of light. The buffer layer 103 is disposed on the light shielding layer 102 and the substrate 101; the material of the buffer layer 103 comprises an organic polymer for buffering. The semiconductor layer 104 is provided on the buffer layer 103; the semiconductor layer 104 material is an oxide material. The gate insulating layer 106 is disposed on the semiconductor layer 104; the material of the gate insulating layer 106 includes silicon oxide or silicon nitride. The gate electrode layer 107 is disposed on the gate insulating layer 106; the gate layer 107 is made of a metal material. The interlayer insulating layer 105 is provided on the buffer layer 103 to cover the semiconductor layer 104 and the gate layer 107. The material of the interlayer insulating layer 105 includes silicon oxide or silicon nitride. The source/drain electrode layer 109 is provided on the interlayer insulating layer 105; the source-drain electrode layer 109 is made of a metal material, the source-drain electrode layer 109 includes a first metal line 1091 and a second metal line 1092, and the first metal line 1091 penetrates through the interlayer insulating layer 105 to connect the semiconductor layer 104; one end of the second metal wire 1092 penetrates the interlayer insulating layer 105 to connect to the semiconductor layer 104, and one end of the second metal wire 1092 penetrates the interlayer insulating layer 105 and the buffer layer 103 to connect to the light shielding layer 102. The passivation layer 108 is provided on the interlayer insulating layer 105 and covers the source-drain electrode layer 109. The planarization layer 111 is disposed on the passivation layer 108, so as to make the structure of the film more flat.
The pad layer 12 is disposed on the substrate 101 and corresponds to the non-display area 120; the interlayer insulating layer 105 extends toward the non-display region 120 and is disposed on the pad layer 12, and the interlayer insulating layer 105 of the non-display region 120 has a first recess 1051. In this embodiment, the elevating layer 12 includes: a first elevating block 121, a second elevating block 122, and a third elevating block 123. The first raised block 121 is disposed on the same layer as the light shielding layer 102, and the first raised block 121 is made of the same material as the light shielding layer 102. The second raised block 122 is disposed on the first raised block 121, the second raised block 122 and the gate insulating layer 106 are disposed on the same layer, and the second raised block 122 and the gate insulating layer 106 are made of the same material. The third raised block 123 is disposed on the second raised block 122, the third raised block 123 and the gate layer 107 are disposed on the same layer, and the third raised block 123 and the gate layer 107 are made of the same material. The present invention avoids a new manufacturing process by manufacturing the first elevating block 121, the second elevating block 122, and the third elevating block 123 together with the film layer of the display area 110. In this embodiment, the buffer layer 103 of the display area 110 extends toward the non-display area 120 and covers the first raised block 121, and the buffer layer 103 of the non-display area 120 is disposed between the first raised block 121 and the second raised block 122.
The isolation layer 124 is disposed on the interlayer insulating layer 105 and fills the first groove 1051, and a side of the isolation layer 124 away from the pad layer 12 has a first acute angle region 10. The blocking layer 124 has a second groove 1241 corresponding to the first groove 1051. The display panel 100 further includes: the protection layer 125 and the first planarization layer 126. The protection layer 125 is disposed on the pad layer 12 and fills the second groove 1241, the protection layer 125 has a third groove 1251 corresponding to the second groove 1241, the passivation layer 108 and the protection layer 125 are disposed on the same layer, and the passivation layer 108 and the protection layer 125 are made of the same material, which avoids adding a new preparation process. The side of the protective layer 125 remote from the isolating layer 124 has a second acute angle region 20. The first planarization layer 126 is disposed between the protection layer 125 and the OLED device 114 and fills the third groove 1251, the first planarization layer 126 is used to improve the flatness of the non-display area 120, the first planarization layer 126 is disposed on the same layer as the planarization layer 111, and the first planarization layer 126 is made of the same material as the planarization layer 111, which avoids adding a new manufacturing process. The second acute angle region 20 refers to a chamfer region formed in an acute angle between the upper surface of the protective layer 125 (i.e., the side away from the isolating layer 124) and the side surface of the protective layer 125. In addition, the overall shape between the upper surface and the side surface of the second acute angle region 20 can also be regarded as an inverted trapezoid structure.
In the display region 110, the anode 112 is disposed on the planarization layer 111, and the anode 112 penetrates the planarization layer 111 downward and the passivation layer 108 to connect the source/drain electrode layer 109. In this embodiment, the display panel 100 further includes: the isolation layer 113 is disposed on the planarization layer 111 and covers the anode 112, the isolation layer 113 includes a slot 1131, and a portion of the anode 112 is exposed in the slot 1131.
In the display area 110, the OLED device 114 is disposed on the isolation layer 113 and fills the groove 1131; in the non-display region 120, the OLED device 114 is disposed on the blocking layer 124, and the OLED device 114 is blocked by the blocking layer 124, and a portion of the OLED device 114 is disposed between the display region 110 and the non-display region 120.
The cathode 115 is disposed on the OLED device 114 and is connected to an auxiliary cathode of the non-display region 120. In this embodiment, the partition layer 124 and the third spacer 123 are auxiliary cathodes. The isolating layer 124 and the third spacer 123 are made of metal conductive materials. The cathode 115 is attached to one end of the partition layer 124 so as to be connected to the auxiliary cathode. The OLED device 114 is printed using a printing technique, and the ink liquid is turned off after drying. Cathode 115 is typically formed by PVD (physical vapor deposition) with good coverage and also by evaporation, which is designed to allow cathode 115 to contact the auxiliary cathode metal.
The invention provides a display panel 100, wherein a spacer layer 12 is arranged in a non-display area 120, and a first groove 1051 is formed, so that a partition layer 124 is prepared, and one side of the partition layer 124 away from the spacer layer 12 is provided with a first inverted acute angle area 10, so that the partition layer 124 can partition an OLED device 114, prevent the OLED device 114 from contacting an auxiliary cathode, and enable the OLED device 114 to be regionalized.
Another embodiment of the present invention provides a method for manufacturing a display panel, for manufacturing the display panel 100 according to an embodiment, the method for manufacturing the display panel includes the following steps: s1 to S13.
S1, as shown in FIG. 2, a substrate 101 is provided, which defines a display area 110 and a non-display area 120.
S2, referring to FIG. 2, a metal material is deposited on the substrate 101, and the light shielding layer 102 and the first raised block 121 are formed by the same mask. The light shielding layer 102 is used for preventing leakage of light.
S3, as shown in FIG. 3, a buffer layer 103 is deposited on the substrate 101, the light shielding layer 102 and the first spacer 121. The material of the buffer layer 103 comprises an organic polymer for buffering.
S4, referring to fig. 3, a semiconductor layer 104 is formed on the buffer layer 103 of the display area 110, and the material of the semiconductor layer 104 is an oxide material.
S5, referring to FIG. 3, depositing an insulating material on the buffer layer 103 and the semiconductor layer 104, depositing a first metal material on the insulating material, and forming a gate and a third raised block 123 through the same mask; the gate insulating layer 106 and the second raised block 122 are formed by etching the insulating material with the gate and the third raised block 123 as patterns.
S6, as shown in FIG. 4, an insulating material is deposited on the buffer layer 103, the gate electrode and the third raised block 123 to form an interlayer insulating layer 105, and a first groove 1051 corresponding to the third raised block 123 is formed, wherein the first groove 1051 is recessed to the upper surface of the third raised block 123; a first via hole 1052, a second via hole 1053 and a third via hole 1054 are sequentially opened, wherein the first via hole 1052 penetrates through the interlayer insulating layer 105 to the left end of the semiconductor layer 104, the second via hole 1053 penetrates through the interlayer insulating layer 105 to the right end of the semiconductor layer 104, and the third via hole 1054 penetrates through the interlayer insulating layer 105 and the buffer layer 103 to the light shielding layer 102.
S7, as shown in fig. 5, a second metal material is deposited on the interlayer insulating layer 105, and the source-drain electrode layer 109 and the isolation layer 124 are formed by the same photomask, the isolation layer 124 fills the first groove 1051, a side of the isolation layer 124 away from the raised layer 12 has a first acute angle region 10, and the isolation layer 124 has a second groove 1241 corresponding to the first groove 1051. The source/drain electrode layer 109 includes a first metal line 1091 and a second metal line 1092, and the first metal line 1091 penetrates the interlayer insulating layer 105 to connect the semiconductor layer 104; one end of the second metal wire 1092 penetrates the interlayer insulating layer 105 to connect to the semiconductor layer 104, and one end of the second metal wire 1092 penetrates the interlayer insulating layer 105 and the buffer layer 103 to connect to the light shielding layer 102.
S8, as shown in FIG. 6, a passivation layer 108 and a passivation layer 125 are formed on the interlayer insulating layer 105, the source/drain electrode layer 109 and the isolation layer 124 by depositing an insulating material. The passivation layer 108 is provided on the interlayer insulating layer 105 and covers the source-drain electrode layer 109. The protection layer 125 is disposed on the raised layer 12 and fills the second groove 1241, and the protection layer 125 has a third groove 1251 corresponding to the second groove 1241. The side of the protective layer 125 remote from the isolating layer 124 has a second acute angle region 20.
S9, as shown in FIG. 7, a planarization material is deposited on the passivation layer 108 and the passivation layer 125 to form a first planarization layer 126 and a planarization layer 111, wherein the first planarization layer 126 and the planarization layer 111 are separated by the second acute angle region 20. The planarization layer 111 is disposed on the passivation layer 108. The first planarization layer 126 is disposed on the protection layer 125.
S10, as shown in fig. 8, an anode is formed on the planarization layer 111, and the anode penetrates through the planarization layer 111 and the passivation layer 108 downwards to connect to the source/drain electrode layer 109, specifically to connect to the second metal line 1092.
S11, as shown in FIG. 8, a spacer 113 is formed on the planarization layer 111 and covers the anode, wherein the spacer 113 includes a slot 1131, and a portion of the anode is exposed in the slot 1131.
S12, as shown in FIG. 9, the OLED material is printed on the isolation layer 113 and the first flat layer 126 in an inkjet manner and fills the grooves 1131 to form OLED devices 114, and in the display area 110, the OLED devices 114 are arranged on the isolation layer 113 and fill the grooves 1131; in the non-display region 120, the OLED device 114 is disposed on the blocking layer 124, and the OLED device 114 is blocked by the blocking layer 124, and a portion of the OLED device 114 is disposed between the display region 110 and the non-display region 120.
S13, as shown in FIG. 10, depositing a metal material on the whole surface of the display area 110 and the non-display area 120 to form a cathode 115; the cathode 115 is typically PVD (physical vapor deposition) and has good coverage, and the cathode 115 is attached to one end of the separator 124 to connect the auxiliary cathode.
The preparation method has the beneficial effects that: the invention provides a preparation method of a display panel, which is characterized in that a spacer layer 12 is arranged in a non-display area 120, and a first groove 1051 is formed, so that a separation layer 124 is prepared, and one side of the separation layer 124 away from the spacer layer 12 is provided with a first inverted acute angle area 10, so that the separation layer 124 can separate an OLED device 114, and the OLED device 114 is prevented from contacting an auxiliary cathode, so that the OLED device 114 is regionalized. And both the lift-off layer 12 and the barrier layer 124 are fabricated with existing film layers, avoiding unnecessary fabrication processes.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of the above examples is only for aiding in understanding the technical solution of the present invention and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (7)
1. A display panel defining a display area and a non-display area, the display panel comprising:
a substrate;
the thin film transistor layer is arranged on the substrate and corresponds to the display area;
the pad layer is arranged on the substrate and corresponds to the non-display area;
the interlayer insulating layer is arranged on the pad layer and provided with a first groove;
a partition layer which is arranged on the interlayer insulating layer and fills the first groove, wherein one side of the partition layer, which is far away from the pad layer, is provided with a first reverse acute angle area;
the OLED devices are arranged on the thin film transistor layer and the isolation layer, the OLED devices are isolated by the isolation layer, and part of the OLED devices are arranged between the display area and the non-display area; and
a cathode electrode disposed on the OLED device and connected to the auxiliary cathode electrode of the non-display region;
the elevating layer comprises:
the first heightening block is arranged on the substrate;
the second heightening block is arranged on the first heightening block; and
the third heightening block is arranged on the second heightening block;
wherein, the partition layer is provided with a second groove corresponding to the first groove;
the display panel further includes:
the protective layer is arranged on the pad layer and fills the second groove, and the protective layer is provided with a third groove corresponding to the second groove; and
the first flat layer is arranged between the protective layer and the OLED device and fills the third groove, the first flat layer and the protective layer are provided with acute angle areas, the part of the cathode located in the display area is directly connected with the part of the cathode located in the non-display area, and the isolation layer and the third heightening block are the auxiliary cathode; the third elevating block is arranged on the same layer as the gate layer, the third elevating block is made of the same material as the gate layer, the isolating layer is arranged on the same layer as the source drain electrode layer, the isolating layer is made of the same material as the source drain electrode layer, and the isolating layer and the third elevating block are made of metal conductive materials.
2. The display panel of claim 1, wherein,
the side of the protective layer far away from the isolating layer is provided with a second reverse acute angle area.
3. The display panel of claim 1, wherein,
the thin film transistor layer includes:
a light shielding layer disposed on the substrate;
the buffer layer is arranged on the shading layer and the substrate;
a semiconductor layer disposed on the buffer layer;
a gate insulating layer disposed on the semiconductor layer;
the grid electrode layer is arranged on the grid electrode insulating layer;
the interlayer insulating layer extends to the display area and is arranged on the buffer layer, and the semiconductor layer and the grid layer are covered by the interlayer insulating layer of the display area;
a source-drain electrode layer provided on the interlayer insulating layer;
a passivation layer disposed on the interlayer insulating layer and covering the source/drain electrode layer; and
and the flattening layer is arranged on the passivation layer.
4. The display panel of claim 3, wherein,
the first elevating block and the light shielding layer are arranged on the same layer, and the first elevating block and the light shielding layer are made of the same material; and/or the number of the groups of groups,
the second elevating block and the gate insulating layer are arranged on the same layer, and the second elevating block and the gate insulating layer are made of the same material.
5. The display panel of claim 3, wherein,
the first planarization layer and the planarization layer are arranged in the same layer, and the first planarization layer and the planarization layer are made of the same material; and/or the number of the groups of groups,
the passivation layer and the protective layer are arranged on the same layer, and the passivation layer and the protective layer are made of the same material.
6. The display panel of claim 3, wherein,
the buffer layer extends to the non-display area and covers the first heightening block, and the buffer layer of the non-display area is arranged between the first heightening block and the second heightening block.
7. A method for manufacturing a display panel, wherein the display panel according to any one of claims 1 to 6 is manufactured, the method comprising the steps of:
providing a substrate, which is defined with a display area and a non-display area;
forming a shading layer and a first raising block on the substrate through the same photomask;
forming a buffer layer on the substrate, the shading layer and the first elevating block;
forming a semiconductor layer on the buffer layer of the display area;
firstly, depositing an insulating material on the buffer layer and the semiconductor layer, then depositing a first metal material on the insulating material, and forming a grid electrode and a third pad through the same photomask; finally, etching the insulating material to form a gate insulating layer and the second heightening block by taking the gate and the third heightening block as patterns;
forming an interlayer insulating layer on the buffer layer, the grid electrode and the third elevating block, and forming a first groove corresponding to the third elevating block on the interlayer insulating layer, wherein the first groove is recessed to the upper surface of the third elevating block;
and depositing a second metal material on the interlayer insulating layer, and forming a source-drain electrode layer and a partition layer through the same photomask, wherein the partition layer fills the first groove, and one side of the partition layer, which is far away from the third pad block, is provided with a first inverted acute angle area.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103632948A (en) * | 2013-12-25 | 2014-03-12 | 苏州晶湛半导体有限公司 | Semiconductor device and manufacturing method thereof |
| JP2015156381A (en) * | 2015-03-31 | 2015-08-27 | ユニファイド イノヴェイティヴ テクノロジー， エルエルシー | Organic electroluminescence (el) display |
| CN108538890A (en) * | 2018-04-20 | 2018-09-14 | 深圳市华星光电技术有限公司 | A kind of organic light-emitting display device |
| CN109599429A (en) * | 2018-12-25 | 2019-04-09 | 合肥鑫晟光电科技有限公司 | Display panel and its manufacturing method |
| CN110071225A (en) * | 2019-04-08 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Display panel and production method |
| US10937998B1 (en) * | 2019-11-28 | 2021-03-02 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel and method for preparing the same, and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210028388A1 (en) * | 2019-07-22 | 2021-01-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Oled display panel |
-
2021
- 2021-03-25 CN CN202110331143.0A patent/CN113097265B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103632948A (en) * | 2013-12-25 | 2014-03-12 | 苏州晶湛半导体有限公司 | Semiconductor device and manufacturing method thereof |
| JP2015156381A (en) * | 2015-03-31 | 2015-08-27 | ユニファイド イノヴェイティヴ テクノロジー， エルエルシー | Organic electroluminescence (el) display |
| CN108538890A (en) * | 2018-04-20 | 2018-09-14 | 深圳市华星光电技术有限公司 | A kind of organic light-emitting display device |
| WO2019200666A1 (en) * | 2018-04-20 | 2019-10-24 | 深圳市华星光电技术有限公司 | Organic light-emitting display device |
| CN109599429A (en) * | 2018-12-25 | 2019-04-09 | 合肥鑫晟光电科技有限公司 | Display panel and its manufacturing method |
| CN110071225A (en) * | 2019-04-08 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Display panel and production method |
| US10937998B1 (en) * | 2019-11-28 | 2021-03-02 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel and method for preparing the same, and display device |
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