CN113097234A - Array substrate, preparation method thereof, display panel and display device - Google Patents

Array substrate, preparation method thereof, display panel and display device Download PDF

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Publication number
CN113097234A
CN113097234A CN202110361551.0A CN202110361551A CN113097234A CN 113097234 A CN113097234 A CN 113097234A CN 202110361551 A CN202110361551 A CN 202110361551A CN 113097234 A CN113097234 A CN 113097234A
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Prior art keywords
source
layer
bus
driving bus
gate
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Inventor
韩长娟
王龙
祝晓钊
冯敏强
廖良生
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Jiangsu Jicui Institute of Organic Optoelectronics Co Ltd
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Jiangsu Jicui Institute of Organic Optoelectronics Co Ltd
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Priority to CN202110361551.0A priority Critical patent/CN113097234A/en
Publication of CN113097234A publication Critical patent/CN113097234A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

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Abstract

The embodiment of the invention discloses an array substrate, a preparation method of the array substrate, a display panel and a display device. The array substrate comprises a grid electrode driving bus, a source electrode driving bus, a plurality of scanning lines, a plurality of signal lines and a plurality of transistors, wherein the transistors are arranged at the intersections of the corresponding scanning lines and the corresponding signal lines, the scanning lines are respectively connected to the grid electrode driving bus, the signal lines are respectively connected to the source electrode driving bus, and the sectional areas of source electrode layers and/or drain electrode layers of the transistors connected to the signal lines are sequentially increased along the extending direction of the signal lines away from the source electrode driving bus. The embodiment of the invention solves the problem of brightness uniformity caused by voltage drop (IR drop), and achieves the effect of improving the display uniformity.

Description

Array substrate, preparation method thereof, display panel and display device
Technical Field
The embodiment of the invention relates to a display technology, in particular to an array substrate, a preparation method of the array substrate, a display panel and a display device.
Background
In the field of Display technology, flat panel Display devices such as Liquid Crystal Display (LCD) panels and Organic Light-Emitting Diode (OLED) panels are increasingly used. The OLED display panel gradually occupies the windward due to the unique advantages of low power consumption, high saturation, fast response time, wide viewing angle and the like, and has wide application space in vehicle-mounted, mobile phone, tablet, computer and television products in the future.
The main driving mode of the OLED display panel is current driving, working current can be provided by a Source driving bus located at a lower frame of the display panel and is transmitted to a Source Drain (SD) of a transistor through a signal line, and the signal transmission has a voltage drop (IR drop) phenomenon because the Source Drain has a certain resistance, namely, the voltage is gradually reduced along a direction far away from the lower frame relative to the lower frame, the input current is correspondingly reduced, and finally the display panel has a non-uniform brightness phenomenon, so that the use performance of the product is influenced.
At present, a method for solving the problem of uneven brightness of the OLED display panel is a double-layer SD structure. Namely, the OLED display panel adopts a double-layer SD structure, and the voltage of the display panel is controlled to be reduced through a parallel circuit, so that the phenomenon of uneven brightness of a product is improved. However, the design of the double-layer SD structure limits its popularization and application due to the disadvantages of complex manufacturing process, high cost and the like.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a preparation method thereof, a display panel and a display device, which are used for solving the problem of brightness uniformity caused by voltage drop (IR drop) and achieving the effect of improving the display uniformity.
In a first aspect, an embodiment of the present invention provides an array substrate, including a gate driving bus and a source driving bus, a plurality of scanning lines, a plurality of signal lines, and a plurality of transistors disposed at intersections corresponding to the scanning lines and the signal lines, where the plurality of scanning lines are respectively connected to the gate driving bus, the plurality of signal lines are respectively connected to the source driving bus, and cross-sectional areas of source layers and/or drain layers of the transistors connected to the signal lines are sequentially increased along an extending direction of the signal lines away from the source driving bus.
Optionally, the width of the signal line gradually increases along a direction away from the source driving bus.
Optionally, the source driving bus includes a first source driving bus and a second source driving bus that are arranged oppositely;
the source layer and/or the drain layer of the transistor connected to the signal line are sequentially increased in cross-sectional area in a direction in which the first source driving bus and the second source driving bus point to the middle region.
Optionally, the width of the signal line gradually increases along a direction in which the first source driving bus and the second source driving bus point to the middle region.
Optionally, the display device further includes a plurality of storage capacitors, and capacitance values of different storage capacitors are gradually increased along an extending direction of the signal line away from the source drive bus.
Optionally, the transistor includes a first gate, a second gate corresponding to the first gate, and an insulating layer disposed between the first gate and the second gate, where the first gate, the second gate, and the insulating layer form the storage capacitor.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
providing a substrate base plate;
forming an array layer on one side of the substrate base plate;
the array layer comprises a gate drive bus, a source drive bus, a plurality of scanning lines, a plurality of signal lines and a plurality of transistors, wherein the transistors are arranged at the intersections of the scanning lines and the signal lines, the scanning lines are respectively connected to the gate drive bus, the signal lines are respectively connected to the source drive bus, and the sectional areas of source layers and/or drain layers of the transistors connected to the signal lines are sequentially increased along the extension direction of the signal lines away from the source drive bus.
Optionally, the forming an array layer on one side of the substrate base plate includes:
forming an active layer on one side of the substrate base plate;
forming a first insulating layer on one side of the active layer, which is far away from the substrate;
forming a gate layer and the scan line on a side of the first insulating layer away from the active layer;
forming a second insulating layer on the side of the gate layer away from the first insulating layer;
exposing a source region and a drain region of the transistor by using a photoetching process, wherein the areas of the source region and/or the drain region of the transistor connected to a signal line are sequentially increased along the extension direction of the signal line away from the source drive bus;
and removing the first insulating layer and the second insulating layer of the source electrode region and the drain electrode region, and pouring a metal material to form a source electrode and a drain electrode.
In a third aspect, an embodiment of the present invention further provides a display panel, including any one of the array substrates described above.
In a fourth aspect, an embodiment of the present invention further provides a display device, including the display panel described above.
The array substrate provided by the embodiment of the invention comprises a grid electrode driving bus, a source electrode driving bus, a plurality of scanning lines, a plurality of signal lines and a plurality of transistors arranged at the intersections of the corresponding scanning lines and the corresponding signal lines, wherein the plurality of scanning lines are respectively connected to the grid electrode driving bus, the plurality of signal lines are respectively connected to the source electrode driving bus, the gate driving wires provide scanning signals for the scanning lines, the source driving buses provide data signals for the signal lines, by arranging the source electrode layer and/or the drain electrode layer of the transistor connected to the signal line in the extending direction of the signal line away from the source drive bus line, the sectional area is increased in turn, thereby reducing the resistance of the source and/or drain of the transistor on the side away from the source drive bus, the problem of brightness uniformity caused by voltage drop (IR drop) is solved, and the effect of improving the display uniformity is achieved.
Drawings
FIG. 1 is a schematic diagram of a display panel according to the prior art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 6 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 8 is a schematic cross-sectional view illustrating another array substrate according to an embodiment of the present invention;
fig. 9 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It should be noted that the terms "upper", "lower", "left", "right", and the like used in the description of the embodiments of the present invention are used in the angle shown in the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in this context, it is also to be understood that when an element is referred to as being "on" or "under" another element, it can be directly formed on "or" under "the other element or be indirectly formed on" or "under" the other element through an intermediate element. The terms "first," "second," and the like, are used for descriptive purposes only and not for purposes of limitation, and do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Fig. 1 is a schematic structural diagram of a display panel in the prior art, referring to fig. 1, taking the display panel as an OLED display panel as an example, the OLED display panel includes a first source drain layer 01 and a second source drain layer 02 which are stacked up and down, an anode 03 of an organic light emitting layer is connected to the second source drain layer 02, and the second source drain layer 02 is designed in a mesh structure. Namely, the OLED display panel adopts a double-layer SD structure, and the voltage of the display panel is controlled to be reduced through a parallel circuit, so that the phenomenon of uneven brightness of a product is improved. However, the design of the double-layer SD structure limits the popularization and application of the structure due to the defects of complex manufacturing process, high cost and the like.
In order to solve the above problems, an embodiment of the invention provides an array substrate, which includes a gate driving bus, a source driving bus, a plurality of scan lines, a plurality of signal lines, and a plurality of transistors disposed at intersections of the corresponding scan lines and the corresponding signal lines, wherein the plurality of scan lines are respectively connected to the gate driving bus, the plurality of signal lines are respectively connected to the source driving bus, and cross-sectional areas of source layers and/or drain layers of the transistors connected to the signal lines are sequentially increased along an extending direction of the signal lines away from the source driving bus.
The array substrate provided by the embodiment of the present invention may be used for a liquid crystal display panel or an OLED display panel, the array substrate in this embodiment is used for an OLED display panel as an example, fig. 2 is a schematic structural diagram of the array substrate provided by the embodiment of the present invention, referring to fig. 2, the array substrate includes a display area 10 and a frame area 20, the frame area 20 includes a gate driving bus 21 and a source driving bus 22, the display area 10 includes a plurality of scan lines 11, a plurality of signal lines 12, and a plurality of transistors 13 disposed at intersections of the corresponding scan lines 11 and the corresponding signal lines 12, and each transistor 13 corresponds to one sub-pixel. It should be noted that the driving circuit corresponding to one sub-pixel may include a plurality of transistors, and fig. 2 shows the driving transistors. One end of each scanning line 11 is connected with the gate drive bus 21, and each scanning line 11 is connected with the gate of the transistor 13 corresponding to one row of sub-pixels and is used for transmitting a scanning signal for controlling the on or off of the transistor 13; one end of each signal line 12 is connected to the source driving bus 22, and each signal line 12 is connected to the source of the transistor 13 corresponding to a column of sub-pixels, and is used for transmitting a data signal for controlling the sub-pixels to emit light. Fig. 3 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention, referring to fig. 3, the array substrate includes a substrate 100 and an array layer 200 located on one side of the substrate 100, a transistor 13 in the array layer 200 includes an active layer 131, a first insulating layer 201, a gate layer 132, a second insulating layer 202, a source layer 133 and a drain layer 134, fig. 3 schematically illustrates that two regions S1 and S2 each include one transistor 13, where the S1 region corresponds to a display region close to a source driving bus, and the S2 region corresponds to a display region far from the source driving bus. The sectional area of the source and the drain of the transistor in the region S2 is larger than that of the source and the drain of the transistor in the region S1, and the smaller the sectional area of the source and/or the drain of the transistor closer to the source drive bus, the larger the sectional area of the source and/or the drain of the transistor farther from the source drive bus, according to the formula R ═ ρ L/S (where ρ represents the resistivity of the resistor and is determined by its own properties, L represents the length of the resistor, and S represents the sectional area of the resistor), it is known that increasing the sectional area can reduce the resistor, so as to reduce the voltage drop of the circuit on the side far from the source drive bus, and achieve the effect of improving the display uniformity.
It should be noted that, the cross-sectional areas of the source and the drain of the transistor in the S2 region shown in fig. 3 are both larger than the cross-sectional areas of the source and the drain of the transistor in the S1 region, which is only schematic, in other embodiments, the cross-sectional areas of the source and the drain of the transistor in the S2 region may be set to be larger, and the specific implementation may be designed according to actual situations. In other embodiments, the cross-sectional areas of the source regions and the drain regions of the transistors in the same sub-display region are the same.
According to the technical scheme of the embodiment of the invention, the gate driving wiring is used for providing scanning signals for the scanning lines, the source driving bus is used for providing data signals for the signal lines, and the sectional areas of the source electrode layer and/or the drain electrode layer of the transistor connected to the signal lines are sequentially increased along the extending direction of the signal lines far away from the source driving bus, so that the resistance value of the source electrode and/or the drain electrode of the transistor far away from one side of the source driving bus is reduced, the problem of brightness uniformity caused by voltage drop (IR drop) is solved, and the effect of improving the display uniformity is achieved.
On the basis of the foregoing embodiment, fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, and referring to fig. 4, optionally, the width of the signal line 12 is gradually increased along a direction away from the source driving bus 22.
By increasing the width of the signal line 12 away from one end of the source driving bus 22, the resistance of the signal line 12 at the side away from the source driving bus 22 can be reduced, so as to reduce the voltage drop of the circuit at the side away from the source driving bus 12, thereby achieving the effect of improving the display uniformity.
Fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, referring to fig. 5, optionally, the source driving bus 22 includes a first source driving bus 221 and a second source driving bus 222 that are oppositely disposed, and fig. 5 schematically illustrates that the first source driving bus 221 and the second source driving bus 222 are respectively located at an upper frame and a lower frame of the array substrate, in which case, a display uniformity problem may occur in a middle display area due to IR drop.
Exemplarily, fig. 6 is a schematic cross-sectional structure view of another array substrate according to an embodiment of the present invention, and fig. 6 schematically illustrates three regions S3, S4, and S5, where the S3 region is located at a side close to the first source driving bus, the S5 region is located at a side close to the second source driving bus, the S4 region is located between the S3 region and the S5 region, cross-sectional areas of the source and the drain of the transistor in the S4 region are larger than those of the source and the drain of the transistor in the S3 region and the S5 region, and the S3 region and the S5 region are not limited, and optionally, cross-sectional areas of the source and the drain of the transistor at the same distance as the corresponding source driving bus are the same.
Fig. 7 is a schematic structural view of another array substrate according to an embodiment of the present invention, and referring to fig. 7, optionally, the width of the signal line 12 gradually increases along a direction in which the first source driving bus 221 and the second source driving bus 222 point to the middle region. By arranging the direction pointing to the middle region along the first source driving bus 221 and the second source driving bus 222, the width of the signal line 12 is gradually increased, that is, the width of the middle region of the signal line 12 far away from the first source driving bus 221 and the second source driving bus 222 is increased, so that the resistance of the signal line 12 in the middle region can be reduced, the voltage drop of the middle region circuit is reduced, and the effect of improving the display uniformity is achieved.
Optionally, the array substrate provided in this embodiment further includes a plurality of storage capacitors, and capacitance values of different storage capacitors are gradually increased along an extending direction of the signal line away from the source driving bus.
The capacitance value of the storage capacitor along the direction away from the source electrode driving wiring is gradually increased, and the driving current of the sub-pixels is prevented from being smaller and smaller in a current compensation mode, so that the driving current uniformity of each sub-pixel can be ensured, the light emitting brightness uniformity of the display panel is ensured, and the uneven light emitting brightness condition of the display panel is improved.
Referring to fig. 8, in another cross-sectional structure of the array substrate according to the embodiment of the invention, optionally, the transistor 13 includes a first gate 1321, a second gate 1322 disposed corresponding to the first gate 1321, and an insulating layer 203 disposed between the first gate 1321 and the second gate 1322, where the first gate 1321, the second gate 1322, and the insulating layer 203 form a storage capacitor. In an embodiment, the first gate 1321 is a lower plate of the storage capacitor, and the second gate 1322 is an upper plate of the storage capacitor, and in an implementation, openings with different areas of the second gate 1322 in different regions may be disposed to implement different sizes of the storage capacitors.
Fig. 9 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention, where the method is used to manufacture any one of the array substrates according to the above embodiments, and referring to fig. 9, the method for manufacturing according to this embodiment includes:
step S110, a substrate is provided.
The substrate may be a rigid substrate, such as a glass substrate, or a flexible substrate, and may be formed of any suitable insulating material having flexibility. For example, the flexible substrate may be formed of a polymer material such as Polyimide (PI), Polycarbonate (PC), Polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), Polyarylate (PAR), or glass Fiber Reinforced Plastic (FRP). The substrate base plate may be transparent, translucent or opaque.
And step S120, forming an array layer on one side of the substrate base plate.
The array layer comprises a grid electrode driving bus, a source electrode driving bus, a plurality of scanning lines, a plurality of signal lines and a plurality of transistors, wherein the transistors are arranged at the intersection of the corresponding scanning lines and the corresponding signal lines, the scanning lines are respectively connected to the grid electrode driving bus, the signal lines are respectively connected to the source electrode driving bus, and the sectional areas of the source electrode layer and/or the drain electrode layer of the transistors connected to the signal lines are sequentially increased along the extending direction of the signal lines far away from the source electrode driving bus.
According to the technical scheme of the embodiment of the invention, the sectional areas of the source electrode layer and/or the drain electrode layer of the transistor connected to the signal line are sequentially increased along the extension direction of the signal line far away from the source electrode driving bus, so that the resistance value of the source electrode and/or the drain electrode of the transistor far away from the source electrode driving bus is reduced, the problem of brightness uniformity caused by voltage drop (IR drop) is solved, and the effect of improving the display uniformity is achieved.
On the basis of the above embodiment, optionally, forming an array layer on one side of the substrate base plate includes:
step S121, forming an active layer on one side of the base substrate.
The active layer may include a silicon-containing active layer, for example, a low temperature polysilicon active layer LTPS, or may include a metal oxide active layer, for example, an indium gallium zinc oxide active layer IGZO, which is not limited in this embodiment of the present invention.
Step S122 is to form a first insulating layer on the side of the active layer away from the substrate.
Wherein the first insulating layer includes an inorganic layer such as silicon oxide, silicon nitride, or metal oxide, and may include a single layer or a plurality of layers.
Step S123, forming a gate layer and a scan line on a side of the first insulating layer away from the active layer.
Among them, the gate electrode layer and the scan line may include a single layer or a plurality of layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or an alloy such as aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy.
In step S124, a second insulating layer is formed on the gate layer away from the first insulating layer.
Wherein the second insulating layer may be the same as the first insulating layer in process and material.
Step S125, exposing the source region and the drain region of the transistor by using a photolithography process, wherein the areas of the source region and/or the drain region of the transistor connected to the signal line are sequentially increased along the extending direction of the signal line away from the source driving bus.
And etching the first insulating layer and the second insulating layer by using a photoetching process, and enabling the area of a source region and/or a drain region at one side far away from the source driving bus to be larger, so that the cross-sectional area of the source layer and/or the drain layer is increased, and the IR drop is reduced.
Step S126, removing the first insulating layer and the second insulating layer in the source region and the drain region, and pouring a metal material to form a source and a drain.
In other embodiments, the transistor may include a double gate structure, a plurality of insulating layer processes and a gate process, wherein the signal line may be formed in the same layer as the source layer and the drain layer, and may be formed in the same process as the source layer, and the gate driving bus and the source driving bus are disposed in the frame region, and the transistor structure and the routing line may be formed in synchronization with the transistor in the display region.
Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 10, the display panel according to the embodiment includes any one of the array substrates 30 according to the above embodiments.
The display panel provided in this embodiment includes any one of the array substrates provided in the above embodiments, and has the same or corresponding technical effects as the array substrate, which is not described herein again. The display panel includes an array substrate 30 and a first substrate 40, where the first substrate 40 is a color film substrate when the display panel is a liquid crystal display panel, and the first substrate is a protective cover plate when the display panel is an OLED display panel.
Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention. Referring to fig. 11, the display device 1 includes the display panel 2 provided in the above embodiment. The display device 1 may be a mobile phone, a computer, an intelligent wearable device, and the like.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. An array substrate comprises a grid electrode driving bus, a source electrode driving bus, a plurality of scanning lines, a plurality of signal lines and a plurality of transistors, wherein the transistors are arranged at the intersections of the scanning lines and the signal lines, the scanning lines are respectively connected to the grid electrode driving bus, the signal lines are respectively connected to the source electrode driving bus, and the sectional area of a source electrode layer and/or a drain electrode layer of each transistor connected to each signal line is sequentially increased along the extension direction of the signal line away from the source electrode driving bus.
2. The array substrate of claim 1, wherein the width of the signal lines gradually increases in a direction away from the source driving bus lines.
3. The array substrate of claim 1, wherein the source driving bus comprises a first source driving bus and a second source driving bus which are oppositely arranged;
the source layer and/or the drain layer of the transistor connected to the signal line are sequentially increased in cross-sectional area in a direction in which the first source driving bus and the second source driving bus point to the middle region.
4. The array substrate of claim 3, wherein the width of the signal line gradually increases along a direction in which the first source driving bus line and the second source driving bus line point to a middle region.
5. The array substrate of claim 1, further comprising a plurality of storage capacitors, wherein capacitance values of different storage capacitors gradually increase along an extending direction of the signal line away from the source driving bus.
6. The array substrate of claim 5, wherein the transistor comprises a first gate, a second gate disposed corresponding to the first gate, and an insulating layer disposed between the first gate and the second gate, wherein the first gate, the second gate, and the insulating layer form the storage capacitor.
7. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate base plate;
forming an array layer on one side of the substrate base plate;
the array layer comprises a gate drive bus, a source drive bus, a plurality of scanning lines, a plurality of signal lines and a plurality of transistors, wherein the transistors are arranged at the intersections of the scanning lines and the signal lines, the scanning lines are respectively connected to the gate drive bus, the signal lines are respectively connected to the source drive bus, and the sectional areas of source layers and/or drain layers of the transistors connected to the signal lines are sequentially increased along the extension direction of the signal lines away from the source drive bus.
8. The method for manufacturing the array substrate according to claim 7, wherein the forming of the array layer on the substrate side comprises:
forming an active layer on one side of the substrate base plate;
forming a first insulating layer on one side of the active layer, which is far away from the substrate;
forming a gate layer and the scan line on a side of the first insulating layer away from the active layer;
forming a second insulating layer on the side of the gate layer away from the first insulating layer;
exposing a source region and a drain region of the transistor by using a photoetching process, wherein the areas of the source region and/or the drain region of the transistor connected to a signal line are sequentially increased along the extension direction of the signal line away from the source drive bus;
and removing the first insulating layer and the second insulating layer of the source electrode region and the drain electrode region, and pouring a metal material to form a source electrode and a drain electrode.
9. A display panel comprising the array substrate according to any one of claims 1 to 6.
10. A display device characterized by comprising the display panel according to claim 9.
CN202110361551.0A 2021-04-02 2021-04-02 Array substrate, preparation method thereof, display panel and display device Pending CN113097234A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114355686A (en) * 2022-01-07 2022-04-15 武汉华星光电技术有限公司 Array substrate and liquid crystal display panel

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028650A (en) * 1996-07-19 2000-02-22 Nec Corporation Liquid crystal display apparatus with uniform feed-through voltage in panel
CN102779475A (en) * 2011-05-10 2012-11-14 索尼公司 Display device and display method
US20130271444A1 (en) * 2012-04-11 2013-10-17 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid Crystal Display Device and Display Panel Thereof
CN107799537A (en) * 2017-09-26 2018-03-13 武汉华星光电技术有限公司 Array base palte and display device
CN107819022A (en) * 2017-11-15 2018-03-20 武汉天马微电子有限公司 A kind of display panel and display device
CN109448635A (en) * 2018-12-06 2019-03-08 武汉华星光电半导体显示技术有限公司 OLED display panel

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028650A (en) * 1996-07-19 2000-02-22 Nec Corporation Liquid crystal display apparatus with uniform feed-through voltage in panel
CN102779475A (en) * 2011-05-10 2012-11-14 索尼公司 Display device and display method
US20130271444A1 (en) * 2012-04-11 2013-10-17 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid Crystal Display Device and Display Panel Thereof
CN107799537A (en) * 2017-09-26 2018-03-13 武汉华星光电技术有限公司 Array base palte and display device
CN107819022A (en) * 2017-11-15 2018-03-20 武汉天马微电子有限公司 A kind of display panel and display device
CN109448635A (en) * 2018-12-06 2019-03-08 武汉华星光电半导体显示技术有限公司 OLED display panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114355686A (en) * 2022-01-07 2022-04-15 武汉华星光电技术有限公司 Array substrate and liquid crystal display panel

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