CN113097105A - Dry etching device and etching method for second-class superlattice refrigeration infrared chip - Google Patents
Dry etching device and etching method for second-class superlattice refrigeration infrared chip Download PDFInfo
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- CN113097105A CN113097105A CN202110319405.1A CN202110319405A CN113097105A CN 113097105 A CN113097105 A CN 113097105A CN 202110319405 A CN202110319405 A CN 202110319405A CN 113097105 A CN113097105 A CN 113097105A
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- 238000005530 etching Methods 0.000 title claims abstract description 61
- 238000001312 dry etching Methods 0.000 title claims abstract description 20
- 238000005057 refrigeration Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 17
- 229910015844 BCl3 Inorganic materials 0.000 claims abstract description 9
- 238000005192 partition Methods 0.000 claims abstract description 8
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 230000007246 mechanism Effects 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000001502 supplementing effect Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000002341 toxic gas Substances 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a second-class superlattice refrigeration infrared chip dry etching device and an etching method, wherein the etching device comprises a box body, the interior of the box body is divided into an upper cavity chamber and a lower cavity chamber through a partition plate, a bin opening is formed in the front face of the box body, a bin door is installed at the bin opening, an opening is formed in the middle of the partition plate, a sample table is installed in the lower cavity chamber, a lifting table is arranged above the sample table, the lifting table is fixedly connected with the sample table, an etching area is formed between the sample table and the lifting table, a base plate is arranged in the etching area, the sample table is driven to lift by the lifting device, a pressure stabilizing tube, a first vacuum tube, a second vacuum tube and a gas adding2And BCl3A gas. The second-class superlattice refrigeration infrared chip dry etching device and the etching method can effectively solve the problem of etching gas consumption in the chip etching processThe quantity is big, and the etching gas leaks the scheduling problem easily, can effectively reduce chip etching process gas consumption cost.
Description
Technical Field
The invention belongs to the technical field of chip manufacturing, and particularly relates to a dry etching device for a second-class superlattice refrigeration infrared chip.
Background
The InAs/GaSb second class superlattice is used as the material of the infrared detector, has easily adjustable wavelength,the electron effective mass is larger, the Auger recombination rate is lower, the response is high and the sensitivity is strong. The manufacturing process of the second type of superlattice refrigeration infrared chip generally comprises the steps of glue homogenizing, pre-baking, exposure, development, post-baking, etching, glue removing and the like. Wherein the etching process mainly adopts an ICP dry etching technology. The ICP dry etching technology is widely applied to the semiconductor chip manufacturing process, and has the advantages of good anisotropy, easily controlled etching appearance and etching depth and the like. However, this technique generally uses Cl2And BCl3Co-participate in reactive etching, and Cl2And BCl3Are all toxic gases, especially Cl2Belongs to extremely toxic gas and has strict control. The leakage of etching gas is easy to occur in the etching process, great potential safety hazard and management difficulty exist, the consumption of the etching gas in the etching process at each time is large, and the cost is high.
Disclosure of Invention
In order to solve the technical problems, the invention adopts the technical scheme that: a second-class superlattice refrigeration infrared chip dry etching device comprises a box body, wherein the interior of the box body is divided into an upper cavity chamber and a lower cavity chamber through a partition plate, a bin opening communicated with the lower cavity chamber is formed in the front face of the box body, a bin door capable of sealing the bin opening is installed at the bin opening, an opening is formed in the middle of the partition plate, a sample table is installed in the lower cavity chamber, a lifting table is arranged above the sample table and fixedly connected with the sample table through a connecting plate, an etching area is formed between the sample table and the lifting table, a base plate is arranged in the etching area and is driven to lift by a lifting device, when the lifting device drives the sample table to descend to the lowest point, the etching area is located in the lower cavity chamber, the lifting table seals and blocks the opening, when the lifting device drives the sample table to ascend to the highest point, a pressure stabilizing tube, a first vacuum tube, a second vacuum tube and a gas, the stabilivolt and the first vacuum tube are respectively communicated with the lower cavity, the second vacuum tube and the gas filling tube are respectively communicated with the upper cavity, and the gas filling tube is connected with Cl2And BCl3A gas.
Preferably, a seal ring is provided inside the opening.
Preferably, in the above technical solution, the connection plate is a porous connection plate.
Preferably, the etching area is provided with a telescopic rod, the telescopic rod is driven by a driving mechanism to extend and retract, and the telescopic rod pushes the substrate out of the lower chamber from the bin opening.
Preferably, the two sides of the base plate are connected with guide rods, the guide rods are installed in guide cylinders, and the guide cylinders are fixed on the sample table.
Preferably, the substrate is detachably provided with a sample plate, and the sample plate is provided with a groove matched with the chip in shape.
A second type of superlattice refrigeration infrared chip single gas dry etching method comprises the etching device according to any one of claims 1-6, and the etching method comprises the following specific steps:
opening the bin gate, and placing a chip to be etched on the substrate;
the bin gate is closed, and the first vacuum tube and the second vacuum tube respectively vacuumize the lower chamber and the upper chamber;
starting the lifting device, lifting the sample platform to the highest point, and enabling the etching area to enter the upper chamber;
the air adding pipe is filled with Cl into the upper cavity2And BCl3Gas is used for etching the chip;
the lifting device is started, the sample platform is lowered to the lowest point, and the etching area returns to the lower chamber;
the first vacuum tube vacuumizes the lower cavity, and then the pressure stabilizing tube fills protective gas into the lower cavity, so that the lower cavity is close to the external pressure;
and opening the bin gate, taking out the etched chip, and supplementing a new chip to be etched.
Preferably, in the above technical solution, the protective gas is air or nitrogen.
The invention has the beneficial effects that: the second-class superlattice refrigeration infrared chip dry etching device and the etching method can effectively solve the problems that the consumption of etching gas is large, the etching gas is easy to leak and the like in the chip etching process, and can effectively reduce the gas consumption cost in the chip etching process.
Drawings
FIG. 1 is a schematic structural diagram of an etching region in a lower chamber;
FIG. 2 is a schematic structural diagram of an etching region in an upper chamber;
FIG. 3 is a schematic view of the configuration of the substrate as it exits the lower chamber from the port.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in FIGS. 1-3, a second-class superlattice refrigeration infrared chip dry etching deviceThe device comprises a box body 1, the interior of the box body 1 is divided into an upper chamber 3 and a lower chamber 4 by a partition plate 2, a bin opening 5 communicated with the lower chamber 4 is arranged on the front surface of the box body 1, a bin door capable of sealing the bin opening 5 is arranged at the bin opening 5, an opening 6 is arranged in the middle of the partition plate 2, a sample stage 7 is arranged in the lower chamber 4, a lifting stage 8 is arranged above the sample stage 7, the lifting stage 8 is fixedly connected with the sample stage 7 through a connecting plate 9, an etching area 10 is formed between the sample stage 7 and the lifting stage 8, a base plate 11 is arranged in the etching area 10, the sample stage 7 is driven to lift by a lifting device, when the lifting device drives the sample stage 7 to fall to the lowest point, the etching area 10 is positioned in the lower chamber 4, the lifting stage 8 seals and blocks the opening 6, when the lifting device drives the sample stage 7 to rise to the highest point, the etching area 10 is positioned in the, A first vacuum tube 13, a second vacuum tube 14 and a gas filling tube 15, wherein the stabilivolt 12 and the first vacuum tube 13 are respectively communicated with the lower chamber 4, the second vacuum tube 14 and the gas filling tube 15 are respectively communicated with the upper chamber 3, and the gas filling tube 15 is connected with Cl2And BCl3A gas. The etching gas in the upper cavity 3 is only taken away by the first vacuum tube 13 in a small amount in the chip loading and unloading process, so that the utilization rate of the etching gas is improved, the leakage of the etching gas is reduced, the etching gas overflowing from the bin opening 5 is less, and the safety of operators is improved. The etching gas in the upper chamber 3 can be replaced periodically, so that the cost of the etching gas is reduced.
Further, a sealing ring is arranged on the inner side of the opening 6. The seal ring maintains the sealing property with the sample stage 7 or the elevating stage 8.
Further, the connection plate 9 is a porous connection plate. The porous web does not interfere with the entry of etching gas into the etching zone 10.
Furthermore, a telescopic rod is installed in the etching area 10, the telescopic rod is driven by a driving mechanism to stretch, and the telescopic rod pushes the substrate 11 out of the lower chamber 4 from the bin opening 5. The driving mechanism can be a motor, an electric push rod, an air cylinder and other traditional driving mechanisms.
Furthermore, two sides of the base plate 11 are connected with guide rods 16, the guide rods 16 are installed in guide cylinders 17, and the guide cylinders 17 are fixed on the sample table 7. The cooperation of the guide rods 16 with the guide cylinders 17 makes the substrate 11 more stable during movement.
Further, a sample plate is detachably mounted on the substrate 11, and a groove matched with the shape of the chip is formed in the sample plate. The grooves prevent the chip from sliding on the substrate 11. The sample plate can be detachably arranged, and different sample plates can be replaced. Different sample plates are provided with grooves with different shapes, so that the sample plates are suitable for chips with different specifications.
The specific operation steps comprise:
the bin gate is opened and the chip to be etched is placed on the substrate 11.
The bin gate is closed, and the first vacuum tube 13 and the second vacuum tube 14 respectively vacuumize the lower chamber 4 and the upper chamber 3;
the lifting device is started, the sample platform 7 is lifted to the highest point, and the etching area 10 enters the upper chamber 3;
the gas-filling pipe 15 fills Cl into the upper chamber 32、BCl3Gas is used for etching the chip;
the lifting device is started, the sample platform 7 descends to the lowest point, and the etching area 10 returns to the lower chamber 4;
the first vacuum tube 13 vacuumizes the lower chamber 4, and then the pressure stabilizing tube 12 fills protective gas into the lower chamber 4, so that the lower chamber 4 is close to the external pressure;
and opening the bin gate, taking out the etched chip, and supplementing a new chip to be etched.
Further, the protective gas is air or nitrogen.
It should be noted that the technical features of other auxiliary mechanisms of dry etching and the like related to the present patent application should be regarded as the prior art, and the specific structure, the operation principle, the control mode and the spatial arrangement mode of the technical features may be selected conventionally in the field, and should not be regarded as the invention point of the present patent, and the present patent is not further specifically described in detail.
Having described preferred embodiments of the present invention in detail, it is to be understood that modifications and variations may be resorted to without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A second-class superlattice refrigeration infrared chip dry etching device is characterized by comprising a box body, the interior of the box body is divided into an upper cavity chamber and a lower cavity chamber through a partition plate, a bin opening communicated with the lower cavity chamber is formed in the front face of the box body, a bin door capable of sealing the bin opening is mounted at the bin opening, an opening is formed in the middle of the partition plate, a sample table is mounted in the lower cavity chamber, a lifting table is arranged above the sample table and fixedly connected with the sample table through a connecting plate, an etching area is formed between the sample table and the lifting table, a base plate is arranged in the etching area, the sample table is driven to lift by a lifting device, when the lifting device drives the sample table to descend to the lowest point, the etching area is located in the lower cavity chamber, the lifting table seals and blocks the opening, when the lifting device drives the sample table to ascend to the highest point, a pressure stabilizing tube, a first vacuum tube, a second vacuum tube and a, the stabilivolt and the first vacuum tube are respectively communicated with the lower cavity, the second vacuum tube and the gas filling tube are respectively communicated with the upper cavity, and the gas filling tube is connected with Cl2And BCl3A gas.
2. The dry etching device for the second-class superlattice refrigeration infrared chip as claimed in claim 1, wherein a sealing ring is arranged inside the opening.
3. The second-class superlattice refrigeration infrared chip dry etching device as claimed in claim 1, wherein said connecting plate is a porous connecting plate.
4. The second-class superlattice refrigeration infrared chip dry etching device as claimed in claim 1, wherein a telescopic rod is installed in the etching area, the telescopic rod is driven by a driving mechanism to extend and retract, and the telescopic rod pushes the substrate out of the lower chamber from the bin opening.
5. The second-class superlattice refrigeration infrared chip dry etching device as claimed in claim 4, wherein two sides of the base plate are connected with guide rods, the guide rods are installed in guide cylinders, and the guide cylinders are fixed on the sample table.
6. The second-class superlattice refrigeration infrared chip dry etching device as claimed in claim 5, wherein a sample plate is detachably mounted on the substrate, and the sample plate is provided with a groove matched with the shape of the chip.
7. A second type of superlattice refrigeration infrared chip dry etching method is characterized in that the etching device as claimed in any one of claims 1-6 is used, and the etching method comprises the following specific steps:
opening the bin gate, and placing a chip to be etched on the substrate;
the bin gate is closed, and the first vacuum tube and the second vacuum tube respectively vacuumize the lower chamber and the upper chamber;
starting the lifting device, lifting the sample platform to the highest point, and enabling the etching area to enter the upper chamber;
the air adding pipe is filled with Cl into the upper cavity2And BCl3Gas is used for etching the chip;
the lifting device is started, the sample platform is lowered to the lowest point, and the etching area returns to the lower chamber;
the first vacuum tube vacuumizes the lower cavity, and then the pressure stabilizing tube fills protective gas into the lower cavity, so that the lower cavity is close to the external pressure;
and opening the bin gate, taking out the etched chip, and supplementing a new chip to be etched.
8. The dry etching device for the second-class superlattice refrigeration infrared chip as claimed in claim 7, wherein the protective gas is air or nitrogen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110319405.1A CN113097105B (en) | 2021-03-25 | 2021-03-25 | Dry etching device and method for second-class superlattice refrigerating infrared chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110319405.1A CN113097105B (en) | 2021-03-25 | 2021-03-25 | Dry etching device and method for second-class superlattice refrigerating infrared chip |
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| Publication Number | Publication Date |
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| CN113097105A true CN113097105A (en) | 2021-07-09 |
| CN113097105B CN113097105B (en) | 2023-11-21 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1187204A (en) * | 1997-09-05 | 1999-03-30 | Texas Instr Japan Ltd | Clean room system for semiconductor wafer treatment device |
| US20020013063A1 (en) * | 1989-02-27 | 2002-01-31 | Masayuki Kojima | Method and apparatus for processing samples |
| US20020056311A1 (en) * | 2000-11-13 | 2002-05-16 | Norihiko Nomura | Trap apparatus |
| US20030060030A1 (en) * | 2001-09-25 | 2003-03-27 | Kwang-Myung Lee | Method for processing a wafer and apparatus for performing the same |
| US20050150861A1 (en) * | 2004-01-13 | 2005-07-14 | Kwang-Myung Lee | Etching apparatus and etching method |
| CN101061253A (en) * | 2004-11-22 | 2007-10-24 | 应用材料股份有限公司 | Substrate processing apparatus using a batch processing chamber |
| CN105097607A (en) * | 2014-05-22 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Reaction chamber and cleaning method thereof |
-
2021
- 2021-03-25 CN CN202110319405.1A patent/CN113097105B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020013063A1 (en) * | 1989-02-27 | 2002-01-31 | Masayuki Kojima | Method and apparatus for processing samples |
| JPH1187204A (en) * | 1997-09-05 | 1999-03-30 | Texas Instr Japan Ltd | Clean room system for semiconductor wafer treatment device |
| US20020056311A1 (en) * | 2000-11-13 | 2002-05-16 | Norihiko Nomura | Trap apparatus |
| US20030060030A1 (en) * | 2001-09-25 | 2003-03-27 | Kwang-Myung Lee | Method for processing a wafer and apparatus for performing the same |
| US20050150861A1 (en) * | 2004-01-13 | 2005-07-14 | Kwang-Myung Lee | Etching apparatus and etching method |
| CN101061253A (en) * | 2004-11-22 | 2007-10-24 | 应用材料股份有限公司 | Substrate processing apparatus using a batch processing chamber |
| CN105097607A (en) * | 2014-05-22 | 2015-11-25 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Reaction chamber and cleaning method thereof |
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