CN113096706B - CPU and manufacturing method thereof - Google Patents
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- CN113096706B CN113096706B CN202110256421.0A CN202110256421A CN113096706B CN 113096706 B CN113096706 B CN 113096706B CN 202110256421 A CN202110256421 A CN 202110256421A CN 113096706 B CN113096706 B CN 113096706B
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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Abstract
The embodiment of the invention provides a Central Processing Unit (CPU) and a manufacturing method thereof. Wherein the CPU comprises: at least one core; a multi-level buffer connected with the core signal; wherein, the buffers of different levels in the multi-level buffer comprise memory cell layers of different levels in the phase change memory; the phase change memory includes a plurality of stacked memory cell layers; the memory cell layer comprises a plurality of memory cells; so as to realize that different levels of buffers in the multi-level buffer in the CPU adopt different layers of memory cell layers in the same phase change memory; the smaller volume of the phase change memory can obviously reduce the final size of the CPU, so that delay between the CPU core and each level of buffer memory is reduced, and the higher capacity of the phase change memory can enable more data to be exchanged through the multi-level buffer memory, so that the use amount of the buffered data is increased.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a central processing unit (CPU, central Processing Unit) and a method for manufacturing the same.
Background
In order to solve the contradiction that the CPU operation speed is not matched with the memory read-write speed, a CPU buffer appears. The CPU buffer is a temporary data exchanger between the CPU core and the memory, its capacity is smaller than the memory, but the exchange speed is faster than the memory. The operating speed and capacity of the CPU buffer is directly related to the type of memory employed in the CPU buffer.
In the related art, the CPU buffer generally includes multiple stages, and the multiple stages of the CPU buffer generally use Static Random-Access Memory (SRAM). However, the performance of the CPU is not good due to the capacity and volume of the SRAM.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present invention provide a CPU and a method for manufacturing the same.
The embodiment of the invention provides a CPU, which comprises:
at least one core;
a multi-level buffer connected with the core signal; wherein, the buffers of different levels in the multi-level buffer comprise memory cell layers of different levels in the phase change memory; the phase change memory includes a plurality of stacked memory cell layers; the memory cell layer includes a plurality of memory cells.
In the above scheme, the memory cell layers of the phase change memory corresponding to different layers of the different levels of buffers adopt phase change materials with different conversion speeds; the transition speed includes a speed of transition between a first state and a second state of the phase change material.
In the above scheme, the phase change memory includes a memory cell layer stacked by M layers; the multi-level buffer comprises an N-level buffer; wherein M is a positive integer greater than one; the N is a positive integer greater than one;
if M is equal to N, the storage unit layers of M different layers in the phase change memory respectively correspond to N different stages of registers in the N stages of registers;
if M is greater than N, the storage unit layers of J different layers in the phase change memory correspond to N-level buffers in the N-level buffers; wherein j=m-n+1;
if M is smaller than N, the storage unit layers of M different layers in the phase change memory respectively correspond to the K-th to N-th buffers in the N-th buffers; wherein k=n-m+1.
In the above scheme, M is four, and N is three;
the first storage unit layer positioned at the bottom of the phase change memory is used as a first-level buffer in the N-level buffer; a second storage unit layer positioned on the first storage unit layer in the phase change memory is used as a second-level buffer in the N-level buffer; and a third storage unit layer and a fourth storage unit layer which are positioned on the second storage unit layer in the phase change memory are used as a third-level buffer in the N-level buffer.
In the above scheme, the phase change material of the memory cell in the first memory cell layer includes a binary phase change material; the phase change material of the memory cells in the second memory cell layer comprises undoped ternary phase change material; the phase change material of the memory cells in the third memory cell layer comprises a ternary phase change material with a doping element.
In the above scheme, the phase change material adopted by the memory cell in the first memory cell layer includes antimony tellurium; the phase change material adopted by the memory cells in the second memory cell layer comprises germanium antimony tellurium; the phase change material adopted by the memory cells in the third memory cell layer and the fourth memory cell layer comprises germanium antimony tellurium doped with nitrogen.
In the above scheme, M is two, and N is three;
the fifth storage unit layer positioned at the bottom in the phase change memory is used as a second-level buffer in the N-level buffer; and a sixth storage unit layer positioned on the fifth storage unit layer in the phase change memory is used as a third-level buffer in the N-level buffer.
The embodiment of the invention also provides a manufacturing method of the CPU, which comprises the following steps:
forming a core of a CPU and a peripheral circuit of a multi-level buffer of the CPU on a substrate respectively; the inner core is in signal connection with the multi-level buffer; the buffers of different levels in the multi-level buffer comprise memory cell layers of different layers in a memory cell array of the phase change memory; the memory cell array includes a plurality of stacked memory cell layers; the memory cell layer comprises a plurality of memory cells;
Forming a first metal interconnection layer on the substrate, wherein the peripheral circuit is electrically connected with the memory cell array of the phase change memory through the first metal interconnection layer;
forming the memory cell array on the first metal interconnection layer;
and forming a second-layer metal interconnection layer, wherein the multi-level buffer is electrically connected to an external device through the second-layer metal interconnection layer.
In the above scheme, when the memory cell array is formed, the memory cell layers corresponding to different layers of the different level buffers in the memory cell array adopt phase change materials with different conversion speeds; the transition speed includes a speed of transition between a first state and a second state of the phase change material.
In the above scheme, forming the memory cell array includes:
sequentially forming a plurality of layers of stacked memory unit modules in a layer-by-layer stacking manner; the manufacturing method of each layer of memory cell module comprises the following steps:
forming a first address line layer;
forming a memory cell layer on the first address line layer;
forming a second address line layer on the memory cell layer; wherein the first address line layer and the second address line layer are parallel; the address lines of the first address line layer are perpendicular to the address lines of the second address line layer; each memory cell in the memory cell layer is perpendicular to the address lines of the first address line layer and the address lines of the second address line layer.
The embodiment of the invention provides a CPU and a manufacturing method thereof, wherein the CPU comprises: at least one core; a multi-level buffer connected with the core signal; wherein, the buffers of different levels in the multi-level buffer comprise memory cell layers of different levels in the phase change memory; the phase change memory includes a plurality of stacked memory cell layers; the memory cell layer includes a plurality of memory cells. In the embodiment of the invention, different levels of buffers in the multi-level buffer in the CPU adopt different layers of memory cell layers in the same phase change memory. It will be appreciated by those skilled in the art that the concentration of multiple levels of caches of a CPU in a single phase change memory can greatly reduce the distance between the levels of caches, thereby reducing the delay from the CPU core to the levels of caches. Meanwhile, the phase change memory has higher bit density, namely smaller volume and higher capacity; the smaller volume of the phase change memory can obviously reduce the final size of the CPU, thereby further reducing the delay from the CPU core to the multi-level buffer; in the process of CPU operation, the higher capacity of the phase change memory can enable more data to be exchanged through the multi-level buffer, so that the use amount of the buffered data is increased.
Drawings
FIG. 1a is a schematic diagram of a storage system of a computer according to an embodiment of the present invention;
FIG. 1b is a schematic diagram of a layout of a CPU according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory cell array structure according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a corresponding structure of a memory cell array and a multi-level buffer according to an embodiment of the present invention;
fig. 4 is a schematic implementation flow chart of a method for manufacturing a CPU according to an embodiment of the present invention;
FIGS. 5 a-5 d are schematic cross-sectional views illustrating a CPU manufacturing process according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an implementation flow of a control method of a CPU according to an embodiment of the present invention.
Detailed Description
In order to make the technical scheme and advantages of the embodiments of the present invention more clear, the following describes the specific technical scheme of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
Because of the large difference in storage speed and cost of different storage technologies, for efficient access to data, computer storage systems place the most frequently used data on storage devices that are fast in read-storage speed, and the less frequently used data on storage devices that are slow in read-storage speed. A memory system is a hierarchy of memory devices having different capacities, costs and access times. As shown in fig. 1a, the capacities of the buffer, the main memory, and the disk memory of the CPU, which are set from left to right, are larger and larger, but the access speeds are slower and slower. For example, the speed at which the CPU accesses its own multi-level buffer (L1, L2, L3 in FIG. 1 a) is approximately 0.1 nanoseconds (ns); the speed of interaction between the CPU's cache and main memory is on the ns level and the speed of interaction between main memory and disk memory is on the microsecond (us) level. The left memory serves as a buffer area for the right memory to store data having a higher access frequency. The multi-level cache memory near the CPU core is a buffer area for a portion of the data and instructions in memory. Main memory buffers data on disk storage, which in turn often serves as a buffer area for data stored on disks or tapes of other machines connected via a network.
Based on the above architecture of the memory system, the configuration of the multi-level buffer of the CPU affects the performance of the CPU to a large extent, and even affects the performance of the computer. In the related art, as shown in fig. 1b, the multi-level buffers (L1, L2, L3) of the CPU are each composed of a dense high-speed SRAM. Due to the low bit density characteristics of the SRAM itself, in some cases, the buffer employing the SRAM occupies half the size of the silicon substrate in the CPU chip or even more. The large size of SRAM results in a large distance between the multi-level buffers and a large interconnect resistance-Capacitance (RC) delay. In addition, the yield of the embedded SRAM also affects the yield of the CPU.
The embodiment of the invention provides a CPU, which adopts a plurality of memory cell layers of the same phase change memory (the English abbreviation can be expressed as PCRAM and Phase Change Random Access Memory and the English abbreviation can be expressed as PCM) as a multi-level buffer of the CPU.
Phase change memory is a memory technology using chalcogenide as a memory medium, and data storage is realized by a characteristic that a phase change material exhibits different resistivities through a rapid and reversible transition between a Crystalline state (crystal) and an Amorphous state (amorphlus) under the action of joule heat of a current. The phase change memory has the advantages of bit addressing, no data loss after power failure, high memory density, high read-write speed, simple manufacturing process, compatibility with the mature complementary metal oxide semiconductor (CMOS, complementary Metal Oxide Semiconductor) process and the like, and is considered as the most promising next-generation memory.
The advantage of the scheme of using the memory cell layers of the same multiple layers of the nonvolatile phase change memory as the multi-level buffer of the CPU may include:
1. based on the multi-level buffer adopting different layers of storage unit layers of the same phase change memory, the data transmission speed between the CPU core and the multi-level buffer is obviously improved, and the RC delay time of the CPU logic circuit is shorter;
2. the CPU caching efficiency is improved, and the size of the intensive multi-level cache and the using amount of cache data are reduced;
3. the phase change memory as a nonvolatile memory can incorporate error correction functions to ensure data accuracy;
4. the phase change memory is used as a memory with higher density, so that the CPU core efficiency is higher, the system speed is faster, and the PCB size is smaller and the die size is smaller;
5. the cost of the CPU chip is lower, and the potential burst of the CPU chip on AI application can be promoted.
The embodiment of the invention provides a CPU. The CPU includes:
at least one core;
a multi-level buffer connected with the core signal; wherein, the buffers of different levels in the multi-level buffer comprise memory cell layers of different levels in the phase change memory; the phase change memory includes a plurality of stacked memory cell layers; the memory cell layer includes a plurality of memory cells.
Here, the CPU may include one core or a plurality of cores. The multi-level buffer may be understood as two or more levels of buffers, and in practical applications, the multi-level buffer may include three or four levels of buffers. The multi-level buffers are sequentially connected, the next-level buffer is used as the buffer of the last-level buffer, namely the inner core is connected with the first-level buffer, and the first-level buffer is used as the buffer of the inner core; the first-level buffer is connected with the second-level buffer, and the second-level buffer is used as the buffer of the first-level buffer; the second level buffer is connected with the third level buffer, and the third level buffer is used as the buffer of the second level buffer, and so on.
Here, the phase change memory includes a memory cell array and peripheral circuits; wherein the memory cell array may be integrated on the same die as the peripheral circuitry, which allows for a wider bus and higher operating speeds.
The memory cell array of the phase change memory comprises a plurality of layers of stacked memory cell modules; each memory cell module in the multi-layer stacked memory cell modules comprises a first address line layer, a memory cell layer and a second address line layer which are stacked; wherein the first address line layer and the second address line layer are parallel; the address lines of the first address line layer are perpendicular to the address lines of the second address line layer; each memory cell in the memory cell layer is perpendicular to the address lines of the first address line layer and the address lines of the second address line layer.
In practical applications, the first address line layer may include a word line layer, and correspondingly the second address line layer may include a bit line layer; alternatively, the first address line layer may comprise a bit line layer and correspondingly the second address line layer may comprise a word line layer. The first address line layer may include a plurality of word lines or bit lines; the second address line layer may include a plurality of bit lines or word lines; each of the plurality of memory cells may include a phase change memory element, a gating element, and a plurality of electrodes.
Illustratively, as shown in fig. 2, the architecture of the memory cell module includes: bit line layer, memory cell layer and word line layer; each memory cell 20 in the memory cell layer may include a stacked phase change memory element 202, a gating element 204, and a plurality of electrodes 201, 203, and 205. Heating or quenching of phase change memory element 202 by the electrode is accomplished by conduction of gating element 204 to effect switching between the crystalline and amorphous states of phase change memory element 202; storage of data is accomplished by switching between the crystalline and amorphous states of phase change memory element 202.
The peripheral circuitry of the phase change memory includes any suitable digital, analog, and/or mixed signal circuitry for facilitating phase change memory operation. For example, the peripheral circuits may include control logic, data buffers, decoders (which may also be referred to as decoders), drivers and read and write circuits and so forth. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages generated from the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read operation or the write operation of the data and interact with the outside through the data buffer.
In the embodiment of the present invention, the multi-level buffer may include multiple levels of buffers having different buffer speeds; the phase change memory may include memory cell layers arranged in a multi-layered stack structure. The memory cell layers of different levels of the multi-level memory including different levels of the phase change memory can be understood as: some or all of the different levels of buffers in the multi-level buffer may correspond to different levels of storage unit layers in the multi-level storage unit layers in the phase change memory, specifically, some levels of buffers in the multi-level buffer may correspond to each level of storage unit layer in the multi-level storage unit layers in the phase change memory one by one, or all levels of buffers in the multi-level buffer may correspond to each level of storage unit layer in the multi-level storage unit layers in the phase change memory one by one; it is also possible that different levels of the multi-level buffers correspond to different ones of the multi-level memory cell layers in the phase change memory, and that a certain level of the multi-level buffers corresponds to a certain one of the multi-level memory cell layers in the phase change memory. That is, the multi-level buffers and the multi-level memory cell layers may have a one-to-one correspondence or a one-to-many correspondence, and the multi-level buffers may be all the levels of buffers corresponding to the same phase change memory or some levels of buffers corresponding to the same phase change memory.
Considering that the cache speeds of the different levels of caches of the CPU are different, in order to match the different cache speeds, the storage speeds of the phase change memory cell layers of the different levels of the corresponding different levels of caches in the phase change memory must be different. In practical applications, the phase change memory cell layers of the different layers can achieve the purpose of different memory speeds by using different phase change materials, or setting phase change memory elements with different thicknesses, or using different dielectric materials, or setting address line layers with different thicknesses, and the like.
In view of the convenience of implementation, the following description will take the example that the memory cell layers corresponding to the different layers of the different levels of the buffers in the phase change memory adopt different phase change materials to explain how to implement different memory speeds of the memory cell layers corresponding to the different layers of the different levels of the buffers, so as to respond to the speed requirements of the different levels of the buffers.
As will be appreciated by those skilled in the art, the phase change memory stores data by reversible transformation between amorphous and crystalline states of the phase change material, and the transformation speed between amorphous and crystalline states of different phase change materials is different, so that different memory cell layers of different layers of the phase change memory adopt different phase change materials, and the memory cell layers of different layers in the phase change memory can have different storage speeds.
In practical applications, in some embodiments, the memory cell layers of the phase change memory corresponding to different layers of the different level buffers use phase change materials with different conversion speeds; the transition speed includes a speed of transition between a first state and a second state of the phase change material.
The switching speed is understood here to mean the switching speed between the amorphous and crystalline states of the phase change material used by a certain memory cell layer. In order to make the buffer speed of the memory cell layers corresponding to different layers of different levels of buffers in the phase change memory different, each memory cell layer adopts a phase change material with different conversion speeds. Therefore, the storage speed of each level of buffer in the multi-level buffer can be different according to the different phase change materials, so that the gradual change of the buffer speed and the storage capacity of the multi-level buffer can be realized.
The correspondence between the multi-level buffer and the multi-level phase change memory layer in the phase change memory will be described in further detail below.
In some embodiments, the phase change memory includes a memory cell layer of an M-layer stack; the multi-level buffer comprises an N-level buffer; wherein M is a positive integer greater than one; the N is a positive integer greater than one;
If M is equal to N, the storage unit layers of M different layers in the phase change memory respectively correspond to N different stages of registers in the N stages of registers;
if M is greater than N, the storage unit layers of J different layers in the phase change memory correspond to N-level buffers in the N-level buffers; wherein j=m-n+1;
if M is smaller than N, the storage unit layers of M different layers in the phase change memory respectively correspond to the K-th to N-th buffers in the N-th buffers; wherein k=n-m+1.
In practical application, for the case that M is equal to N:
and the storage unit layers of M different layers in the phase change memory are respectively in one-to-one correspondence with N different stages of registers in the N stages of registers. That is, the first memory cell layer in the phase change memory is used as a first level buffer; and the second storage unit layer in the phase change memory is used as a second-level buffer, so that the M-th storage unit layer in the phase change memory is used as an N-th buffer.
For example, when m=n=2, the multi-level buffer is a second-level buffer, and the phase change memory includes two stacked memory cell layers, where a first memory cell layer located at the bottom of the phase change memory is used as a first-level buffer in the second-level buffer; and a second storage unit layer positioned on the first storage unit layer in the phase change memory is used as a second-level buffer in the second-level buffer.
For example, when m=n=4, the multi-level buffer is a four-level buffer, and the phase change memory includes four stacked memory cell layers, where a first memory cell layer located at the bottom of the phase change memory is used as a first level buffer in the four-level buffer; the second storage unit layer positioned on the first storage unit layer in the phase change memory is used as a second-level buffer in the fourth-level buffer; a third storage unit layer positioned on the second storage unit layer in the phase change memory is used as a third-level buffer in the fourth-level buffer; and the fourth storage unit layer positioned on the third storage unit layer in the phase change memory is used as a fourth-level buffer in the fourth-level buffers.
In practical application, for the case that M is greater than N:
and the storage unit layers of M different layers in the phase change memory correspond to N different stages of buffers in the N-stage buffer. At this time, the first storage unit layer in the phase change memory is used as a first level buffer in the N level buffer; the second storage unit layer in the phase change memory is used as a second-level buffer in the N-level buffer, so that the rest M-N+1 storage unit layers in the phase change memory are used as an N-level buffer in the N-level buffer; that is, the first to N-1 th level buffers in the N level buffer correspond to N-1 different levels of memory cell layers in the phase change memory one by one, respectively.
For example, as shown in fig. 3, when m=4 and n=3, the multi-level buffer is a three-level buffer, and the phase change memory includes four stacked memory cell layers, then the first memory cell layer at the bottom of the phase change memory is used as the first level buffer in the three-level buffer; the second storage unit layer positioned on the first storage unit layer in the phase change memory is used as a second-level buffer in the three-level buffer; and the third storage unit layer and the fourth storage unit layer which are positioned on the second storage unit layer in the phase change memory are used as a third-stage buffer in the third-stage buffer.
In practical applications, in some embodiments, the phase change material of the memory cells in the first memory cell layer includes a binary phase change material; the phase change material of the memory cells in the second memory cell layer comprises undoped ternary phase change material; the phase change material of the memory cells in the third memory cell layer comprises a ternary phase change material with a doping element.
Here, the binary phase change material may include Ga-Sb, in-Sb, ge-Te, ge-Sb, sb-Te, and other alloy materials, and the thin film made of the binary phase change material has the characteristics of relatively excellent electrical properties, low crystallization temperature, and fast crystallization rate, and based on the thin film, the read-write operation speed of the first memory cell layer made of the binary phase change material is relatively fast. The ternary phase change material mainly comprises a Ge-Sb-Te alloy material, and a film manufactured based on the undoped ternary phase change material is characterized by enhanced thermal stability compared with a binary phase change material, and the increased number of reversible conversion operations between an amorphous state and a crystalline state means that the speed of reading and writing operations of a second storage unit layer manufactured by adopting the ternary phase change material is reduced, the number of times of repeatable erasing is increased, and the storage capacity is enhanced. The undoped ternary phase change material is doped with N, sn, bi, si, C, in and other elements, and the result shows that the doped ternary phase change material not only can improve the thermal stability of the film, reduce the power consumption of the device, but also can improve the crystalline resistance or reduce the melting point and the like on the basis of the original (undoped ternary phase change material); however, at the same time, the third memory cell layer made of the ternary phase change material with the doping element has slower read-write operation speed and enhanced memory capability compared with the second memory cell layer made of the undoped ternary phase change material.
Therefore, the binary phase change material, the undoped ternary phase change material and the ternary phase change material with doped elements are respectively used as manufacturing materials of different memory cell layers of the phase change memory, so that the cache speed of the phase change memory is gradually decreased layer by layer, and the memory capacity is gradually increased layer by layer, thereby achieving the purposes of gradually decreasing the memory speed of the multi-level buffer and gradually increasing the memory capacity.
Illustratively, the phase change material used by the memory cells in the first memory cell layer includes antimony tellurium (Sb-Te); the phase change material adopted by the memory cells in the second memory cell layer comprises germanium antimony tellurium (Ge-Sb-Te); the phase change materials adopted by the memory cells in the third memory cell layer and the fourth memory cell layer comprise germanium antimony tellurium (Ge-Sb-Te) doped with nitrogen element (N).
In practical application, the binary alloy Sb-Te is widely used as a phase change material for optical storage due to higher crystallization rate, and the crystallization mechanism of the Sb-Te phase change material is a growth type mechanism which is beneficial to accelerating crystallization; in the ternary phase change material Ge-Sb-Te series alloy, the comprehensive performance is excellent as Ge 2 Sb 2 Te 5 And GeSb 2 Te 4 The film made based on the two materials has high crystallization rate (nanosecond order), the resistivity difference between the amorphous state and the crystalline state is large, and the amorphous state and the crystalline state are between The reversibility is good; the doped Ge-Sb-Te phase-change material has enhanced thermal stability by doping N, sn, bi, si, C, in and other elements, such as N element, to make Ge 2 Sb 2 Te 5 The crystal lattice of the film is distorted, the doped N element is bonded with Ge to generate GeN, so that the crystal grain has obvious refining effect, and the crystallization rate can be improved; and the doped ternary phase change material can also be reflected from the performance test result of the doped material, so that the crystallization temperature can be increased.
In practical application, the doping amount of the doping element can be adjusted according to practical situations, and those skilled in the art can understand that the higher the doping amount of the doping element is, the more remarkable the stability and resistivity improvement effect of the phase change material is.
Here, the conversion rate between amorphous and crystalline states of Sb-Te, ge-Sb-Te, and N-doped Ge-Sb-Te phase change materials is gradually decreased, and the thermal stability is gradually increased, so that the above three materials are used as phase change materials of different memory cell layers of the phase change memory, and can match the requirements of different memory speeds of the memory cell layers of the phase change memory.
In practical application, for the case that M is smaller than N:
and the storage unit layers of M different layers in the phase change memory correspond to part of different stages of the N-stage buffer. At this time, the first storage unit layer in the phase change memory is used as a K-th level buffer in the N-level buffer; the second storage unit layer in the phase change memory is used as a K+1st level buffer in the N level buffer; similarly, the M-th layer of memory cell layer in the phase change memory is used as a K+M-1-th level buffer in the N-level buffer; the K+M-1 level buffer is the N level buffer, i.e. K=N-M+1.
For example, m=2, n=3, and the multi-level buffer is a three-level buffer, where the phase change memory includes two stacked memory cell layers, namely, a fifth memory cell layer and a sixth memory cell layer; then, a fifth storage unit layer positioned at the bottom in the phase change memory is used as a second-level buffer in the third-level buffer; and a sixth storage unit layer positioned on the fifth storage unit layer in the phase change memory is used as a third-level buffer in the third-level buffer.
The embodiment of the invention provides a CPU, which comprises: at least one core; a multi-level buffer connected with the core signal; wherein, the buffers of different levels in the multi-level buffer comprise memory cell layers of different levels in the phase change memory; the phase change memory includes a plurality of stacked memory cell layers; the memory cell layer includes a plurality of memory cells. In the embodiment of the invention, different levels of buffers in the multi-level buffer in the CPU adopt different layers of memory cell layers in the same phase change memory. It will be appreciated by those skilled in the art that the concentration of multiple levels of caches of a CPU in a single phase change memory can greatly reduce the distance between the levels of caches, thereby reducing the delay from the CPU core to the levels of caches. Meanwhile, the phase change memory has higher bit density, namely smaller volume and higher capacity; the smaller volume of the phase change memory can obviously reduce the final size of the CPU, thereby further reducing the delay from the CPU core to the multi-level buffer; in the process of CPU operation, the higher capacity of the phase change memory can enable more data to be exchanged through the multi-level buffer, so that the use amount of the buffered data is increased.
The advantage of the scheme of using the memory cell layers of the same multiple layers of the nonvolatile phase change memory as the multi-level buffer of the CPU may include:
1. based on the adoption of different layers of storage unit layers of the same phase change memory by the multi-level buffer, the data transmission speed between the CPU core and the multi-level buffer is obviously improved, and the RC delay time is shorter;
2. the matching of the storage speeds of different stages of buffers is easy to realize by changing the phase change material;
3. the CPU cache efficiency is improved, the size of the intensive multi-level cache is reduced, and the use amount of cache data is improved;
4. the phase change memory as a nonvolatile memory can incorporate error correction functions to ensure data accuracy;
5. the phase change memory is used as a memory with higher density, so that the CPU core efficiency is higher, the system speed is faster, and the PCB size is smaller and the die size is smaller;
6. the cost of the CPU chip is lower, and the potential burst of the CPU chip on AI application can be promoted.
The embodiment of the invention also provides a manufacturing method of the CPU to obtain the CPU. Fig. 4 is a schematic implementation flow chart of a method for manufacturing a CPU according to an embodiment of the present invention. As shown in fig. 4, the method comprises the steps of:
Step 401: forming a core of a CPU and a peripheral circuit of a multi-level buffer of the CPU on a substrate respectively; the inner core is in signal connection with the multi-level buffer; the buffers of different levels in the multi-level buffer comprise memory cell layers of different layers in a memory cell array of the phase change memory; the memory cell array includes a plurality of stacked memory cell layers; the memory cell layer comprises a plurality of memory cells;
step 402: forming a first metal interconnection layer on the substrate, wherein the peripheral circuit is electrically connected with the memory cell array of the phase change memory through the first metal interconnection layer;
step 403: forming the memory cell array on the first metal interconnection layer;
step 404: and forming a second-layer metal interconnection layer, wherein the multi-level buffer is electrically connected to an external device through the second-layer metal interconnection layer.
Fig. 5a to 5d are examples of cross-sectional views of a manufacturing process of a CPU according to an embodiment of the present invention. In fig. 5a to 5d, only the multi-level buffer is taken as the three-level buffer, and the memory cell array of the phase change memory is exemplified by four stacked memory cell layers. It should be understood that the operations shown in fig. 4 are not exclusive and that other operations may be performed before, after, or between any of the operations shown. The method of forming the CPU of the present embodiment is described below with reference to fig. 4, 5a to 5 d.
In this embodiment, the relationship between the different levels of registers in the multi-level registers of the CPU and the different levels of memory cell layers in the memory cell array of the phase change memory is described in the previous embodiment, and will not be described here again. For ease of understanding, herein, taking the multi-level buffer as the three-level buffer, the phase change memory includes four stacked memory cell layers as an example, and in this example, the first memory cell layer located at the bottom of the phase change memory is used as the first level buffer in the three-level buffer; the second storage unit layer positioned on the first storage unit layer in the phase change memory is used as a second-level buffer in the three-level buffer; the third memory cell layer and the fourth memory cell layer on the second memory cell layer in the phase change memory are used as a third level buffer in the third level buffer.
In step 401, as shown in fig. 5a, on the one hand, a core of the CPU and a peripheral circuit of a multi-level buffer of the CPU are formed; specifically, an arithmetic function element for realizing an arithmetic function of a core and a control function element for realizing a controller function are formed; and forming peripheral circuits and memory cell arrays of each level of buffer in the three levels of buffers. The manufacturing of the core and the multi-level buffer is mature in the related art, and will not be described herein.
In practical applications, the specific process of forming the transistors and related control circuits of the peripheral circuits of the phase change memory may include: firstly, forming a P-type well region (PWAll) and an N-type well region (NWAll) on a substrate (such as a silicon substrate), respectively carrying out N doping on the PWAll, and carrying out P doping on the NWAll to form a required semiconductor doping region; then, a metal gate is formed over the surface of the substrate to obtain a peripheral circuit including transistors and related control circuits.
In practical application, the CPU provided by the embodiment of the present invention may use a System On a Chip (SOC) package, or may use a System On a Chip (SIP, system In a Package) package. Here, SOC refers to an integrated circuit (IC, integrated Circuit) that integrates originally different functions into one chip. The method not only can reduce the volume, but also can reduce the distance between different ICs and improve the calculation speed of the chip. SIP integrates various functional chips, including a processor, a memory, and the like, into one package, thereby realizing a substantially complete function.
In step 402, as shown in fig. 5b, a first metal interconnection layer is formed on the substrate, and the peripheral circuit is electrically connected to the memory cell array of the phase change memory through the first metal interconnection layer;
In practical application, the method for forming the first metal interconnection layer comprises the steps of forming a dielectric layer on a substrate; forming a hole or a groove penetrating through the dielectric layer and extending into a structure to be connected in the substrate in the dielectric layer; and filling conductive materials in the holes or the grooves to form a first metal interconnection layer. Here, the dielectric layer may include silicon oxide, and the conductive material may include copper or tungsten.
In step 403, as shown in fig. 5c, the memory cell array is formed on the first metal interconnection layer;
in practical applications, in some embodiments, forming the memory cell array includes:
sequentially forming a plurality of layers of stacked memory unit modules in a layer-by-layer stacking manner; the manufacturing method of each layer of memory cell module comprises the following steps:
forming a first address line layer;
forming a memory cell layer on the first address line layer;
forming a second address line layer on the memory cell layer; wherein the first address line layer and the second address line layer are parallel; the address lines of the first address line layer are perpendicular to the address lines of the second address line layer; each memory cell in the memory cell layer is perpendicular to the address lines of the first address line layer and the address lines of the second address line layer.
It should be noted that, the first address line layer may include a word line layer, and correspondingly, the second address line layer may include a bit line layer; alternatively, the first address line layer may comprise a bit line layer and correspondingly the second address line layer may comprise a word line layer. The first address line layer may include a plurality of word lines or bit lines; the second address line layer may include a plurality of bit lines or word lines. In practice, the material of the word line or bit line may comprise tungsten. The first address line layer is parallel to the second address line layer, and the address lines (word lines or bit lines) of the first address line layer are perpendicular to the address lines (bit lines or word lines) of the second address line layer; each memory cell of the plurality of memory cells is perpendicular to an address line of the first address line layer and an address line of the second address line layer. Each memory cell includes: the first electrode layer, the gating layer, the second electrode layer, the phase change memory layer and the third electrode layer are sequentially stacked. Here, reference is made to fig. 2 for the relative positional relationship among the word line layer, the bit line layer, and the memory cell, and the structure of the memory cell.
In practical application, the step of forming the address line of the corresponding first address line layer or the address line of the corresponding second address line layer includes: depositing a conductor layer; patterning the conductor layer; and etching the conductor layer after the patterning treatment to form address lines of the corresponding first address line layer or address lines of the corresponding second address line layer.
In practical applications, a stacked memory cell module may be sequentially formed in a layer-by-layer manner. For example, a phase change memory having four stacked memory cell layers may be formed sequentially in a layer-by-layer stacked manner into four stacked memory cell modules, and in some embodiments, two adjacent address lines may be combined into one address line.
In practical application, the step of forming the corresponding memory cell includes: sequentially depositing a first electrode layer, a gating layer, a second electrode layer, a phase change material layer and a third electrode layer on the corresponding first address line layer; patterning the first electrode layer, the gating layer, the second electrode layer, the phase change material layer and the third electrode layer; and etching the first electrode layer, the gating layer, the second electrode layer, the phase change material layer and the third electrode layer after the patterning treatment to form corresponding memory cells.
In practical applications, in some embodiments, when forming the memory cell array, memory cell layers corresponding to different layers of different levels of buffers in the memory cell array use phase change materials with different conversion speeds; the transition speed includes a speed of transition between a first state and a second state of the phase change material.
The switching speed is understood here to mean the switching speed between the amorphous and crystalline states of the phase change material used by a certain memory cell layer. In order to make the buffer speed of the memory cell layers corresponding to different layers of different levels of buffers in the phase change memory different, each memory cell layer adopts phase change materials with different conversion speeds. Therefore, the storage speed of each level of buffer in the multi-level buffer can be different according to the different phase change materials, so that the gradual change of the buffer speed and the storage capacity of the multi-level buffer can be realized.
In step 404, as shown in fig. 5d, a second metal interconnect layer is formed, through which the multi-level buffer is electrically connected to an external device.
Here, the external device refers to an external circuit, an external device, or an external system, etc. to which the CPU needs to be connected when the CPU is used.
In practical application, the specific process of forming the second metal interconnection layer includes: forming through silicon vias on a memory cell array of a last level buffer of the multi-level buffers; filling conductive materials in the through silicon via to form a through silicon conductive plunger; forming a wiring layer on the through silicon via; and generating an extraction welding pad on the rewiring layer.
It will be appreciated that, when the CPU includes an N-level buffer, and the phase change memory includes M-stacked memory cell layers, the manufacturing method is similar to the case where the CPU includes a three-level buffer as illustrated above, and the phase change memory includes four-stacked memory cell layers, which will not be described herein.
Based on the foregoing CPU, the embodiment of the present invention further provides a control method for the CPU. Fig. 6 is a schematic diagram of an implementation flow of a control method of a CPU according to an embodiment of the present invention. As shown in fig. 6, the method comprises the steps of:
step 601: the kernel of the CPU receives a data access request; the CPU comprises the CPU provided by the embodiment of the invention;
step 602: checking whether the request data exists in a first level buffer in the multi-level buffers of the CPU;
step 603: when the request data does not exist in the first-level buffer, checking whether the request data exists in a next-level buffer of the first-level buffer in the multi-level buffer;
step 604: when the searched buffer memory does not have the request data, continuously checking whether the new next buffer memory has the request data according to the order of sequentially increasing the buffer memory levels until the last buffer memory in the multi-level buffer memory;
Step 605: returning the request data when the request data exists in the last level buffer in the multi-level buffers; and when the fact that the request data does not exist in the last-stage buffer in the multi-stage buffers is determined, corresponding data in the main memory are loaded into the last-stage buffer in the multi-stage buffers.
Based on the CPU, in practical application, a multi-level buffer is taken as an example of a three-level buffer. Three levels of buffers for the CPU: l1, L2, L3, the smaller the level, the closer to the CPU, and the faster the cache speed. Each kernel may be provided with one L1 register, or two L1 registers. When two L1 registers are provided, one may be used to store data and the other may be used to store instructions. Each core may be provided with an L2 buffer; the cores between the same CPU socket may share one L3 buffer. Just like a database cache, when data is acquired, the data is firstly found in the fastest cache, if the cache is not hit, the data is found in the next level until the data is required by the memory until the data is not found in the third level cache. As the number of misses increases, the length of time that represents the data acquisition effort increases.
That is, in the embodiment of the present invention, when reading data, the order of querying the data from the memory is: firstly, inquiring a first-level buffer memory, inquiring a second-level buffer memory after the first-level buffer memory is missed, according to the rule, until the last-level buffer memory in the multi-level buffer memory, and loading corresponding data in a main memory into the multi-level buffer memory after the last-level buffer memory is missed.
When the request data does not exist in the last level buffer in the multi-level buffers, loading the corresponding data in the main memory into the multi-level buffers, including:
when the fact that the request data does not exist in the last-stage buffer in the multi-stage buffer is determined, corresponding data in a main memory are loaded into a phase change memory of the multi-stage buffer;
when checking whether the request data exists in the multi-level buffer, the method comprises the following steps:
checking whether the request data exists in the multi-level buffer;
and when the request data is determined not to exist in the phase change memory, checking whether the request data exists in the phase change memory in the multi-level buffer.
In some embodiments, the method further comprises:
And when the CPU is restarted, the normal operation of the CPU is quickly restored by checking the operation state and the snapshot of the data stored in the multi-level buffer when the CPU is powered off.
In practical application, the running state and data of the CPU are stored in the phase change memory, and the running state and data of the CPU are still stored in the phase change memory after the CPU is powered off because the phase change memory is a nonvolatile memory. After the power supply of the CPU is restored, the running state and data of the CPU do not need to be copied into the main memory from the disk, and the normal running of the CPU is restored to be greatly improved because the loading program of the disk does not need to be started.
It should be noted that, the applications of the CPU are many, in some application scenarios, the operation speed of the CPU is required to be higher, and in some application scenarios, the operation speed of the CPU is required to be lower, and those skilled in the art can understand that different phase change memories can provide different response speeds (storage speeds) to match and adapt to different requirements of the CPU.
The embodiment of the invention provides a scheme for adopting a plurality of storage unit layers of the same phase change memory as a multi-level buffer of a CPU, which can improve the CPU buffer performance, logic efficiency and yield. In the embodiment of the invention, the CPU core and the logic circuit of the multi-level cache are formed on the same chip through a logic CMOS process, and the dense phase change memory array is formed into a nonvolatile multi-level cache in a back-end routing layer so as to provide large nonvolatile data storage. The embodiment of the invention can store the state of the CPU and the snapshot of the data so as to quickly recover the CPU, and can also combine the error correction function so as to ensure the accuracy of the data.
It should be noted that: "first," "second," etc. are used to distinguish similar objects and not necessarily to describe a particular order or sequence.
In addition, the embodiments of the present invention may be arbitrarily combined without any collision.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention.
Claims (8)
1. A central processing unit CPU, comprising:
at least one core;
a multi-level buffer connected with the core signal; wherein, the buffers of different levels in the multi-level buffer comprise memory cell layers of different levels in the phase change memory; the phase change memory includes a plurality of stacked memory cell layers; the memory cell layer comprises a plurality of memory cells; each memory cell includes a phase change memory element, a gating element, and a plurality of electrodes; the storage speeds of the phase change memory cell layers of different layers corresponding to different levels of buffers in the phase change memory are different; the memory cell layers of different layers corresponding to different levels of buffers in the phase change memory achieve different memory speeds by adopting phase change materials with different crystal phases so as to enable the phase change materials to have different conversion speeds, or setting phase change memory elements with different thicknesses; the transition speed includes a transition speed between a first state and a second state of the phase change material.
2. The CPU of claim 1 wherein the phase change memory includes M stacked layers of memory cells; the multi-level buffer comprises an N-level buffer; wherein M is a positive integer greater than one; the N is a positive integer greater than one;
if M is equal to N, the storage unit layers of M different layers in the phase change memory respectively correspond to N different stages of registers in the N stages of registers;
if M is greater than N, the storage unit layers of J different layers in the phase change memory correspond to N-level buffers in the N-level buffers; wherein j=m-n+1;
if M is smaller than N, the storage unit layers of M different layers in the phase change memory respectively correspond to the K-th to N-th buffers in the N-th buffers; wherein k=n-m+1.
3. The CPU of claim 2 wherein M is four and N is three;
the first storage unit layer positioned at the bottom of the phase change memory is used as a first-level buffer in the N-level buffer; a second storage unit layer positioned on the first storage unit layer in the phase change memory is used as a second-level buffer in the N-level buffer; and a third storage unit layer and a fourth storage unit layer which are positioned on the second storage unit layer in the phase change memory are used as a third-level buffer in the N-level buffer.
4. The CPU of claim 3 wherein the phase change material of the memory cells in the first memory cell layer comprises a binary phase change material; the phase change material of the memory cells in the second memory cell layer comprises undoped ternary phase change material; the phase change material of the memory cells in the third memory cell layer comprises a ternary phase change material with a doping element.
5. The CPU of claim 4 wherein the phase change material used for the memory cells in the first memory cell layer comprises antimony tellurium; the phase change material adopted by the memory cells in the second memory cell layer comprises germanium antimony tellurium; the phase change material adopted by the memory cells in the third memory cell layer and the fourth memory cell layer comprises germanium antimony tellurium doped with nitrogen.
6. The CPU of claim 2 wherein M is two and N is three;
the fifth storage unit layer positioned at the bottom in the phase change memory is used as a second-level buffer in the N-level buffer; and a sixth storage unit layer positioned on the fifth storage unit layer in the phase change memory is used as a third-level buffer in the N-level buffer.
7. A method for manufacturing a CPU, comprising:
forming a core of a CPU and a peripheral circuit of a multi-level buffer of the CPU on a substrate respectively; the inner core is in signal connection with the multi-level buffer; the buffers of different levels in the multi-level buffer comprise memory cell layers of different layers in a memory cell array of the phase change memory; the memory cell array includes a plurality of stacked memory cell layers; the memory cell layer comprises a plurality of memory cells; each memory cell includes a phase change memory element, a gating element, and a plurality of electrodes; the storage speeds of the phase change memory cell layers of different layers corresponding to different levels of buffers in the phase change memory are different; the memory cell layers of different layers corresponding to different levels of buffers in the phase change memory achieve different memory speeds by adopting phase change materials with different crystal phases so as to enable the phase change materials to have different conversion speeds, or setting phase change memory elements with different thicknesses; the transition speed comprises a transition speed between a first state and a second state of the phase change material;
forming a first metal interconnection layer on the substrate, wherein the peripheral circuit is electrically connected with the memory cell array of the phase change memory through the first metal interconnection layer;
Forming the memory cell array on the first metal interconnection layer;
and forming a second-layer metal interconnection layer, wherein the multi-level buffer is electrically connected to an external device through the second-layer metal interconnection layer.
8. The method of claim 7, wherein forming the array of memory cells comprises:
sequentially forming a plurality of layers of stacked memory unit modules in a layer-by-layer stacking manner; the manufacturing method of each layer of memory cell module comprises the following steps:
forming a first address line layer;
forming a memory cell layer on the first address line layer;
forming a second address line layer on the memory cell layer; wherein the first address line layer and the second address line layer are parallel; the address lines of the first address line layer are perpendicular to the address lines of the second address line layer; each memory cell in the memory cell layer is perpendicular to the address lines of the first address line layer and the address lines of the second address line layer.
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