CN113078069A - Chip packaging method and chip packaging structure - Google Patents

Chip packaging method and chip packaging structure Download PDF

Info

Publication number
CN113078069A
CN113078069A CN202110327890.7A CN202110327890A CN113078069A CN 113078069 A CN113078069 A CN 113078069A CN 202110327890 A CN202110327890 A CN 202110327890A CN 113078069 A CN113078069 A CN 113078069A
Authority
CN
China
Prior art keywords
layer
chip
thermal expansion
adapter plate
expansion coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110327890.7A
Other languages
Chinese (zh)
Other versions
CN113078069B (en
Inventor
谢俊
曹立强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd, Shanghai Xianfang Semiconductor Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN202110327890.7A priority Critical patent/CN113078069B/en
Publication of CN113078069A publication Critical patent/CN113078069A/en
Application granted granted Critical
Publication of CN113078069B publication Critical patent/CN113078069B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A chip packaging method and a chip packaging structure are provided, the chip packaging method comprises the following steps: providing an adapter plate; arranging a chip on one side of the adapter plate; forming a first plastic packaging layer covering the side wall of the chip on one side of the adapter plate; bonding a slide glass on the surface of one side, back to the adapter plate, of the first plastic packaging layer; forming a second plastic packaging layer on the surface of one side, back to the first plastic packaging layer, of the slide glass, wherein the thermal expansion coefficients of the slide glass are respectively smaller than the thermal expansion coefficient of the second plastic packaging layer and the thermal expansion coefficient of the first plastic packaging layer; and thinning the surface of one side of the adapter plate, which faces away from the first plastic package layer, after the second plastic package layer is formed. The chip packaging method can effectively reduce warping.

Description

Chip packaging method and chip packaging structure
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a chip packaging method and a chip packaging structure.
Background
The chips need to be packaged after the fabrication is complete. In the process of packaging the chip, a plastic packaging process is required. However, after the molding layer is formed, the package structure has a very serious warpage problem, which causes great operation difficulty in the subsequent back surface process.
In the prior art, the warpage problem exists in the chip packaging process, so that an effective improvement method is urgently needed.
Disclosure of Invention
The invention aims to solve the technical problem of how to effectively reduce the warpage in the chip packaging process in the prior art.
In order to solve the above technical problem, the present invention provides a chip packaging method, including: providing an adapter plate; arranging a chip on one side of the adapter plate; forming a first plastic packaging layer covering the side wall of the chip on one side of the adapter plate; bonding a slide glass on the surface of one side, back to the adapter plate, of the first plastic packaging layer; forming a second plastic packaging layer on the surface of one side, back to the first plastic packaging layer, of the slide glass, wherein the thermal expansion coefficients of the slide glass are respectively smaller than the thermal expansion coefficient of the second plastic packaging layer and the thermal expansion coefficient of the first plastic packaging layer; and thinning the surface of one side of the adapter plate, which faces away from the first plastic package layer, after the second plastic package layer is formed.
Optionally, the difference between the thermal expansion coefficient of the first plastic package layer and the thermal expansion coefficient of the slide glass is less than or equal to 7.3 ppm/K; the difference between the thermal expansion coefficient of the second plastic packaging layer and the thermal expansion coefficient of the slide glass is less than or equal to 7.3 ppm/K.
Optionally, a difference between the thermal expansion coefficient of the first plastic package layer and the thermal expansion coefficient of the second plastic package layer is greater than or equal to 0 and less than or equal to 1 ppm/K.
Optionally, a distance from a surface of one side of the first plastic package layer, which faces away from the interposer, to the interposer is less than or equal to a distance from a surface of one side of the chip, which faces away from the interposer, to the interposer; the carrier is also bonded on the surface of one side, back to the adapter plate, of the chip.
Optionally, the method further includes: before a chip is arranged on one side of the adapter plate, forming a conductive plug in the adapter plate with partial thickness; after the conductive plug is formed, a first rewiring structure is formed on one side surface of the adapter plate and one side surface of the conductive plug, and the first rewiring structure is electrically connected with the conductive plug; after a chip is arranged on one side of the adapter plate, the chip is electrically connected with the first rewiring structure; after the first plastic packaging layer is formed, the first plastic packaging layer also covers the first rewiring structure; and thinning the surface of the adapter plate back to one side of the first plastic packaging layer until the conductive plug is exposed, wherein the surface of the conductive plug back to one side of the chip.
Optionally, the thickness of the second plastic package layer is smaller than that of the first plastic package layer.
Optionally, the thickness of the slide glass is 700-800 μm.
Optionally, the method further includes: and thinning the surface of one side of the adapter plate, which faces away from the first plastic package layer, and then carrying out a back process.
Optionally, the method further includes: and after the back surface process is carried out, removing the second plastic packaging layer and the slide glass.
The invention also provides a chip packaging structure, which comprises an adapter plate; the chip is positioned on one side of the adapter plate; the first plastic packaging layer is positioned on one side of the adapter plate and covers the side wall of the chip; the slide glass is positioned on the surface of one side, back to the adapter plate, of the first plastic packaging layer; and the second plastic package layer is positioned on the surface of one side of the slide glass, which is back to the first plastic package layer, and the thermal expansion coefficients of the slide glass are respectively smaller than the thermal expansion coefficient of the second plastic package layer and the thermal expansion coefficient of the first plastic package layer.
Optionally, the difference between the thermal expansion coefficient of the first plastic package layer and the thermal expansion coefficient of the slide glass is less than or equal to 7.3 ppm/K; the difference between the thermal expansion coefficient of the second plastic packaging layer and the thermal expansion coefficient of the slide glass is less than or equal to 7.3 ppm/K.
Optionally, a difference between the thermal expansion coefficient of the first plastic package layer and the thermal expansion coefficient of the second plastic package layer is greater than or equal to 0 and less than or equal to 1 ppm/K.
Optionally, the thickness of the second plastic package layer is smaller than that of the first plastic package layer.
Optionally, the thickness of the slide glass is 700-800 μm.
Optionally, the interposer has a conductive plug penetrating through the interposer; the chip packaging structure further comprises: the first rewiring structure is positioned on one side surface of the adapter plate and the conductive plug and is electrically connected with the conductive plug and the chip; the first plastic packaging layer also covers the first rewiring structure; the second rewiring structure is positioned on the other side surfaces of the adapter plate and the conductive plug and is electrically connected with the conductive plug; and the solder ball is positioned on the surface of the second rewiring structure.
The technical method of the invention has the following beneficial effects:
according to the chip packaging method provided by the technical scheme of the invention, a slide glass is bonded on the surface of one side, back to the adapter plate, of the first plastic packaging layer, and the slide glass can reduce the warping of a packaging structure to a certain extent. The second plastic packaging layer is formed on the surface of one side, back to the first plastic packaging layer, of the slide glass, so that the first plastic packaging layer, the slide glass and the second plastic packaging layer form a sandwich structure. Because the thermal expansion coefficient of the slide glass is respectively smaller than the thermal expansion coefficient of the second plastic-sealed layer and the thermal expansion coefficient of the first plastic-sealed layer, the acting force of the second plastic-sealed layer on the slide glass is suitable for offsetting partial acting force of the first plastic-sealed layer on the slide glass, the warping degree of the slide glass is reduced, and when the warping degree of the slide glass is reduced, the warping degree of the whole chip packaging structure is reduced. And after the surface of the adapter plate, which faces away from one side of the first plastic package layer, is thinned, the stress in the adapter plate is released, the stress released in the adapter plate is suitable for being mutually offset with the middle stress of a sandwich structure formed by the first plastic package layer, the slide glass and the second plastic package layer, and the warping of the adapter plate can be reduced or even eliminated by adjusting the thickness of the second plastic package layer. In conclusion, the chip packaging method can effectively reduce the warping degree of the packaging structure.
After the surface of the adapter plate, which faces away from one side of the first plastic packaging layer, is thinned, the warping degree of the packaging structure can be effectively reduced, so that the requirement of subsequent back processing equipment operation is met, and the purpose of fine operation is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts;
FIG. 1 is a flow chart of a chip packaging process in one embodiment of the invention;
fig. 2 to 9 are schematic structural diagrams of a chip packaging process according to an embodiment of the invention.
Detailed Description
As described in the background, the prior art has warpage problems during chip packaging.
A method of ameliorating warpage in a chip packaging process, comprising: providing an adapter plate; arranging a chip on one side of the adapter plate; forming a plastic packaging layer covering the side wall of the chip on one side of the adapter plate; and arranging a glass substrate with a certain thickness on the surface of one side of the plastic packaging layer back to the adapter plate.
Although providing a glass substrate of a certain thickness improves warpage of the packaging process to some extent, the degree of improving warpage is limited. And the conducting plug is arranged in the adapter plate, after the surface of one side of the plastic packaging layer back to the adapter plate is provided with the glass substrate with a certain thickness, one side of the adapter plate back to the chip is thinned, the stress in the adapter plate is released, the warping direction of the adapter plate is overturned and increased, the influence on the subsequent back process is great, and the fine operation of the subsequent back process is not facilitated.
On the basis, the embodiment of the invention provides a chip packaging method, which effectively solves the warping problem in the chip packaging process.
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a chip packaging method, please refer to fig. 1, including the following steps:
s01, providing an adapter plate;
s02, arranging a chip on one side of the adapter plate;
s03, forming a first plastic package layer covering the side wall of the chip on one side of the adapter plate;
s04, bonding a slide glass on the surface of one side, back to the adapter plate, of the first plastic packaging layer;
s05, forming a second plastic package layer on the surface of one side, back to the first plastic package layer, of the slide glass, wherein the thermal expansion coefficients of the slide glass are respectively smaller than the thermal expansion coefficient of the second plastic package layer and the thermal expansion coefficient of the first plastic package layer;
and S06, thinning the surface of the adapter plate, which is back to one side of the first plastic package layer, after the second plastic package layer is formed.
The process of chip packaging is described in detail below with reference to fig. 2 to 9.
Referring to fig. 2, an interposer 100 is provided.
In this embodiment, the interposer 100 is a silicon interposer. In other embodiments, the interposer may also be selected from other semiconductor materials.
With continued reference to fig. 2, a conductive plug 101 is formed in a partial thickness of the interposer 100; after the conductive plug 101 is formed, a first redistribution structure 120 is formed on one side surface of the interposer 100 and the conductive plug 101, and the first redistribution structure 120 is electrically connected to the conductive plug 101.
The number of the conductive plugs 101 may be several.
The first rewiring structure 120 includes a first insulating layer 121 and a first rewiring conductive layer 122 in the first insulating layer 121.
The conductive plug 101 is in contact with the first redistribution line conductive layer 122.
Referring to fig. 3, a chip is disposed on one side of the interposer 100.
Specifically, after the first redistribution structure 120 is formed, a chip 130 is disposed on a side of the first redistribution structure 120 facing away from the interposer 100.
The number of the chips 130 is several.
The chip 130 is electrically connected to the first rewiring structure 120 through conductive microspheres 140.
The chip 130 is placed upside down on the first rewiring structure 120.
Referring to fig. 4, a first molding layer 150 covering a sidewall of the chip 130 is formed at one side of the interposer 100.
Since the thermal expansion coefficient of the first molding compound layer 150 is greatly different from that of the interposer 100, after the first molding compound layer 150 is formed, the edge of the package structure formed in this step is warped toward the side of the first molding compound layer 150 opposite to the interposer 100.
Specifically, the thermal expansion coefficient of the first molding compound layer 150 is greater than the thermal expansion coefficient of the interposer 100.
In this embodiment, the method for forming the first molding compound layer 150 includes: forming a first initial plastic package film covering the chip 130 on a side of the first redistribution structure 120 facing away from the interposer 100; the first initial molding film is planarized until the top surface of the chip 130 facing away from the interposer 100 is exposed, thereby forming a first molding layer 150. Accordingly, the first molding compound layer 150 covers a side surface of the first redistribution structure 120 facing away from the chip 130 and a sidewall of the chip 130, and the first molding compound layer 150 exposes a top surface of the chip 130 facing away from the interposer 100. This reduces the thickness of the first molding compound layer 150, reduces the degree of warpage to be improved later, and reduces the thickness of the chip package structure.
In other embodiments, the first molding compound layer 150 may cover a side surface of the first redistribution structure 120 facing away from the chip 130, a sidewall of the chip 130, and a top surface of the chip 130 facing away from the interposer 100.
Referring to fig. 5, a carrier 160 is bonded to a side surface of the first molding layer 150 facing away from the interposer 100.
In this embodiment, the carrier sheet 160 is a silicon carrier sheet. In other embodiments, the slide may also be a glass slide.
In one embodiment, the carrier sheet 160 has a thickness of 700 μm to 800 μm. The slide glass 160 has a thickness not too small, a certain rigidity, and a good support performance.
It should be noted that, without forming the subsequent second molding compound layer, theoretically, the thicker the thickness of the carrier is, the more beneficial the warpage of the chip package structure is to be reduced in the chip packaging process, however, the thickness of the carrier is practically limited, and the carrier with the required thickness cannot be arbitrarily selected.
Referring to fig. 6, a second molding layer 170 is formed on a surface of the carrier sheet 160 facing away from the first molding layer 150, and the thermal expansion coefficients of the carrier sheet 160 are respectively smaller than the thermal expansion coefficient of the second molding layer 170 and the thermal expansion coefficient of the first molding layer 150.
The first molding layer 150, the carrier sheet 160 and the second molding layer 170 constitute a sandwich structure. Because the thermal expansion coefficient of the carrier sheet 160 is smaller than the thermal expansion coefficient of the second molding layer 170 and the thermal expansion coefficient of the first molding layer 150, respectively, the acting force of the second molding layer 170 on the carrier sheet 160 is suitable for offsetting partial acting force of the first molding layer 150 on the carrier sheet 160, so that the warping degree of the carrier sheet 160 is reduced, and when the warping degree of the carrier sheet 160 is reduced, the warping degree of the whole chip packaging structure is reduced.
It should be noted that, in the present application, in the process of reducing the warpage of the chip package structure, the acting force of the second molding compound 170 on the carrier 160 is adapted to offset a part of the acting force of the first molding compound 150 on the carrier 160, so that the requirement for the thickness of the carrier itself is reduced, that is, the carrier purchased in the market can completely meet the use requirement of the present application. The thickness of the slide sheet 160 is 700 mu m-800 mu m.
It should be noted that, in the present application, after the second molding compound layer 170 is formed, and before the surface of the interposer 100 facing away from the first molding compound layer 150 is thinned subsequently, the chip package structure still has a slight warpage, and the warpage of the chip package structure in fig. 6 and the warpage of the chip package structure in fig. 5 and 4 are both toward the same side of the chip package structure. The degree of warpage of the chip package structure in fig. 5 is lower than that of the chip package structure in fig. 4. The degree of warpage of the chip package structure in fig. 6 is lower than that of the chip package structure in fig. 5.
In one embodiment, the difference between the thermal expansion coefficient of the first molding layer 150 and the thermal expansion coefficient of the carrier sheet 160 is less than or equal to 7.3ppm/K, such as 7ppm/K, 6ppm/K, 5 ppm/K; the difference between the thermal expansion coefficient of the second molding layer 170 and the thermal expansion coefficient of the carrier sheet 160 is less than or equal to 7.3ppm/K, such as 7ppm/K, 6ppm/K, 5 ppm/K.
If the difference between the thermal expansion coefficient of the first molding compound layer 150 and the thermal expansion coefficient of the carrier 160 is greater than 7.3ppm/K, the warpage of the chip package structure in fig. 4 is too large, which is not favorable for subsequent improvement. Because the difference between the thermal expansion coefficient of the first molding compound layer 150 and the thermal expansion coefficient of the carrier sheet 160 is greater than 7.3ppm/K, the difference between the thermal expansion coefficient of the second molding compound layer 170 and the thermal expansion coefficient of the carrier sheet 160 is selected to be less than or equal to 7.3ppm/K, so that the thermal expansion coefficient of the second molding compound layer 170 is not too large, and the warping degree of the chip packaging structure is prevented from being aggravated.
In one embodiment, the difference between the thermal expansion coefficient of the first molding layer 150 and the thermal expansion coefficient of the second molding layer 170 is greater than or equal to 0 and less than or equal to 1ppm/K, such as 0.8ppm/K, 0.6ppm/K, 0.4ppm/K, 0.2ppm/K, 0 ppm/K. This allows the force of the second molding layer 170 against the slide 160 to better counter the force of the first molding layer 150 against the slide 160. Preferably, the thermal expansion coefficient of the second molding layer 170 is equal to that of the first molding layer 150, and the material of the second molding layer 170 is the same as that of the first molding layer 150.
In this embodiment, the thickness of the second plastic package layer 170 is smaller than that of the first plastic package layer 150, so that after the second plastic package layer is formed, the chip package structure in fig. 6 further has an upward warpage for resisting a stress released in the interposer after the surface of the interposer 100 facing away from the first plastic package layer 150 is thinned subsequently.
Referring to fig. 7, after the second molding compound 170 is formed, the surface of the interposer 100 opposite to the first molding compound 150 is thinned.
Specifically, the surface of the interposer 100 facing away from the first molding compound layer 150 is thinned until the surface of the conductive plug 101 facing away from the chip 130 is exposed.
In this embodiment, after the surface of the interposer 100 facing away from the first plastic package layer 150 is thinned, the stress in the interposer 100 is released, and the stress released in the interposer 100 is suitable for being offset with the middle stress of the sandwich structure formed by the first plastic package layer 150, the carrier sheet 160, and the second plastic package layer 170, so that the warpage of the interposer 100 can be effectively reduced or even eliminated by adjusting the thickness of the second plastic package layer 170. In a preferred embodiment, the thickness of the second molding compound layer 170 is adjusted such that no warpage of the chip package structure exists after the surface of the interposer 100 facing away from the first molding compound layer 150 is thinned and before the back process is performed.
Referring to fig. 8, after the surface of the interposer 100 facing away from the first molding compound 150 is thinned, a backside process is performed.
The back process comprises the following steps: forming a second redistribution structure 180 on a surface of the interposer 100 opposite to the first molding compound 150; a solder ball 190 is formed on the surface of the second redistribution structure 180.
The second redistribution structure 180 includes: a second insulating layer and a second redistribution conductive layer in the second insulating layer.
The second redistribution structure 180 is electrically connected to the conductive plug 101, and in particular, the second redistribution conductive layer is electrically connected to the conductive plug 101.
In this embodiment, the process of forming the second redistribution structure 180 is a relatively fine process, and the patterning process usually adopts a photolithography process, such as exposure, development, and etching.
The process of forming the second redistribution structure 180 has a strict requirement on the degree of warpage of the chip package structure, i.e., the degree of warpage of the chip package structure is required to be minimal or no.
In the lithography equipment adopted in the second rewiring structure, an arm or a working platform vacuum adsorbs the front surface of the chip packaging structure, however, the adsorption force of the lithography equipment vacuum on the chip packaging structure is weak, if the warping degree of the chip packaging structure before the back surface process is carried out is large, the lithography equipment can alarm that the process cannot be carried out under the conditions that the chip packaging structure is not easily identified by a mechanical arm, the chip is taken from the chip packaging structure, the sensor scanning (mapping) is difficult, and the wafer edge protection ring cannot be pre-aligned or is placed to be stuck. If a large warpage exists, the conventional lithography equipment cannot mainly rely on the adsorption force of vacuum on the chip packaging structure to flatten the surface of the chip packaging structure, so that the lithography pattern is shifted, and the pattern of the second rewiring structure cannot meet the requirement.
In this embodiment, after the surface of the interposer 100 facing away from the first molding compound 150 is thinned and before the back process is performed, the warpage of the chip package structure is greatly reduced, which is beneficial to completing the fine operation of the second redistribution structure 180.
Referring to fig. 9, after the back process is performed, the second molding layer 170 and the carrier sheet 160 are removed.
The process of removing the second molding compound 170 and the carrier sheet 160 is a debonding process, and specifically, the carrier sheet 160 and the first molding compound 150 are subjected to a mechanical or thermal slip debonding process to remove the second molding compound 170 and the carrier sheet 160.
Since the second molding layer 170 and the carrier 160 are removed after the back process is performed, the thickness of the chip package structure is reduced. After removing the second molding layer 170 and the carrier film 160, the following processes further include: scribing process and flip-chip assembly process.
It should be noted that even though the chip package structure is warped after the second molding layer 170 and the carrier 160 are removed, the back process of the chip package process is completed, so that the fine process of the back process is not affected. The scribing process and the flip-chip assembly process have low requirements on the warping degree of the chip packaging structure, so that the scribing process and the flip-chip assembly process cannot be influenced even if the chip packaging structure is warped after the second plastic packaging layer 170 and the carrier film 160 are removed.
Correspondingly, the embodiment further provides a chip packaging structure, referring to fig. 8, including:
an interposer 100;
a chip 130 located at one side of the interposer 100;
a first molding compound layer 150 located on one side of the interposer 100 and covering a sidewall of the chip 130;
a carrier sheet 160 located on a side surface of the first plastic package layer 150 opposite to the interposer 100;
the second plastic package layer 170 is located on a side surface of the carrier sheet 160 opposite to the first plastic package layer 150, and the thermal expansion coefficients of the carrier sheet 160 are respectively smaller than the thermal expansion coefficient of the second plastic package layer 170 and the thermal expansion coefficient of the first plastic package layer 150.
In this embodiment, the interposer 100 is a silicon interposer. In other embodiments, the interposer may also be selected from other semiconductor materials.
The interposer 100 has a conductive plug 101 extending through the interposer.
The number of the conductive plugs 101 may be several.
The chip packaging structure further comprises: a first redistribution structure 120 located on one side surface of the interposer 100 and the conductive plug 101, the first redistribution structure 120 being electrically connected to the conductive plug 101 and the chip 130; the first molding compound layer 150 also covers the first redistribution structure 120.
The first rewiring structure 120 includes a first insulating layer 121 and a first rewiring conductive layer 122 in the first insulating layer 121.
The chip 130 is electrically connected to the first rewiring structure 120 through conductive microspheres 140.
The chip 130 is placed upside down on the first rewiring structure 120.
In this embodiment, a distance from a surface of the first molding compound layer 150, which faces away from the interposer 100, to the interposer 100 is less than or equal to a distance from a surface of the chip 130, which faces away from the interposer 100, to the interposer 100; the carrier sheet 160 is also bonded to a surface of the chip 130 facing away from the interposer 100.
In other embodiments, the first molding compound layer also covers the top surface of the chip facing away from the interposer 100.
In one embodiment, the difference between the coefficient of thermal expansion of the first molding layer 150 and the coefficient of thermal expansion of the carrier sheet 160 is less than or equal to 7.3 ppm/K; the difference between the thermal expansion coefficient of the second plastic packaging layer 170 and the thermal expansion coefficient of the slide glass 160 is less than or equal to 7.3 ppm/K.
The difference between the thermal expansion coefficient of the first molding layer 150 and the thermal expansion coefficient of the second molding layer 170 is greater than or equal to 0 and less than or equal to 1 ppm/K.
The thickness of the second molding layer 170 is smaller than that of the first molding layer 150.
In this embodiment, the carrier sheet 160 is a silicon carrier sheet. In other embodiments, the slide may also be a glass slide.
The thickness of the slide sheet 160 is 700 μm to 800 μm.
The chip packaging structure further comprises: a second rewiring structure 180 located on the other side surfaces of the interposer 100 and the conductive plug 101, the second rewiring structure 180 being electrically connected to the conductive plug 101; and a solder ball 190 on a surface of the second redistribution structure 180.
Another embodiment of the present invention further provides a chip packaging method, and the difference between the present embodiment and the chip packaging method provided by the foregoing embodiment is: and removing the second plastic packaging layer after the back process is carried out.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (15)

1. A method of chip packaging, comprising:
providing an adapter plate;
arranging a chip on one side of the adapter plate;
forming a first plastic packaging layer covering the side wall of the chip on one side of the adapter plate;
bonding a slide glass on the surface of one side, back to the adapter plate, of the first plastic packaging layer;
forming a second plastic packaging layer on the surface of one side, back to the first plastic packaging layer, of the slide glass, wherein the thermal expansion coefficients of the slide glass are respectively smaller than the thermal expansion coefficient of the second plastic packaging layer and the thermal expansion coefficient of the first plastic packaging layer;
and thinning the surface of one side of the adapter plate, which faces away from the first plastic package layer, after the second plastic package layer is formed.
2. The chip packaging method according to claim 1, wherein the difference between the thermal expansion coefficient of the first molding compound layer and the thermal expansion coefficient of the carrier is less than or equal to 7.3 ppm/K; the difference between the thermal expansion coefficient of the second plastic packaging layer and the thermal expansion coefficient of the slide glass is less than or equal to 7.3 ppm/K.
3. The chip packaging method according to claim 1 or 2, wherein a difference between the thermal expansion coefficient of the first molding layer and the thermal expansion coefficient of the second molding layer is 0ppm/K or more and 1ppm/K or less.
4. The chip packaging method according to claim 1, wherein a distance from a side surface of the first molding compound layer facing away from the interposer to the interposer is smaller than or equal to a distance from a side surface of the chip facing away from the interposer to the interposer; the carrier is also bonded on the surface of one side, back to the adapter plate, of the chip.
5. The chip packaging method according to claim 1, further comprising: before a chip is arranged on one side of the adapter plate, forming a conductive plug in the adapter plate with partial thickness; after the conductive plug is formed, a first rewiring structure is formed on one side surface of the adapter plate and one side surface of the conductive plug, and the first rewiring structure is electrically connected with the conductive plug;
after a chip is arranged on one side of the adapter plate, the chip is electrically connected with the first rewiring structure; after the first plastic packaging layer is formed, the first plastic packaging layer also covers the first rewiring structure;
and thinning the surface of the adapter plate back to one side of the first plastic packaging layer until the conductive plug is exposed, wherein the surface of the conductive plug back to one side of the chip.
6. The chip packaging method according to claim 1, wherein the thickness of the second molding compound layer is smaller than the thickness of the first molding compound layer.
7. The chip packaging method according to claim 1, wherein the thickness of the carrier sheet is 700 μm to 800 μm.
8. The chip packaging method according to claim 1, further comprising: and thinning the surface of one side of the adapter plate, which faces away from the first plastic package layer, and then carrying out a back process.
9. The chip packaging method according to claim 8, further comprising: and after the back surface process is carried out, removing the second plastic packaging layer and the slide glass.
10. A chip package structure, comprising:
an adapter plate;
the chip is positioned on one side of the adapter plate;
the first plastic packaging layer is positioned on one side of the adapter plate and covers the side wall of the chip;
the slide glass is positioned on the surface of one side, back to the adapter plate, of the first plastic packaging layer;
and the second plastic package layer is positioned on the surface of one side of the slide glass, which is back to the first plastic package layer, and the thermal expansion coefficients of the slide glass are respectively smaller than the thermal expansion coefficient of the second plastic package layer and the thermal expansion coefficient of the first plastic package layer.
11. The chip package structure according to claim 10, wherein the difference between the thermal expansion coefficient of the first molding compound layer and the thermal expansion coefficient of the carrier is less than or equal to 7.3 ppm/K; the difference between the thermal expansion coefficient of the second plastic packaging layer and the thermal expansion coefficient of the slide glass is less than or equal to 7.3 ppm/K.
12. The chip package structure according to claim 10 or 11, wherein a difference between the thermal expansion coefficient of the first molding layer and the thermal expansion coefficient of the second molding layer is greater than or equal to 0 and less than or equal to 1 ppm/K.
13. The chip package structure according to claim 10, wherein a thickness of the second molding layer is smaller than a thickness of the first molding layer.
14. The chip package structure according to claim 10, wherein the thickness of the carrier sheet is 700 μm to 800 μm.
15. The chip package structure according to claim 10, wherein the interposer has a conductive plug therein extending through the interposer; the chip packaging structure further comprises: the first rewiring structure is positioned on one side surface of the adapter plate and the conductive plug and is electrically connected with the conductive plug and the chip; the first plastic packaging layer also covers the first rewiring structure; the second rewiring structure is positioned on the other side surfaces of the adapter plate and the conductive plug and is electrically connected with the conductive plug; and the solder ball is positioned on the surface of the second rewiring structure.
CN202110327890.7A 2021-03-26 2021-03-26 Chip packaging method and chip packaging structure Active CN113078069B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110327890.7A CN113078069B (en) 2021-03-26 2021-03-26 Chip packaging method and chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110327890.7A CN113078069B (en) 2021-03-26 2021-03-26 Chip packaging method and chip packaging structure

Publications (2)

Publication Number Publication Date
CN113078069A true CN113078069A (en) 2021-07-06
CN113078069B CN113078069B (en) 2022-07-19

Family

ID=76610782

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110327890.7A Active CN113078069B (en) 2021-03-26 2021-03-26 Chip packaging method and chip packaging structure

Country Status (1)

Country Link
CN (1) CN113078069B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150235874A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
CN106611713A (en) * 2015-10-27 2017-05-03 美光科技公司 Semiconductor package and method for forming the same
US20200058570A1 (en) * 2018-08-14 2020-02-20 Texas Instruments Incorporated Semiconductor package with multilayer mold

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150235874A1 (en) * 2014-02-19 2015-08-20 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
CN106611713A (en) * 2015-10-27 2017-05-03 美光科技公司 Semiconductor package and method for forming the same
US20200058570A1 (en) * 2018-08-14 2020-02-20 Texas Instruments Incorporated Semiconductor package with multilayer mold

Also Published As

Publication number Publication date
CN113078069B (en) 2022-07-19

Similar Documents

Publication Publication Date Title
US11456251B2 (en) Semiconductor structure, package structure, and manufacturing method thereof
US7256073B2 (en) Semiconductor device and manufacturing method thereof
EP1801866B1 (en) Method of manufacturing a semiconductor device
CN101355058B (en) Semiconductor device and method of manufacturing the same
US8105856B2 (en) Method of manufacturing semiconductor device with wiring on side surface thereof
EP1505643B1 (en) Semiconductor device and manufacturing method thereof
KR20210003923A (en) Die stacking for multi-tier 3D integration
US11749651B2 (en) Semiconductor package and manufacturing method thereof
US11502040B2 (en) Package structure and semiconductor pacakge
EP1453090A2 (en) Manufacturing method of semiconductor device
TW202105666A (en) Chip structure
US11899242B2 (en) Method of manufacturing a packaged device with optical pathway
EP1478021A1 (en) Semiconductor device and manufacturing method thereof
US10679915B2 (en) Package structure and manufacturing method thereof
CN113078069B (en) Chip packaging method and chip packaging structure
US8592286B2 (en) Ultra-thin wafer system and method of manufacture thereof
US10867963B2 (en) Die stack structure and method of fabricating the same
JP4371719B2 (en) Semiconductor device and manufacturing method thereof
US20240105679A1 (en) Semiconductor package and method of fabricating the same
US20230063147A1 (en) Semiconductor package
US20220278075A1 (en) Packaging structure and formation method thereof
TW202131472A (en) Semiconductor device and method of fabricating the same
CN100334699C (en) Method of making connecting lead wire of chip back surface
KR20230117688A (en) Package with integrated optical die and method forming same
CN117690804A (en) Wafer level packaging method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant