CN113067677A - Intelligent coding and decoding processing system and method applied to high-speed communication - Google Patents
Intelligent coding and decoding processing system and method applied to high-speed communication Download PDFInfo
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- 230000009466 transformation Effects 0.000 claims abstract description 37
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
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- 238000007906 compression Methods 0.000 claims description 17
- 230000002776 aggregation Effects 0.000 claims description 12
- 238000004220 aggregation Methods 0.000 claims description 12
- 238000013507 mapping Methods 0.000 claims description 11
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- 230000003287 optical effect Effects 0.000 description 11
- 230000005540 biological transmission Effects 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 238000012795 verification Methods 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 7
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- 238000005516 engineering process Methods 0.000 description 4
- 238000004422 calculation algorithm Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
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- 238000001228 spectrum Methods 0.000 description 3
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- 238000009826 distribution Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
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- 238000012937 correction Methods 0.000 description 1
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- 238000001514 detection method Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
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- 238000011160 research Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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Abstract
The invention relates to an intelligent coding and decoding processing system and method applied to high-speed communication, comprising the following steps: a multi-line pushing processing process and a multi-line traction processing process; the multi-line pushing processing process comprises a first functional module and a division transformation cell, and the division transformation cell conducts division transformation on data of a data source so as to be in butt joint with data output by the subsequent first functional module; the multi-line traction processing process comprises a second functional module and a polymerization conversion cell, and the polymerization conversion cell performs polymerization conversion on data output by the second functional module to obtain target data. The method expands the single-line coding and decoding processing process in the traditional communication system to the multi-line coding and decoding processing process, and improves the parallelism and the expandability of the coding and decoding process in the communication system.
Description
Technical Field
The invention relates to the technical field of communication digital signals, in particular to an intelligent coding and decoding processing system and method applied to high-speed communication.
Background
After the third generation mobile communication system has become a history, the implementation of the fourth generation mobile communication system has been approaching the end, and in the past decades, mobile communication has been rapidly developed, and the third generation mobile communication system has advanced mobile communication for a long time, but 3G communication technology has many shortcomings, so that when the third generation mobile communication has not been completely spread, research on the 4 th generation mobile communication system has been started in many countries. Compared with 3G, 4G has a qualitative leap in technology and application, and not only adds improved technology on the basis of third-generation mobile communication, but also can be sure that 4G communication creates a wireless world which is more perfect than 3G communication, and creates a plurality of applications which are hard to imagine in the 3G era. In recent years, fifth generation mobile communication systems have become a focus of attention in the communication industry. There are two major driving forces for the development of 5G. On one hand, the fourth generation mobile communication system 4G is completely commercialized; on the other hand, the demand for mobile data has increased explosively, and it is difficult for the existing mobile communication system to meet the rapidly increasing demand. With the development of the mobile internet, more and more devices are accessed into the mobile network, and at the same time, new services and applications are in endlessly, global mobile broadband users have 90 billion in 2018, and the capacity of the mobile communication network in 2020 has increased by 1000 times on the network capacity in 2018. The explosion of mobile data traffic presents a significant challenge to existing networks. In order to meet the contradiction between the increasing mobile traffic demand and the limited bandwidth of the mobile communication equipment, the development and implementation of the 5G mobile communication network are urgently needed.
TD-SCDMA is a third generation mobile communication system standard independently proposed by China, adopts a series of advanced technologies at that time, and has higher system performance and spectrum utilization rate. However, one major weak link affecting the maturity of the TD-SCDMA industry in our country is the baseband processing core chip, i.e., the baseband system-level chip. In order to make up for the weak link, many companies both at home and abroad develop and release TD-SCDMA baseband chips, and spread communication limited company (now more named as Violet Brilliant) is one of them. The company has already introduced the first TD-SCDMA core chip in the world in 2004, and the creation of this chip has taken the first step of the baseband processing core chip in China, but it has only taken a small step of the practical work of channel coding and decoding.
The design of the current integrated circuit has entered the era of a super-large scale integrated circuit, and forms a situation that a CPU, a GPU and an FPGA are tripodal, the scale and the complexity of a chip are exponentially increased, and particularly for the super-large scale integrated circuit such as a baseband chip, more manpower and material resources are needed to be spent to design and verify in order to ensure the correctness of the function of the designed chip, so that the communication field can be ensured to catch up with and be ahead of the international advanced level. Engineers currently typically spend 60% to 80% of their time designing a proof. Therefore, advanced and efficient verification methods, languages and tools are needed to effectively improve the verification efficiency, shorten the product development time and speed up the market step. Although various design verification methods such as tangible form verification, numerical calculation, programmable logic device implementation and the like can be selected, in practice, engineers prefer simulation-based verification, which is also a design method preferred by communication chip design companies in the mainstream at present, but the design method has the defects that most of manpower and material resources are occupied for verification tasks, and the investment in early design, particularly numerical calculation, simulation and later verification implementation, is less, so that a passive situation of large middle and small ends is caused.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the technical defects that most of manpower and material resources are occupied for verification tasks, and the investment in early design, particularly numerical calculation, simulation and later verification is less.
In order to solve the above technical problem, the present invention provides an intelligent encoding and decoding processing system for high-speed communication, comprising:
a multi-line pushing processing process and a multi-line traction processing process; the multi-line pushing processing process comprises a first functional module and a division transformation cell, and the division transformation cell conducts division transformation on data of a data source so as to be in butt joint with data output by the subsequent first functional module; the multi-line traction processing process comprises a second functional module and a polymerization conversion cell, and the polymerization conversion cell performs polymerization conversion on data output by the second functional module to obtain target data.
Preferably, the first functional module includes a plurality of first functional cells, and the plurality of first functional cells sequentially process the data output by the division-transformed cell to complete the encoding.
Preferably, one or more of the following operations are also performed between two adjacent first functional cells: transitive, divergent, convergent, and full mapping; the division-transformed cell is one or more of transiting, diverging, converging, and fully mapping with its neighboring first functional cell.
Preferably, the first functional cell is a compression-encoded cell, a check-encoded cell, an equalization-encoded cell, or a modulated cell.
Preferably, the second functional module comprises a plurality of second functional cells, and the plurality of second functional cells process data to be input to the aggregate transformed cells.
Preferably, one or more of the following operations are also performed between two adjacent second functional cells: transitive, divergent, convergent, and full mapping; the polymerization transformation cell is one or more of transmitted, diverged, converged and fully mapped with the adjacent second functional cell.
Preferably, the second functional module is a demodulation cell, an equalization decoding cell, a check decoding cell or a compression decoding cell.
Preferably, the aggregate transform cell performs one or more of the following operations on the data: aggregation, padding, dropping, and transformation; the dividing and transforming cell performs one or more of the following operations on the data: segmentation, padding, discarding, and transformation.
Preferably, the smallest data processing unit corresponding to the aggregation transformation cell and/or the division transformation cell is a bit.
The invention also discloses an intelligent coding and decoding processing method applied to high-speed communication, and the data is processed based on the intelligent coding and decoding processing system.
Compared with the prior art, the technical scheme of the invention has the following advantages:
1. the single-line coding and decoding processing process in the traditional communication system is expanded to the multi-line coding and decoding processing process, so that the parallelism and the expandability of the coding and decoding process in the communication system are improved.
2. The concept of cell is introduced into the high-speed communication coding and decoding processing process, and the flexibility and controllability of system processing are improved.
3. The concept of data splitting and aggregation transformation based on the minimum bit level is introduced into the coding and decoding processing process of the high-speed communication system, so that the flexibility of seamless butt joint and data preprocessing of the coding and decoding processing system of the high-speed communication system and equipment or devices or modules such as data sources and data destination data, transmission, distribution, storage and the like is further improved.
Drawings
FIG. 1 is a schematic structural diagram of a multi-thread pushing process and a multi-thread pulling process according to the present invention;
FIG. 2 is a schematic diagram of an intelligent codec processing system for high-speed communications;
FIG. 3 is a graph of the functional relationship between adjacent cells, wherein (a) is a graph of the relationship between adjacent first functional cells; (b) a graph of the relationship between adjacent second functional cells;
FIG. 4 is a diagram illustrating a codec processing system according to a first embodiment;
FIG. 5 is a diagram illustrating a codec processing system according to a second embodiment;
fig. 6 is a schematic diagram of a codec processing system according to a third embodiment.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
Referring to fig. 1 to 5, the present invention discloses an intelligent encoding and decoding processing system for high-speed communication, which includes a multi-line push processing procedure and a multi-line pull processing procedure.
The multiline pushing processing process comprises a first functional module and division transformation cells, and the division transformation cells carry out division transformation on data of the data source so as to be in butt joint with data output by the subsequent first functional module.
The multi-line traction processing process comprises a second functional module and a polymerization conversion cell, and the polymerization conversion cell performs polymerization conversion on data output by the second functional module to obtain target data.
The first functional module comprises a plurality of first functional cells, and the first functional cells sequentially process data output by the division transformation cells to complete coding. The aggregate transform cell performs one or more of the following operations on the data: aggregation, padding, dropping, and transformation. The split-transform cell performs one or more of the following operations on the data: segmentation, padding, discarding, and transformation.
And performing one or more of the following operations between two adjacent first functional cells: transitive, divergent, convergent, and fully mapped. The division-transformed cell is one or more of transiting, diverging, converging, and fully mapping with its neighboring first functional cell. The first functional cell is a compression encoded cell, a check encoded cell, a balance encoded cell, or a modulation cell.
The second functional module includes a plurality of second functional cells that process data for input to the aggregate transformed cells. And one or more of the following operations are also carried out between two adjacent second functional cells: transitive, divergent, convergent, and full mapping; the polymerization transformed cell is one or more of passed, diverged, converged and fully mapped to a second functional cell adjacent to the polymerization transformed cell. The second functional module is a demodulation cell, an equalization decoding cell, a check decoding cell or a compression decoding cell.
The minimum data processing unit corresponding to the aggregation transformation cell and/or the division transformation cell is a bit.
Fig. 2 shows an embodiment of a codec processing system according to the present invention. In the multi-line pushing process, the first functional cells are compression coding cells, check coding cells, balance coding cells and modulation cells in sequence. In the multi-line traction processing process, the second functional cells are demodulation cells, equalization decoding cells, check decoding cells and compression decoding cells in sequence. The cells in the same hierarchical relationship may be the same or different, for example, the compression encoding between different lines may be the same algorithm or different algorithms. The purpose of compression coding is to reduce the data volume and complete the compression function of data source data on the premise of not losing useful information. The check coding is mainly used for increasing the reliability of communication or increasing the anti-interference performance of the whole system, so that the spectrum characteristic of a data code stream is adapted to the spectrum characteristic of a channel, and the error detection (correction) capability is increased according to the characteristic requirement of a wireless communication channel. The purpose of equalization coding is to maximally disperse the concentrated errors generated by bursts during channel transmission, so that the signals are distributed uniformly and disorderly in time and frequency as much as possible. Modulation is a technique whereby a signal is injected into a carrier wave, which is modulated with the signal to convert the original signal into an electrical wave signal suitable for transmission, the modulation serving to place the message into a message carrier for transmission or processing. The single-wire traction processing process comprises compression decoding, check decoding, equalization decoding and demodulation. The single-wire pull processing procedure is the reverse of the single-wire push processing.
In the multi-line processing process, a data division transformation cell of a data source and a pre-aggregation transformation processing cell of target data are added, after the division transformation cell completes seamless reception of data of the data source, the division transformation cell performs functions of division, filling, discarding, transformation and the like on the data and serves as data preprocessing of subsequent functional module (compression coding, check coding, balanced coding and modulation) operation (the described data processing unit with the minimum operation is a bit); the aggregation transformation processing cell as a preprocessing module for the target data mainly aims to ensure seamless connection with devices or modules for processing, transmitting, distributing, storing and the like of the target data, aggregation transformation processing is performed after the data is subjected to traction processing (demodulation, equalization decoding, check decoding, compression decoding), and functions of aggregation, padding, discarding, transformation and the like are performed on the data as preprocessing on the target data (the data processing unit with the minimum operation is a bit).
As shown in fig. 2, the main relationship between the minimum unit cells (specific algorithms in compression coding, check coding, equalization coding, modulation, demodulation, equalization decoding, check decoding, and compression decoding)) discussed in this patent is the transfer relationship shown by the solid arrow shown in fig. 2, but the relationship between the cells (cells) is not limited thereto, and there is a relationship shown in fig. 3 in which the dotted arrow shown in fig. 2 diverges, converges, and is completely mapped.
The processing method provided by the invention can realize parallel operation (multi-line transmission operation), single-line processing (single-line transmission operation as shown in fig. 1), partial parallel operation (operation with coexistence of transmission, divergence, convergence and complete mapping relation) and complete mapping operation (operation with complete mapping relation) according to the relation between computing resources and operation processing requirements of the communication system as shown in fig. 2 and fig. 3.
The invention has the following beneficial effects:
1. the single-line coding and decoding processing process in the traditional communication system is expanded to the multi-line coding and decoding processing process, so that the parallelism and the expandability of the coding and decoding process in the communication system are improved.
2. The concept of cell is introduced into the high-speed communication coding and decoding processing process, and the flexibility and controllability of system processing are improved.
3. The concept of data splitting and aggregation transformation based on the minimum bit level is introduced into the coding and decoding processing process of the high-speed communication system, so that the flexibility of seamless butt joint and data preprocessing of the coding and decoding processing system of the high-speed communication system and equipment or devices or modules such as data sources and data destination data, transmission, distribution, storage and the like is further improved.
The technical solution of the present invention is further described below with reference to specific examples.
Example one
As shown in fig. 4, this embodiment is a specific example of the intelligent codec processing method in the high-speed communication system, but is not limited thereto, wherein, the sending part of 10G optical Ethernet/RapidIO/XDMA PCIE corresponds to the data source of figure 2, the receiving part of 10G optical Ethernet/RapidIO/XDMA PCIE corresponds to the target data of figure 2, the Block division and the data stream division correspond to the split transformation of figure 2, the Block combination and the data stream combination correspond to the aggregation transformation of figure 2, the MP3/H264 audio-video coding corresponds to the compression coding of figure 2, the MP3/H264 audio-video decoding corresponds to the compression decoding of figure 2, the CRC/MD/RS corresponds to the LDPC coding and decoding of figure 2, the interleaving/scrambling corresponds to the equalization coding of figure 2, the deinterleaving/descrambling corresponds to the equalization decoding of figure 2, the QAM modulation corresponds to the modulation of figure 2, and the QAM demodulates corresponds to the demodulation of figure 2.
Example two
As shown in fig. 5, this embodiment is a specific example of the processing method of intelligent coding and decoding in the high-speed communication system, but is not limited thereto, wherein 10G ethernet Transmit corresponds to the data source of fig. 2, 10G ethernet Receive corresponds to the destination data of fig. 2, Block division corresponds to the split transform of fig. 2, Block combination corresponds to the aggregate transform of fig. 2, CRC32/RS corresponds to the check coding and decoding of fig. 2, interleaving/scrambling corresponds to the equalization coding of fig. 2, deinterleaving/descrambling corresponds to the equalization decoding of fig. 2, QAM64 modulation corresponds to the modulation of fig. 2, and DQAM64 demodulation corresponds to the demodulation of fig. 2.
The data pushing process comprises the following steps: the data code stream (for example, 10Gbps) given by a CCU (Communication Control Unit) is received through a data input interface (for example, a 10G SFP optical module), code block segmentation (block segmentation for facilitating subsequent processing) is performed, CRC32 encoding, ENCODE (RS encoding), scrambling (preventing co-channel interference of a receiving end), modulation (QAM64, increasing bandwidth utilization) is performed, and an IQ signal is generated. The data pulling process is a reverse processing process, and IQ signals are demodulated (DQAM64, converting from symbols to digital signals), descrambled, Decode (RS), CRC, code block merged (block merged, converting to data that 10G MAC can receive), and then the data are transmitted back to the CCU through the 10Gbps optical module.
The data source interface provides a data code stream (for example, 10Gbps ethernet data), after the data code stream is encoded, the data code stream rate is slightly increased (according to different CRC/MD/LDPC/RS encoding), and then the data code stream is subjected to processing work such as modulation (QPSK, QAM, etc., in this example, the current modulation mode is 64QAM), and signals subjected to encoding and decoding processing with different bandwidths can be obtained according to different modulation modes. Modulating according to 64QAM, calculating according to 10Gbps data code stream, and the required processing bandwidth of coding and decoding signals is 2(10 × 1.2/6) GsHz (two paths of I/Q) at most.
EXAMPLE III
The encoding and decoding process takes fig. 6 as an example, takes a 10G optical module as an example, data received from the 10G optical module is divided into 8 lines in sequence for data pushing, data pulling is performed through the 8 lines in the same way, and finally, the data is synthesized in one path and sent back through the 10G optical module. Before a data packet received by a 10G optical module MAC is split into 8 lines for data pushing, 10G MAC data is split into data blocks with equal length of 1888 byte, the data blocks are split into 8 lines for coding respectively, and the size of each line of the data blocks is 236 byte. And the MAC data sent to the 10G optical module is treated equally. And merging the data blocks with the size of 236 bytes after decoding the 8-line data into data blocks with the same length of 1888 bytes, merging the data blocks in sequence, sending the merged data blocks to a 10G MAC, and sending the merged data blocks to a 10G optical module.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. An intelligent encoding and decoding processing system applied to high-speed communication is characterized by comprising:
a multi-line pushing processing process and a multi-line traction processing process;
the multi-line pushing processing process comprises a first functional module and a division transformation cell, and the division transformation cell conducts division transformation on data of a data source so as to be in butt joint with data output by the subsequent first functional module;
the multi-line traction processing process comprises a second functional module and a polymerization conversion cell, and the polymerization conversion cell performs polymerization conversion on data output by the second functional module to obtain target data.
2. The system according to claim 1, wherein the first functional module comprises a plurality of first functional cells, and the first functional cells sequentially process the data outputted from the division-transformed cells to complete the encoding.
3. The intelligent coding and decoding processing system for high-speed communication according to claim 2, wherein one or more of the following operations are performed between two adjacent first functional cells: transitive, divergent, convergent, and full mapping;
the division-transformed cell is one or more of transiting, diverging, converging, and fully mapping with its neighboring first functional cell.
4. The intelligent codec processing system of claim 2, wherein the first functional cell is a compression coding cell, a check coding cell, an equalization coding cell or a modulation cell.
5. The intelligent codec processing system of claim 1, wherein the second functional module includes a plurality of second functional cells, and the plurality of second functional cells process data to be inputted to the conver cell.
6. The intelligent coding/decoding processing system for high-speed communication according to claim 5, wherein one or more of the following operations are performed between two adjacent second functional cells: transitive, divergent, convergent, and full mapping;
the polymerization transformation cell is one or more of transmitted, diverged, converged and fully mapped with the adjacent second functional cell.
7. The intelligent codec processing system according to claim 5, wherein the second functional module is a demodulation cell, an equalization decoding cell, a check decoding cell or a compression decoding cell.
8. The intelligent coding-decoding processing system applied to high-speed communication according to claim 1, wherein the convergent transform cell performs one or more of the following operations on data: aggregation, padding, dropping, and transformation; the dividing and transforming cell performs one or more of the following operations on the data: segmentation, padding, discarding, and transformation.
9. The intelligent codec processing system of claim 8, wherein the minimum data processing unit for the aggregate transform cell and/or the split transform cell is one bit.
10. An intelligent encoding and decoding processing method applied to high-speed communication, characterized in that the data is processed based on the intelligent encoding and decoding processing system of any one of claims 1-9.
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| US20080225965A1 (en) * | 2007-03-16 | 2008-09-18 | Zhouyue Pi | Methods and apparatus to improve performance and enable fast decoding of transmissions with multiple code blocks |
| CN112367144A (en) * | 2020-10-20 | 2021-02-12 | 西北工业大学 | High-speed data transmission system based on LDPC and parallel QPSK modulation and implementation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20080225965A1 (en) * | 2007-03-16 | 2008-09-18 | Zhouyue Pi | Methods and apparatus to improve performance and enable fast decoding of transmissions with multiple code blocks |
| CN112367144A (en) * | 2020-10-20 | 2021-02-12 | 西北工业大学 | High-speed data transmission system based on LDPC and parallel QPSK modulation and implementation method |
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