CN113067574B - Light PUF circuit adopting interconnection line deviation - Google Patents

Light PUF circuit adopting interconnection line deviation Download PDF

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CN113067574B
CN113067574B CN202110167190.6A CN202110167190A CN113067574B CN 113067574 B CN113067574 B CN 113067574B CN 202110167190 A CN202110167190 A CN 202110167190A CN 113067574 B CN113067574 B CN 113067574B
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gate
input end
output
inverter
input
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CN113067574A (en
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林烨
张跃军
王秋杰
李林
陈佳
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Ningbo University
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Ningbo University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET

Abstract

The invention discloses a lightweight PUF circuit adopting interconnection line deviation, which comprises a control module, a PUF array and an output module, wherein the PUF array is formed by arranging 64 PUF units according to 8 rows and 8 columns, each PUF unit respectively comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first metal wire, a second metal wire, a third metal wire, a first NAND gate, a second NAND gate and a first MOS (metal oxide semiconductor) transistor, the first MOS transistor is an NMOS (N-channel metal oxide semiconductor) transistor, the first metal wire can be coupled with the third metal wire to generate a coupling capacitor, the second metal wire can be coupled with the third metal wire to generate a coupling capacitor, when a first input end of the PUF unit is accessed with a signal, the third metal wire is respectively coupled with the first metal wire and the second metal wire to generate a coupling capacitor, so that the PUF unit is interfered, and the corresponding signal is output by the PUF unit; the method has the advantages that errors are not easy to occur in output logic, the reliability is high, and the occupied area is small.

Description

Light PUF circuit adopting interconnection line deviation
Technical Field
The invention relates to a PUF circuit, in particular to a lightweight PUF circuit adopting interconnection line deviation.
Background
With the explosion of the internet, the information security problem is more and more concerned by people. Network transactions are becoming popular in China and it is becoming more important to enhance security systems to secure our personal information and property. There are no two identical objects in the world, so that the final products will have different integrated circuit processes even if they are the same. In recent years, Physical Unclonable Function (PUF) technology has been introduced in the field of chip security as a secure key that cannot be copied, and researchers have published more and more scientific articles and comments about this. The output response of a PUF circuit is caused by process variations in its devices, and is unpredictable, making it difficult to replicate a PUF. PUF circuits have uniqueness, consistency, and reliability. Typical PUF circuits can be divided into two categories: memory-based PUF circuits and path delay-based PUF circuits. In the existing PUF circuit based on path delay, different delays are generated by process variations of gates, so that different output responses are generated.
With the rapid development of science, the size of the CMOS becomes smaller, which results in the transmission time of signals between devices becoming shorter and the cross-sectional area of the devices becoming smaller. Accordingly, the number of devices is gradually increased in the original place with the same area, which results in the increase of the number of wires between the devices by a multiple. As the number of lines increases, the area occupied by the PUF circuit increases, which is detrimental to the development of integrated circuits. With the progress of processing technology, the distances among the interconnection lines in the PUF circuit based on the path delay are smaller and smaller, so that a transverse capacitance is generated among multiple layers of metal, the delay of the interconnection lines is far larger than that of a gate circuit, and finally, a logic signal output by the PUF circuit based on the path delay is wrong, and the reliability is reduced. Further, when the PUF circuit based on the path delay is used for a chip for key generation and authentication, a large number of gates are required, which results in a large area, and particularly when high accuracy is required, the PUF circuit does not have lightweight characteristics.
Disclosure of Invention
The invention aims to solve the technical problem of providing a light-weight PUF circuit which is difficult to make mistakes in output logic, high in reliability and small in occupied area and adopts interconnection line deviation.
The technical scheme adopted by the invention for solving the technical problems is as follows: a lightweight PUF circuit adopting interconnection line deviation comprises a control module, a PUF array and an output module, wherein the control module is provided with a first control end, a second control end, a third control end, a first clock end, a second clock end, a third clock end and 8 output ends, the first control end of the control module is used for accessing a first control signal, the second control end of the control module is used for accessing a second control signal, the third control end of the control module is used for accessing a third control signal, the first control end, the second control end and the third control end of the control module are all high-level effective, the first clock end of the control module is used for accessing a first clock signal, the second clock end of the control module is used for accessing a second clock signal, and the third clock end of the control module is used for accessing a third clock signal, the frequency of the first clock signal is twice the frequency of the second clock signal, and the frequency of the second clock signal is twice the frequency of the third clock signal; the output module is provided with 8 input ends, 8 output ends, a first control end, a second control end, a third control end, a first clock end, a second clock end and a third clock end, wherein the first control end of the output module is used for accessing a fourth control signal, the second control end of the output module is used for accessing a fifth control signal, the third control end of the output module is used for accessing a sixth control signal, the first control end, the second control end and the third control end of the output module are all effective at high level, the first clock end of the output module is used for accessing a fourth clock signal, the second clock end of the output module is used for accessing a fifth clock signal, the third clock end of the output module is used for accessing a sixth clock signal, and the frequency of the fourth clock signal is twice the frequency of the fifth clock signal, the frequency of the fifth clock signal is twice the frequency of the sixth clock signal; the PUF array is formed by arranging 64 PUF units according to 8 rows and 8 columns, each PUF unit is respectively provided with a first input end, a second input end and an output end, the first input ends and the second input ends of the 8 PUF units positioned on the same row are all connected, the connection ends of the first input ends and the second input ends are used as one input end of the PUF array, the output ends of the 8 PUF units positioned on the same column are all connected, the connection ends of the 8 PUF units are used as one output end of the PUF array, the PUF array is provided with 8 input ends and 8 output ends, the 8 input ends of the PUF array are connected with the 8 output ends of the control module in a one-to-one correspondence mode, the 8 output ends of the PUF array are used for outputting 8-bit response signals; each PUF unit comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a first metal wire, a second metal wire, a third metal wire, a first NAND gate, a second NAND gate and a first MOS (metal oxide semiconductor) tube respectively, wherein the first MOS tube is an NMOS tube, the first NAND gate and the second NAND gate are respectively provided with a first input end, a second input end and an output end, the input end of the first phase inverter is connected with the input end of the third phase inverter, the connecting end of the first phase inverter is the first input end of the PUF unit, the output end of the first phase inverter is connected with the input end of the second phase inverter, the output end of the third phase inverter is connected with the input end of the fourth phase inverter, the output end of the second phase inverter is connected with one end of the first metal wire, and the other end of the first metal wire is connected with the first input end of the first NAND gate, the output end of the fourth inverter is connected with one end of the second metal wire, the other end of the second metal wire is connected with the second input end of the second nand gate, the second input end of the first nand gate is connected with the output end of the second nand gate, the output end of the first nand gate, the first input end of the second nand gate and the drain electrode of the first MOS transistor are connected, the gate of the first MOS transistor is the second input end of the PUF unit, the source of the first MOS transistor is the output end of the PUF unit, the third metal wire is located between the first metal wire and the second metal wire, the third metal wire is respectively parallel to the first metal wire and the second metal wire, and the first metal wire can be coupled with the third metal wire to generate a coupling capacitor, the second metal wire can be coupled with the third metal wire to generate a coupling capacitor, the first metal wire and the second metal wire are used as victim wires, the third metal wire is used as an attack wire, when a signal is accessed to the first input end of the PUF unit, the third metal wire is respectively coupled with the first metal wire and the second metal wire to generate a coupling capacitor, the third metal wire interferes with the PUF unit, and the corresponding signal is output by the PUF unit.
The control module comprises a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate and a ninth AND gate, wherein the first AND gate is a three-input AND gate and is provided with a first input end, a second input end, a third input end and an output end, the second AND gate, the third AND gate, the fourth AND gate, the fifth AND gate, the sixth AND gate, the seventh AND gate, the eighth AND gate and the ninth AND gate are four-input AND gates and are respectively provided with a first input end, a second input end, a third input end, a fourth input end and an output end, the first input end of the first AND gate is a first control end of the control module, the second input end of the first and gate is the second control end of the control module, the third input end of the first and gate is the third control end of the control module, the input end of the fifth inverter is the first clock end of the control module, the input end of the sixth inverter is the second clock end of the control module, the input end of the seventh inverter is the third clock end of the control module, the output end of the fifth inverter is respectively connected with the first input end of the second and gate, the first input end of the fourth and gate, the input end of the eighth inverter, the first input end of the sixth and gate and the first input end of the eighth and gate, and the output end of the sixth inverter is respectively connected with the second input end of the second and gate, the second input end of the third and gate, the third input end of the sixth and gate, The input end of the ninth inverter, the second input end of the sixth and gate and the second input end of the seventh and gate are connected, the output end of the seventh inverter is respectively connected with the third input end of the second and gate, the third input end of the third and gate, the input end of the tenth inverter, the third input end of the fourth and gate and the third input end of the fifth and gate, the output end of the eighth inverter is respectively connected with the first input end of the third and gate, the first input end of the fifth and gate, the first input end of the seventh and gate and the first input end of the ninth and gate, the output end of the ninth inverter is respectively connected with the second input end of the fourth and gate, the second input end of the fifth and gate, the second input end of the eighth and gate and the second input end of the ninth and gate, the output end of the tenth inverter is respectively connected with the third input end of the sixth AND gate, the third input end of the seventh AND gate, the third input end of the eighth AND gate and the third input end of the ninth AND gate, the output end of the first AND gate is respectively connected with the fourth input end of the second AND gate, the fourth input end of the third AND gate, the fourth input end of the fourth AND gate, the fourth input end of the fifth AND gate, the fourth input end of the sixth AND gate, the fourth input end of the seventh AND gate, the fourth input end of the eighth AND gate and the fourth input end of the ninth AND gate, and the output ends of the second AND gate, the third AND gate, the fourth AND gate, the fifth AND gate, the sixth AND gate, the seventh AND gate, the eighth AND gate and the ninth AND gate are used as 8 output ends of the control module.
The output module comprises an eleventh phase inverter, a twelfth phase inverter, a thirteenth phase inverter, a fourteenth phase inverter, a fifteenth phase inverter, a sixteenth phase inverter, a tenth and gate, an eleventh and gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a sixteenth and gate, a seventeenth and gate, an eighteenth and gate, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a ninth MOS tube, wherein the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are all NMOS tubes, the tenth and gate is a three-input and gate and has a first input end, a second input end, a third input end and an output end, and gate, the eleventh and gate, the sixteenth and gate, the thirteenth and gate, the fourteenth and gate, the sixteenth and gate, the fifteenth and gate, the sixteenth and gate, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube and the ninth MOS tube are NMOS tube, The twelfth AND gate, the thirteenth AND gate, the fourteenth AND gate, the fifteenth AND gate, the sixteenth AND gate, the seventeenth AND gate and the eighteenth AND gate are four-input AND gates and are respectively provided with a first input end, a second input end, a third input end, a fourth input end and an output end; the drain of the second MOS transistor, the drain of the third MOS transistor, the drain of the fourth MOS transistor, the drain of the fifth MOS transistor, the drain of the sixth MOS transistor, the drain of the seventh MOS transistor, the drain of the eighth MOS transistor, and the drain of the ninth MOS transistor are 8 input terminals of the output module, the source of the second MOS transistor, the source of the third MOS transistor, the source of the fourth MOS transistor, the source of the fifth MOS transistor, the source of the sixth MOS transistor, the source of the seventh MOS transistor, the source of the eighth MOS transistor, and the source of the ninth MOS transistor are 8 output terminals of the output module, the first input terminal of the tenth and gate is the first control terminal of the output module, and the second input terminal of the tenth and gate is the second control terminal of the output module, a third input end of the tenth and-gate is a third control end of the output module, an input end of the eleventh inverter is a first clock end of the output module, an input end of the twelfth inverter is a second clock end of the output module, an input end of the thirteenth inverter is a third clock end of the output module, an output end of the tenth and-gate is respectively connected with a fourth input end of the eleventh and-gate, a fourth input end of the twelfth and-gate, a fourth input end of the thirteenth and-gate, a fourth input end of the fourteenth and-gate, a fourth input end of the fifteenth and-gate, a fourth input end of the sixteenth and-gate, a fourth input end of the seventeenth and-gate and a fourth input end of the eighteenth and-gate, and an output end of the eleventh inverter is respectively connected with an input end of the fourteenth inverter, A first input end of an eleventh AND gate, a first input end of a thirteenth AND gate, a first input end of a fifteenth AND gate and a first input end of a seventeenth AND gate, an output end of the twelfth inverter is respectively connected with an input end of the fifteenth inverter, a second input end of the eleventh AND gate, a second input end of the twelfth AND gate, a second input end of the fifteenth AND gate and a second input end of the sixteenth AND gate, an output end of the thirteenth inverter is respectively connected with an input end of the sixteenth inverter, a third input end of the eleventh AND gate, a third input end of the twelfth AND gate, a third input end of the thirteenth AND gate and a third input end of the fourteenth AND gate, an output end of the fourteenth inverter is respectively connected with a first input end of the twelfth AND gate, a first input end of the fourteenth AND gate, a first input end of the sixteenth AND gate and a first input end of the eighteenth AND gate, the output end of the fifteenth inverter is respectively connected with the second input end of the thirteenth AND gate, the second input end of the fourteenth AND gate, the second input end of the seventeenth AND gate and the second input end of the eighteenth AND gate, the output end of the sixteenth inverter is respectively connected with the third input end of the fifteenth AND gate, the third input end of the sixteenth AND gate, the third input end of the seventeenth AND gate and the third input end of the eighteenth AND gate, the grid of the second MOS tube is connected with the output end of the eleventh AND gate, the grid of the third MOS tube is connected with the output end of the twelfth AND gate, the grid of the fourth MOS tube is connected with the output end of the thirteenth AND gate, the grid of the fifth MOS tube is connected with the output end of the fourteenth AND gate, and the grid of the sixth MOS tube is connected with the output end of the fifteenth AND gate, the grid electrode of the seventh MOS tube is connected with the output end of the sixteenth AND gate, the grid electrode of the eighth MOS tube is connected with the output end of the seventeenth AND gate, and the grid electrode of the ninth MOS tube is connected with the output end of the eighteenth AND gate.
Compared with the prior art, the invention has the advantages that a lightweight PUF circuit is constructed by the control module, the PUF array and the output module, the PUF array is formed by arranging 64 PUF units according to 8 rows and 8 columns, each PUF unit respectively comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first metal wire, a second metal wire, a third metal wire, a first NAND gate, a second NAND gate and a first MOS transistor, the first MOS transistor is an NMOS transistor, the first NAND gate and the second NAND gate respectively have a first input end, a second input end and an output end, the input end of the first inverter is connected with the input end of the third inverter, the connection end of the first inverter, the output end of the first inverter and the input end of the second inverter are connected, the output end of the third inverter is connected with the input end of the fourth inverter, the output end of the second inverter is connected with one end of the first metal wire, the other end of the first metal wire is connected with the first input end of the first NAND gate, the output end of the fourth inverter is connected with one end of the second metal wire, the other end of the second metal wire is connected with the second input end of the second NAND gate, the second input end of the first NAND gate is connected with the output end of the second NAND gate, the output end of the first NAND gate, the first input end of the second NAND gate and the drain electrode of the first MOS transistor are connected, the gate of the first MOS transistor is the second input end of the PUF unit, the source of the first MOS transistor is the output end of the PUF unit, the third metal wire is positioned between the first metal wire and the second metal wire, the third metal wire is respectively parallel to the first metal wire and the second metal wire, the first metal wire can be coupled with the third metal wire to generate a coupling capacitor, the second metal wire can be coupled with the third metal wire to generate a coupling capacitor, and the first metal wire and the second metal wire are used as victim wires, the third metal wire is used as an attack wire, when a signal is accessed to the first input end of the PUF unit, the third metal wire is respectively coupled with the first metal wire and the second metal wire to generate a coupling capacitor to interfere the PUF unit, so that the PUF unit outputs a corresponding signal, the PUF unit is realized by adopting a simple circuit structure, the structure of the PUF array is simplified, the whole occupied area is small, in each PUF unit, the first metal wire and the second metal wire are used as victim wires, the third metal wire is used as an attack wire, the coupling capacitor and mutual inductance generated by coupling between the first metal wire and the third metal wire and the coupling capacitor and mutual inductance generated by coupling between the second metal wire and the third metal wire are avoided, and process deviation cannot be avoided by the first metal wire, the second metal wire and the third metal wire in different PUF units due to process uncertainty of the metal wires in the manufacturing process, therefore, the sizes of the coupling capacitance and the mutual inductance generated between the first metal wire and the third metal wire in different PUF units and the sizes of the coupling capacitance and the mutual inductance generated between the second metal wire and the third metal wire are respectively different, the delays of signals in different PUF units are correspondingly different, when the control module selects the corresponding PUF unit, the PUF unit receives the signals and randomly outputs a result under the interference of internal interconnection wires, due to process deviation, the internal structure of each PUF unit is not completely the same, when the same signals are input, the output result of each PUF unit is different, when the same PUF unit is changed in the face of environment, the same group of signals are responded, the output results are approximately the same, the output results of different PUF units are different, different PUF units output different signals to the output module, and the output module outputs corresponding random response signals, the output logic is not easy to make mistakes, the reliability is high, the information safety of users is guaranteed, the circuit structure is simple, and the occupied area is small.
Drawings
FIG. 1 is a block diagram of a circuit configuration of a lightweight PUF circuit employing interconnect wiring bias according to the present invention;
FIG. 2 is a circuit diagram of a PUF cell of the present invention employing interconnect wiring bias for a lightweight PUF circuit;
FIG. 3 is a circuit diagram of a control module of the light weight PUF circuit of the present invention employing interconnect wiring bias;
FIG. 4 is a circuit diagram of an output module of the light weight PUF circuit of the present invention employing interconnect bias;
fig. 5 is an equivalent circuit diagram of a first metal line, a second metal line, and a third metal line in a PUF cell of a lightweight PUF circuit employing interconnection line bias according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example (b): as shown in fig. 1 and fig. 2, a lightweight PUF circuit with interconnect line skew includes a control module, a PUF array, and an output module, where the control module has a first control terminal, a second control terminal, a third control terminal, a first clock terminal, a second clock terminal, a third clock terminal, and 8 output terminals, the first control terminal of the control module is configured to access a first control signal S1, the second control terminal of the control module is configured to access a second control signal S2, the third control terminal of the control module is configured to access a third control signal S3, the first control terminal, the second control terminal, and the third control terminal of the control module are all active at high level, the first clock terminal of the control module is configured to access a first clock signal CLK1, the second clock terminal of the control module is configured to access a second clock signal CLK2, the third clock terminal of the control module is configured to access a third clock signal CLK3, a frequency of the first clock signal CLK1 is twice a frequency of the second clock signal CLK2, the frequency of the second clock signal CLK2 is twice the frequency of the third clock signal CLK 3; the output module is provided with 8 input ends, 8 output ends, a first control end and a second control end, the first control end of the output module is used for accessing a fourth control signal S4, the second control end of the output module is used for accessing a fifth control signal S5, the third control end of the output module is used for accessing a sixth control signal S6, the first control end, the second control end and the third control end of the output module are all high-level active, the first clock end of the output module is used for accessing a fourth clock signal CLK4, the second clock end of the output module is used for accessing a fifth clock signal CLK5, the third clock end of the output module is used for accessing a sixth clock signal CLK6, the frequency of the fourth clock signal CLK4 is twice the frequency of the fifth clock signal CLK5, and the frequency of the fifth clock signal CLK5 is twice the frequency of the sixth clock signal CLK 6; the PUF array is formed by arranging 64 PUF units according to 8 rows and 8 columns, each PUF unit is respectively provided with a first input end, a second input end and an output end, the first input ends and the second input ends of the 8 PUF units positioned on the same row are all connected, the connection end of each PUF unit is used as one input end of the PUF array, the output ends of the 8 PUF units positioned on the same column are all connected, the connection end of each PUF unit is used as one output end of the PUF array, the PUF array is provided with 8 input ends and 8 output ends, the 8 input ends of the PUF array are connected with the 8 output ends of the control module in a one-to-one correspondence manner, the 8 output ends of the PUF array are connected with the 8 input ends of the output module in a one-to-correspondence manner, and the 8 output ends of the output module are used for outputting 8-bit response signals OUT 1-OUT 8; each PUF cell includes a first inverter T1, a second inverter T2, a third inverter T3, a fourth inverter T4, a first metal line LN1, a second metal line LN2, a third metal line LN3, a first nand B1, a second nand B2, and a first MOS M1, the first MOS M1 is an NMOS transistor, the first nand B1 and the second nand B2 respectively have a first input terminal, a second input terminal, and an output terminal, an input terminal of the first inverter T1 is connected to an input terminal of the third inverter T3, and its connection terminals are the first input terminal of the PUF cell, the output terminal of the first inverter T1 and the input terminal of the second inverter T2, an output terminal of the third inverter T3 is connected to an input terminal of the fourth inverter T4, an output terminal of the second inverter T2 is connected to one end of the first metal line LN1, the other end of the first metal line 1 is connected to the first input terminal of the first inverter B1, and the output terminal 2 of the fourth inverter T4, the other end of the second metal line LN2 is connected to the second input terminal of the second nand gate B2, the second input terminal of the first nand gate B1 is connected to the output terminal of the second nand gate B2, the output terminal of the first nand gate B1, the first input terminal of the second nand gate B2 and the drain of the first MOS transistor M1 are connected, the gate of the first MOS transistor M1 is the second input terminal of the PUF cell, the source of the first MOS transistor M1 is the output terminal of the PUF cell, the third metal line LN3 is located between the first metal line LN1 and the second metal line LN2, the third metal line LN3 is parallel to the first metal line LN1 and the second metal line LN2, the first metal line LN 42 can be coupled to the third metal line LN3 to generate a coupling capacitance, the second metal line LN2 can be coupled to the third metal line LN3 to generate a coupling capacitance, the first metal line LN 5 and the second metal line LN2 serve as a victim line 5857324, when a signal is accessed to the first input end of the PUF cell, the third metal line LN3 is coupled to the first metal line LN1 and the second metal line LN2, respectively, to generate coupling capacitance, and interferes with the PUF cell, so that the output of the PUF cell outputs a corresponding signal.
As shown in fig. 3, in the present embodiment, the control module includes a fifth inverter T5, a sixth inverter T6, a seventh inverter T7, an eighth inverter T8, a ninth inverter T9, a tenth inverter T10, a first and gate a1, a second and gate a2, a third and gate A3, a fourth and gate a4, a fifth and gate A5, a sixth and gate A6, a seventh and gate a7, an eighth and gate A8, and a ninth and gate a9, the first and gate a1 is a three-input and gate having a first input terminal, a second input terminal, a third input terminal, and an output terminal, the second and gate a2, the third and gate A3, the fourth and gate a4, the fifth and gate A5, the sixth and gate A6, the seventh and gate a7, the eighth and gate A8, and the ninth and gate a9 are four input terminals, each having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and terminal 1, the second input end of the first and gate a1 is the second control end of the control module, the third input end of the first and gate a1 is the third control end of the control module, the input end of the fifth inverter T5 is the first clock end of the control module, the input end of the sixth inverter T6 is the second clock end of the control module, the input end of the seventh inverter T7 is the third clock end of the control module, the output end of the fifth inverter T5 is respectively connected with the first input end of the second and gate a2, the first input end of the fourth and gate a4, the input end of the eighth inverter T8, the first input end of the sixth and gate a6 and the first input end of the eighth and gate A8, the output end of the sixth inverter T6 is respectively connected with the second input end of the second and gate a2, the second input end of the third and gate A3, the input end of the ninth inverter T9, the second input end of the sixth and gate a6 and the second input end of the seventh and gate a7, the output terminal of the seventh inverter T7 is connected to the third input terminal of the second and gate a2, the third input terminal of the third and gate A3, the input terminal of the tenth inverter T10, the third input terminal of the fourth and gate A4 and the third input terminal of the fifth and gate A5, the output terminal of the eighth inverter T8 is connected to the first input terminal of the third and gate A3, the first input terminal of the fifth and gate A5, the first input terminal of the seventh and gate a7 and the first input terminal of the ninth and gate a9, the output terminal of the ninth inverter T9 is connected to the second input terminal of the fourth and gate A4, the second input terminal of the fifth and gate A5, the second input terminal of the eighth and gate A8 and the second input terminal of the ninth and gate a9, the output terminal of the tenth inverter T10 is connected to the third input terminal of the sixth and gate A6, the third input terminal of the seventh and gate a7, the third input terminal of the eighth and gate A8 and gate a9, the output terminals of the first and gate a1 are respectively connected to the fourth input terminal of the second and gate a2, the fourth input terminal of the third and gate A3, the fourth input terminal of the fourth and gate a4, the fourth input terminal of the fifth and gate A5, the fourth input terminal of the sixth and gate A6, the fourth input terminal of the seventh and gate a7, the fourth input terminal of the eighth and gate A8, and the fourth input terminal of the ninth and gate a9, and the output terminals of the second and gate a2, the third and gate A3, the fourth and gate a4, the fifth and gate A5, the sixth and gate A6, the seventh and gate a7, the eighth and gate A8, and the ninth and gate a9 serve as 8 output terminals of the control module, wherein the output terminal of the second and gate a2 serves as the first output terminal of the control module, the output terminal of the third and gate A3 serves as the second output terminal of the control module, and so on, and the output terminal of the ninth and gate a9 serves as the second output terminal of the control module.
As shown in fig. 4, in the present embodiment, the output module includes an eleventh inverter T11, a twelfth inverter T12, a thirteenth inverter T13, a fourteenth inverter T14, a fifteenth inverter T14, a sixteenth inverter T14, a tenth and gate a14, an eleventh and gate a14, a twelfth and gate a14, a thirteenth and gate a14, a fourteenth and gate a14, a fifteenth and gate a14, a sixteenth and gate a14, a seventeenth and gate a14, an eighteenth and gate a14, a second MOS transistor M14, a third MOS transistor M14, a fourth MOS transistor M14, a fifth MOS transistor M14, a sixth MOS transistor M14, a seventh MOS transistor M14, an eighth MOS transistor M14, a ninth MOS transistor M14, a second MOS transistor M14, a third MOS transistor M14, a fourth MOS transistor M14, a fifth MOS transistor M14, a sixth MOS transistor M14, a seventh MOS transistor M14, a ninth and a ninth input terminal of the eleventh and tenth input terminal of the tenth and tenth input terminal of the eleventh and tenth input terminal of the second MOS transistor M14, the eleventh and gate a11, the twelfth and gate a12, the thirteenth and gate a13, the fourteenth and gate a14, the fifteenth and gate a15, the sixteenth and gate a16, the seventeenth and gate a17 and the eighteenth and gate a18 are four-input and gates, and respectively have a first input end, a second input end, a third input end, a fourth input end and an output end; the drain of the second MOS transistor M2, the drain of the third MOS transistor M3, the drain of the fourth MOS transistor M4, the drain of the fifth MOS transistor M5, the drain of the sixth MOS transistor M6, the drain of the seventh MOS transistor M7, the drain of the eighth MOS transistor M8, and the drain of the ninth MOS transistor M9 are used as 8 input terminals of the output module, the source of the second MOS transistor M2, the source of the third MOS transistor M3, the source of the fourth MOS transistor M4, the source of the fifth MOS transistor M5, the source of the sixth MOS transistor M6, the source of the seventh MOS transistor M7, the source of the eighth MOS transistor M8, and the source of the ninth MOS transistor M9 are used as 8 output terminals of the output module, wherein the source of the second MOS transistor M2 is used as the 1 st output terminal of the output module, the source of the third MOS transistor M3 is used as the 2 nd output terminal of the output module, and so on, the source of the ninth MOS transistor M9 is used as the tenth output terminal of the tenth output module 9, and the tenth output terminal of the tenth output module is used as the tenth output terminal of the tenth output module 10 a, a second input terminal of the tenth and gate a10 is a second control terminal of the output module, a third input terminal of the tenth and gate a10 is a third control terminal of the output module, an input terminal of the eleventh inverter T11 is a first clock terminal of the output module, an input terminal of the twelfth inverter T12 is a second clock terminal of the output module, an input terminal of the thirteenth inverter T13 is a third clock terminal of the output module, an output terminal of the tenth and gate a10 is respectively connected to a fourth input terminal of the eleventh and gate a11, a fourth input terminal of the twelfth and gate a12, a fourth input terminal of the thirteenth and gate a13, a fourth input terminal of the fourteenth and gate a14, a fourth input terminal of the fifteenth and gate a15, a fourth input terminal of the sixteenth and gate a16, a fourth input terminal of the seventeenth and gate a17 and a18, an output terminal of the eleventh inverter T11 is respectively connected to an input terminal of the fourteenth inverter T14, a third control terminal of the output module, a control terminal of the thirteenth and gate a10, a, A first input terminal of an eleventh and gate a11, a first input terminal of a thirteenth and gate a13, a first input terminal of a fifteenth and gate a15 and a first input terminal of a seventeenth and gate a17, output terminals of a twelfth inverter T12 are connected to an input terminal of a fifteenth inverter T15, a second input terminal of an eleventh and gate a11, a second input terminal of a twelfth and gate a12, a second input terminal of a fifteenth and gate a15 and a second input terminal of a sixteenth and gate a16, output terminals of a thirteenth inverter T13 are connected to an input terminal of a sixteenth inverter T16, a third input terminal of an eleventh and gate a11, a third input terminal of a twelfth and gate a12, a third input terminal of a thirteenth and gate a13 and a fourteenth and a14, output terminals of a fourteenth inverter T14 are connected to a first input terminal of a twelfth and gate a12, a first input terminal of a fourteenth and gate a14, a sixteenth and gate a16 and a eighteenth input terminal of an eighteenth and gate 18, the output end of a fifteenth inverter T15 is connected with the second input end of the thirteenth and gate a13, the second input end of the fourteenth and gate a14, the second input end of the seventeenth and gate a17 and the second input end of the eighteenth and gate a18, the output end of a sixteenth inverter T16 is connected with the third input end of the fifteenth and gate a15, the third input end of the sixteenth and gate a16, the third input end of the seventeenth and gate a17 and the third input end of the eighteenth and gate a18, the gate of the second MOS transistor M2 is connected with the output end of the eleventh and gate a11, the gate of the third MOS transistor M3 is connected with the output end of the twelfth and gate a12, the gate of the fourth MOS transistor M4 is connected with the output end of the thirteenth and gate a13, the gate of the fifth MOS transistor M5 is connected with the output end of the fourteenth and gate a14, the gate of the sixth MOS transistor M6 is connected with the output end of the fifteenth A5, the gate of the seventh and the sixteenth and gate 16 of the gate a 5857324, the gate of the eighth MOS transistor M8 is connected to the output terminal of the seventeenth and gate a17, and the gate of the ninth MOS transistor M9 is connected to the output terminal of the eighteenth and gate a 18.
Fig. 5 shows an equivalent circuit diagram of the first metal line, the second metal line, and the third metal line in the PUF cell of the lightweight PUF circuit according to the present invention using interconnection line deviation. In fig. 5, L1 denotes an equivalent inductance of the first metal line LN1, L2 denotes an equivalent inductance of the second metal line LN2, L3 denotes an equivalent inductance of the third metal line LN3, C1 denotes an equivalent capacitance of the first metal line LN1, C2 denotes an equivalent capacitance of the second metal line LN2, C3 denotes an equivalent capacitance of the third metal line LN3, R1 denotes an equivalent resistance of the first metal line LN1, R2 denotes an equivalent resistance of the second metal line LN2, R3 denotes an equivalent resistance of the third metal line LN3, and C2 denotes an equivalent resistance of the second metal line LN213Represents the coupling capacitance, L, generated by the coupling of the third metal line LN3 and the first metal line LN113The mutual inductance, C, generated by the coupling of the third metal wire LN3 and the first metal wire LN1 is shown23Represents the coupling capacitance, L, generated by the coupling of the third metal line LN3 and the second metal line LN223The mutual inductance generated by the coupling of the third metal wire LN3 and the second metal wire LN2 is shown. In each PUF cell, the first and second metal lines LN1 and LN2 are victim lines, and the third metal line LN3 is attack line. Because of the uncertainty of the process of the metal wire in the manufacturing processThe first metal line LN1, the second metal line LN2 and the third metal line LN3 in different PUF cells inevitably have process variations, and thus C in different PUF cells13、C23、L13And L23Are different, and the delays of the signals in different PUF cells are correspondingly different, so that different PUF cells output different signals to the output module, so that the output module outputs different output response signals.
The working principle of the lightweight PUF circuit using interconnection line deviation in this embodiment is as follows: the control module normally operates only when the first control signal S1, the second control signal S2, and the third control signal S3 are all at a high level, the output module normally operates only when the fourth control signal S4, the fifth control signal S5, and the sixth control signal S6 are all at a high level, and if one of the first control signal S1, the second control signal S2, and the third control signal S3 is at a low level, all 8 output terminals of the control module are at a low level. If one of the fourth control signal S4, the fifth control signal S5 and the sixth control signal S6 is low, the 8 output terminals of the output block are all low, i.e., OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7 and OUT8 are all low. If the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are at high level, low level, and low level, respectively, the control module outputs high level at the second output terminal, and outputs low level at the other seven output terminals. Meanwhile, if the fourth clock signal CLK4, the fifth clock signal CLK5 and the sixth clock signal CLK6 are all at high level, the output module selects the ninth MOS transistor M9 to be turned on, so that the logic signal of the eighth PUF cell of the row of PUF cells connected to the second output terminal of the control module is output to the 8 th port of the output module, so that OUT8 is at high level, and the rest of OUT1, OUT2, OUT3, OUT4, OUT5, OUT6 and OUT7 are all at low level. If the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are at a high level, a low level, and a low level respectively, the levels of the fourth clock signal CLK4, the fifth clock signal CLK5, and the sixth clock signal CLK6 are at a high level, a low level, and a high level, the output module selects the seventh MOS transistor M7 to be turned on, so that the logic signals of the sixth PUF cell of the row of PIF cells connected to the second output terminal of the control module are output to the sixth output terminal of the output module, that is, the OUT6 is at a high level, and the rest of the OUT1, OUT2, OUT3, OUT4, OUT5, OUT7, and OUT8 are at a low level. If the fourth clock signal CLK4, the fifth clock signal CLK5, and the sixth clock signal CLK6 are at a high level, and a high level, respectively, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are at a low level, a high level, and a low level, the control module outputs the high level at the third output terminal, and outputs the low levels at the other seven output terminals. The output module selects the ninth MOS transistor M9 to be turned on, so that the logic signal of the eighth PUF cell of the row of PUF cells connected to the third output terminal of the control module is output to the eighth output terminal thereof, that is, OUT8 is at a high level, and the rest of OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, and OUT7 are all at a low level. And so on for other cases. The control module of the present invention enables the output of the corresponding output terminal of the control module to be at the high level and the other output terminals to be at the low level according to the high and low levels of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK 3. The output module selects the corresponding MOS transistor to be opened according to the high and low levels of the fourth clock signal CLK4, the fifth clock signal CLK5 and the sixth clock signal CLK6, and outputs the logic signal of the selected PUF unit.
The light-weight PUF circuit adopting the interconnection line deviation performs on-chip difference experiment tests. The external environment of the power supply voltage is considered in the experiment, and the experiment is carried out under the conditions that the power supply voltage is 1.08V, 1.2V and 1.32V. H1 represents experimental tests performed at a voltage of 1.08V, and using the method of monte carlo simulation, experimental tests were performed 100 times for the variation of the width of the interconnection line (the first metal line LN1, the second metal line LN2, and the third metal line LN3) within a deviation range of ten percent, H2 represents experimental tests performed at a voltage of 1.2V, using the method of monte carlo simulation, experimental tests were performed 100 times for the variation of the width of the interconnection line (the first metal line LN1, the second metal line LN2, and the third metal line LN3) within a deviation range of ten percent, H3 represents experimental tests performed at a voltage of 1.32V, and using the method of monte carlo simulation, 100 times for the variation of the width of the interconnection line (the first metal line LN1, the second metal line LN2, and the third metal line LN3) within a deviation range of ten percent were performed. When the widths of the interconnection lines (the first metal line LN1, the second metal line LN2, and the third metal line LN3) are the same and the voltages are different, H1 and H2 are compared with each other with logic signals, and the probability of finding the same is 90%. When the widths of the interconnection lines (the first metal line LN1, the second metal line LN2, and the third metal line LN3) are the same and the voltages are different, H1 and H3 are compared with each other with logic signals, and the probability of finding the same is 93%. When the widths of the interconnection lines (the first metal line LN1, the second metal line LN2, and the third metal line LN3) are the same and the voltages are different, H2 and H3 are compared with each other with logic signals, and the probability of finding the same is 97%. As can be seen from the data, the reliability of the PUF circuits under different supply voltage conditions is approximately the same, 90%, 93%, and 97%, the average reliability is 93.6%, and the ideal reliability is 100%, with little variation. Therefore, the light-weight PUF circuit adopting the interconnection line deviation has strong anti-interference performance and good reliability.

Claims (3)

1. A lightweight PUF circuit adopting interconnection line deviation is characterized by comprising a control module, a PUF array and an output module, wherein the control module is provided with a first control end, a second control end, a third control end, a first clock end, a second clock end, a third clock end and 8 output ends, the first control end of the control module is used for accessing a first control signal, the second control end of the control module is used for accessing a second control signal, the third control end of the control module is used for accessing a third control signal, the first control end, the second control end and the third control end of the control module are all high-level effective, the first clock end of the control module is used for accessing a first clock signal, the second clock end of the control module is used for accessing a second clock signal, and the third clock end of the control module is used for accessing a third clock signal, the frequency of the first clock signal is twice the frequency of the second clock signal, and the frequency of the second clock signal is twice the frequency of the third clock signal; the output module is provided with 8 input ends, 8 output ends, a first control end, a second control end, a third control end, a first clock end, a second clock end and a third clock end, wherein the first control end of the output module is used for accessing a fourth control signal, the second control end of the output module is used for accessing a fifth control signal, the third control end of the output module is used for accessing a sixth control signal, the first control end, the second control end and the third control end of the output module are all effective at high level, the first clock end of the output module is used for accessing a fourth clock signal, the second clock end of the output module is used for accessing a fifth clock signal, the third clock end of the output module is used for accessing a sixth clock signal, and the frequency of the fourth clock signal is twice the frequency of the fifth clock signal, the frequency of the fifth clock signal is twice the frequency of the sixth clock signal; the PUF array is formed by arranging 64 PUF units according to 8 rows and 8 columns, each PUF unit is respectively provided with a first input end, a second input end and an output end, the first input ends and the second input ends of the 8 PUF units positioned on the same row are all connected, the connection ends of the first input ends and the second input ends are used as one input end of the PUF array, the output ends of the 8 PUF units positioned on the same column are all connected, the connection ends of the 8 PUF units are used as one output end of the PUF array, the PUF array is provided with 8 input ends and 8 output ends, the 8 input ends of the PUF array are connected with the 8 output ends of the control module in a one-to-one correspondence mode, the 8 output ends of the PUF array are used for outputting 8-bit response signals; each PUF unit comprises a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a first metal wire, a second metal wire, a third metal wire, a first NAND gate, a second NAND gate and a first MOS (metal oxide semiconductor) tube respectively, wherein the first MOS tube is an NMOS tube, the first NAND gate and the second NAND gate are respectively provided with a first input end, a second input end and an output end, the input end of the first phase inverter is connected with the input end of the third phase inverter, the connecting end of the first phase inverter is the first input end of the PUF unit, the output end of the first phase inverter is connected with the input end of the second phase inverter, the output end of the third phase inverter is connected with the input end of the fourth phase inverter, the output end of the second phase inverter is connected with one end of the first metal wire, and the other end of the first metal wire is connected with the first input end of the first NAND gate, the output end of the fourth inverter is connected with one end of the second metal wire, the other end of the second metal wire is connected with the second input end of the second nand gate, the second input end of the first nand gate is connected with the output end of the second nand gate, the output end of the first nand gate, the first input end of the second nand gate and the drain electrode of the first MOS transistor are connected, the gate of the first MOS transistor is the second input end of the PUF unit, the source of the first MOS transistor is the output end of the PUF unit, the third metal wire is located between the first metal wire and the second metal wire, the third metal wire is respectively parallel to the first metal wire and the second metal wire, and the first metal wire can be coupled with the third metal wire to generate a coupling capacitor, the second metal wire can be coupled with the third metal wire to generate a coupling capacitor, the first metal wire and the second metal wire are used as victim wires, the third metal wire is used as an attack wire, when a signal is accessed to the first input end of the PUF unit, the third metal wire is respectively coupled with the first metal wire and the second metal wire to generate a coupling capacitor, the third metal wire interferes with the PUF unit, and the corresponding signal is output by the PUF unit.
2. The light-weight PUF circuit adopting the interconnection wire deviation as claimed in claim 1, wherein said control module comprises a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate and a ninth AND gate, said first AND gate is a three-input AND gate having a first input terminal, a second input terminal, a third input terminal and an output terminal, said second AND gate, said third AND gate, said fourth AND gate, said fifth AND gate, said sixth AND gate, said seventh AND gate, said eighth AND gate and said ninth AND gate are four-input AND gates having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal and an output terminal respectively, the first input end of the first and gate is the first control end of the control module, the second input end of the first and gate is the second control end of the control module, the third input end of the first and gate is the third control end of the control module, the input end of the fifth inverter is the first clock end of the control module, the input end of the sixth inverter is the second clock end of the control module, the input end of the seventh inverter is the third clock end of the control module, the output end of the fifth inverter is respectively connected with the first input end of the second and gate, the first input end of the fourth and gate, the input end of the eighth inverter, the first input end of the sixth and gate and the first input end of the eighth and gate, and the output end of the sixth inverter is respectively connected with the second input end of the second and gate, the third input end of the third and gate, the third input end of the fourth and gate, the fourth and gate, The second input end of the third and gate, the input end of the ninth inverter, the second input end of the sixth and gate and the second input end of the seventh and gate are connected, the output end of the seventh inverter is respectively connected with the third input end of the second and gate, the third input end of the third and gate, the input end of the tenth inverter, the third input end of the fourth and gate and the third input end of the fifth and gate, the output end of the eighth inverter is respectively connected with the first input end of the third and gate, the first input end of the fifth and gate, the first input end of the seventh and gate and the first input end of the ninth and gate, the output end of the ninth inverter is respectively connected with the second input end of the fourth and gate, the second input end of the fifth and gate, the second input end of the sixth and gate and the second input end of the seventh and gate, the output end of the seventh inverter is connected with the first input end of the fourth and gate, the second input end of the fifth and gate, the sixth and gate, the fourth and gate, the fifth and gate, the fourth and gate, The second input end of the eighth and gate is connected with the second input end of the ninth and gate, the output end of the tenth inverter is respectively connected with the third input end of the sixth and gate, the third input end of the seventh and gate, the third input end of the eighth and gate and the third input end of the ninth and gate, the output end of the first and gate is respectively connected with the fourth input end of the second and gate, the fourth input end of the third and gate, the fourth input end of the fourth and gate, the fourth input end of the fifth and gate, the fourth input end of the sixth and gate, the fourth input end of the seventh and gate, the fourth input end of the eighth and gate and the fourth input end of the ninth and gate, the second and gate, the third and gate, the fourth and gate, the fifth and gate of the ninth and gate, the tenth inverter, the output end of the tenth inverter is respectively connected with the third input end of the sixth and gate, the third input end of the seventh and gate, the fourth input end of the eighth and gate, the fourth input end of the ninth and gate, the fifth and gate, And the output ends of the sixth AND gate, the seventh AND gate, the eighth AND gate and the ninth AND gate are used as 8 output ends of the control module.
3. A lightweight PUF circuit with interconnection line bias according to claim 1, wherein the output module includes an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a fifteenth inverter, a sixteenth inverter, a tenth and gate, an eleventh and gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a sixteenth and gate, a seventeenth and gate, an eighteenth and gate, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are NMOS transistors, the tenth and gate is a three-input and gate, the power supply circuit is provided with a first input end, a second input end, a third input end and an output end, wherein the eleventh AND gate, the twelfth AND gate, the thirteenth AND gate, the fourteenth AND gate, the fifteenth AND gate, the sixteenth AND gate, the seventeenth AND gate and the eighteenth AND gate are four-input AND gates and are respectively provided with a first input end, a second input end, a third input end, a fourth input end and an output end; the drain of the second MOS transistor, the drain of the third MOS transistor, the drain of the fourth MOS transistor, the drain of the fifth MOS transistor, the drain of the sixth MOS transistor, the drain of the seventh MOS transistor, the drain of the eighth MOS transistor, and the drain of the ninth MOS transistor are 8 input terminals of the output module, the source of the second MOS transistor, the source of the third MOS transistor, the source of the fourth MOS transistor, the source of the fifth MOS transistor, the source of the sixth MOS transistor, the source of the seventh MOS transistor, the source of the eighth MOS transistor, and the source of the ninth MOS transistor are 8 output terminals of the output module, the first input terminal of the tenth and gate is the first control terminal of the output module, and the second input terminal of the tenth and gate is the second control terminal of the output module, a third input end of the tenth and-gate is a third control end of the output module, an input end of the eleventh inverter is a first clock end of the output module, an input end of the twelfth inverter is a second clock end of the output module, an input end of the thirteenth inverter is a third clock end of the output module, an output end of the tenth and-gate is respectively connected with a fourth input end of the eleventh and-gate, a fourth input end of the twelfth and-gate, a fourth input end of the thirteenth and-gate, a fourth input end of the fourteenth and-gate, a fourth input end of the fifteenth and-gate, a fourth input end of the sixteenth and-gate, a fourth input end of the seventeenth and-gate and a fourth input end of the eighteenth and-gate, and an output end of the eleventh inverter is respectively connected with an input end of the fourteenth inverter, A first input end of an eleventh AND gate, a first input end of a thirteenth AND gate, a first input end of a fifteenth AND gate and a first input end of a seventeenth AND gate, an output end of the twelfth inverter is respectively connected with an input end of the fifteenth inverter, a second input end of the eleventh AND gate, a second input end of the twelfth AND gate, a second input end of the fifteenth AND gate and a second input end of the sixteenth AND gate, an output end of the thirteenth inverter is respectively connected with an input end of the sixteenth inverter, a third input end of the eleventh AND gate, a third input end of the twelfth AND gate, a third input end of the thirteenth AND gate and a third input end of the fourteenth AND gate, an output end of the fourteenth inverter is respectively connected with a first input end of the twelfth AND gate, a first input end of the fourteenth AND gate, a first input end of the sixteenth AND gate and a first input end of the eighteenth AND gate, the output end of the fifteenth inverter is respectively connected with the second input end of the thirteenth AND gate, the second input end of the fourteenth AND gate, the second input end of the seventeenth AND gate and the second input end of the eighteenth AND gate, the output end of the sixteenth inverter is respectively connected with the third input end of the fifteenth AND gate, the third input end of the sixteenth AND gate, the third input end of the seventeenth AND gate and the third input end of the eighteenth AND gate, the grid of the second MOS tube is connected with the output end of the eleventh AND gate, the grid of the third MOS tube is connected with the output end of the twelfth AND gate, the grid of the fourth MOS tube is connected with the output end of the thirteenth AND gate, the grid of the fifth MOS tube is connected with the output end of the fourteenth AND gate, and the grid of the sixth MOS tube is connected with the output end of the fifteenth AND gate, the grid electrode of the seventh MOS tube is connected with the output end of the sixteenth AND gate, the grid electrode of the eighth MOS tube is connected with the output end of the seventeenth AND gate, and the grid electrode of the ninth MOS tube is connected with the output end of the eighteenth AND gate.
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