CN113067322A - ESD power supply clamping protection circuit with double-trigger structure - Google Patents

ESD power supply clamping protection circuit with double-trigger structure Download PDF

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Publication number
CN113067322A
CN113067322A CN202110345844.XA CN202110345844A CN113067322A CN 113067322 A CN113067322 A CN 113067322A CN 202110345844 A CN202110345844 A CN 202110345844A CN 113067322 A CN113067322 A CN 113067322A
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circuit
trigger
power supply
transistor
drain
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CN113067322B (en
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李振荣
陆益军
杨艳梅
乔佳
刘帅
张新雨
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

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  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses an ESD power supply clamping protection circuit with a double-trigger structure, which comprises a transient trigger circuit, a static trigger circuit, a synthesis control circuit and a discharge circuit. The transient trigger circuit identifies an ESD impact signal through an RC network. The static trigger circuit monitors a voltage signal through a diode string. The synthesis control circuit is used for controlling the opening and closing of the bleeder circuit. The ESD power supply clamping protection circuit provided by the invention can solve the problems of large leakage current and easy false triggering of the existing ESD power supply clamping protection circuit on the premise of providing reliable ESD protection performance.

Description

ESD power supply clamping protection circuit with double-trigger structure
Technical Field
The invention belongs to the technical field of microelectronics, and further relates to an electrostatic discharge (ESD) power supply clamping protection circuit with a double-trigger structure in the technical field of integrated circuits. The invention can be integrated in analog and radio frequency chips to carry out ESD protection on the chips.
Background
The ESD power supply clamping protection circuit is a key module for realizing the full-chip ESD protection of an integrated circuit, and has the function of providing a low-impedance current path when an ESD signal comes, so that an internal circuit is prevented from being impacted by large current. The traditional ESD power supply clamping protection circuit meets the function of chip ESD protection, but has the defects of larger leakage current, easy false triggering, larger occupied chip area and the like. In order to achieve a better chip ESD protection effect, the ESD power clamp protection circuit must have the characteristics of high ESD robustness, small leakage current, difficulty in false triggering and the like.
Shanghai weiji 29583, microelectronics ltd, discloses a simple power clamp protection circuit in its patent document "power clamp ESD protection circuit" (application No. 201710600942.7, application publication No. CN 109286181A, published 2019.01.29). The circuit comprises a trigger module and a bleeding module: the discharge module comprises a discharge transistor and is used for discharging large current generated during ESD impact; the trigger module comprises a trigger unit, and the trigger unit is connected with the grid electrode of the bleeder transistor and used for controlling the conduction or the cut-off of the bleeder transistor. The circuit has lower cost, improves the traditional power supply clamping circuit, can generate a stronger charge release path in negative static discharge, and plays a perfect ESD protection function. However, the circuit still has the disadvantage that the size of the bleeder transistor used in the circuit is larger in order to bleed off the larger ES D current, which results in larger static leakage current of the circuit, thereby increasing the power consumption of the overall circuit.
A low leakage type power clamp ESD protection circuit is disclosed in the patent technology "a low leakage type power clamp ESD protection circuit" owned by beijing university (application No. 201410461419.7, publication No. CN 104242286B, publication No. 2017.06.16). The circuit comprises a transient trigger module, a direct current voltage detection module and a bleeder transistor. When the chip normally works, the resistance from the direct-current voltage detection module to the ground is large, and after the bleeder transistor is triggered, the resistance from the direct-current voltage detection module to the ground is reduced, so that the leakage of the protection circuit in the normal working process of the chip is small, and meanwhile, reliable ESD protection performance can be provided. However, the circuit has the disadvantage that due to the existence of the transient trigger module, when the circuit is exposed to rapid power-on or power supply noise, the circuit can be triggered by mistake, so that the protected circuit does not work normally.
Disclosure of Invention
The invention aims to provide an ESD power clamp protection circuit with a dual-trigger structure, which can solve the problems of large leakage current and easy false triggering of the existing ESD power clamp protection circuit on the premise of providing reliable ESD protection performance.
The idea for realizing the purpose of the invention is as follows: on the basis of the transient trigger circuit in the prior art, the static trigger circuit is added to realize the detection of the overvoltage signal, and the trigger condition of the circuit is strict, so that the circuit is not easy to trigger by mistake. Meanwhile, the static trigger circuit and the synthesis control circuit are added, so that the conduction time of the bleeder transistor is prolonged, and the size of the bleeder transistor can be reduced to reduce the leakage current of the circuit.
In order to achieve the above object, the ESD power clamp protection circuit of the present invention comprises a transient trigger circuit, a bleeder circuit, a static trigger circuit and a synthesis control circuit; the output end of the transient trigger circuit is connected with a first input end S1 of the synthesis control circuit, the output end of the static trigger circuit is connected with a second input end S2 of the synthesis control circuit, the feedback end S3 of the synthesis control circuit is connected with the input end of the static trigger circuit, and the output end S4 of the synthesis control circuit is connected with the input end of the bleeder circuit.
A first PMOS transistor P1, a second detection resistor R2, a diode string D1 and a first NMOS transistor M1 of the static trigger circuit are sequentially connected in series, the grid electrode of the first NMOS transistor M1 is the input end of the static trigger circuit, the source electrode of the first NMOS transistor M1 is connected with the ground terminal VSS, the grid electrode of the first PMOS transistor P1 is connected with the grid electrode of the second PMOS transistor P2, the source electrode of the second PMOS transistor P2 is connected with the power supply VDD, and the drain electrode of the first PMOS transistor P2 is connected with the third detection resistor R3 and the second input end S2 of the synthesis control circuit; the drain of the third PMOS transistor P3 of the synthesized control circuit is connected to the power supply VDD, the gate thereof is connected to the transient circuit output terminal V1, the source thereof is connected to the drain of the second NMOS transistor M2, the fifth detection resistor R5 and the input terminal of the static trigger circuit, the gate of the second NMOS transistor M2 is connected to the output terminal S2 of the static trigger circuit, and the source thereof is connected to the fourth detection resistor R4 and the input terminal of the bleeder circuit.
Compared with the prior art, the invention has the following advantages:
firstly, because the diode string D1 of the static trigger circuit in the circuit of the invention is turned on when the power supply voltage exceeds the trigger voltage of the diode string, the static circuit can monitor the overvoltage signal to realize the effect of static trigger, and the feedback end S3 of the synthesis control circuit can also control the trigger of the static circuit, so that the trigger condition of the whole circuit becomes strict, the bleeder transistor can be turned on only when the static trigger condition and the transient trigger condition are satisfied, and the circuit of the invention can not be turned on under the condition that the power supply is quickly powered on, thereby overcoming the problem that the ESD power supply clamp circuit in the prior art is easy to be triggered by mistake, and the circuit of the invention has the advantages of preventing false trigger and having no influence on the normal work of the chip.
Secondly, because the PMOS transistors P1 and P2 in the static trigger circuit of the invention have parasitic capacitances, and these parasitic capacitances and the detection resistor R3 form an RC network, which can increase the delay time and increase the on-time of the bleeder transistor, the size of the bleeder transistor with a smaller size can also realize ESD protection, thereby reducing the static leakage current of the circuit, overcoming the problem of large leakage current of the ESD clamp protection circuit in the prior art, and making the circuit of the invention have the advantages of low leakage current and low static power consumption.
Drawings
FIG. 1 is a circuit schematic of the present invention;
FIG. 2 is a graph of simulation results for the circuit of the present invention under normal power-up conditions;
FIG. 3 is a graph of simulation results of the circuit of the present invention under ESD shock;
FIG. 4 is a graph of simulation results for the circuit of the present invention with the power supply powered on quickly.
The specific implementation mode is as follows:
embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
The overall circuit architecture topology of the present invention is further described with reference to fig. 1.
The invention comprises a transient trigger circuit, a static trigger circuit, a synthesis control circuit and a bleeder circuit.
The output end of the transient trigger circuit is connected with a first input end S1 of the synthesis control circuit, the output end of the static trigger circuit is connected with a second input end S2 of the synthesis control circuit, the feedback end S3 of the synthesis control circuit is connected with the input end of the static trigger circuit, and the output end S4 of the synthesis control circuit is connected with the input end of the bleeder circuit.
The transient trigger circuit comprises a first detection resistor R1 and a first detection capacitor C1, one end of the first detection resistor R1 is connected with a power supply end VDD, the other end of the first detection resistor R3526 is connected with an upper electrode plate of the first detection capacitor C1 and an input end of the synthesis control circuit, and a lower electrode plate of the first detection capacitor C1 is connected with a ground end VSS.
A first PMOS transistor P1, a second detection resistor R2, a diode string D1 and a first NMOS transistor M1 of the static trigger circuit are sequentially connected in series, the grid electrode of the first NMOS transistor M1 is the input end of the static trigger circuit, the source electrode of the first NMOS transistor M1 is connected with a ground terminal VSS, the grid electrode of the first PMOS transistor P1 is connected with the grid electrode of a second PMOS transistor P2, the source electrode of the second PMOS transistor P2 is connected with a power supply VDD, and the drain electrode of the first PMOS transistor P2 is connected with a third detection resistor R3 and a second input end S2 of the synthesis control circuit.
The drain of the third PMOS transistor P3 of the synthesized control circuit is connected to the power supply VDD, the gate thereof is connected to the transient circuit output terminal V1, the source thereof is connected to the drain of the second NMOS transistor M2, the fifth detection resistor R5 and the input terminal of the static trigger circuit, the gate of the second NMOS transistor M2 is connected to the output terminal S2 of the static trigger circuit, and the source thereof is connected to the fourth detection resistor R4 and the input terminal of the bleeder circuit.
The drain circuit comprises a drain transistor Mesd, the grid electrode of the drain transistor Mesd is connected with the output end S4 of the synthesis control circuit, the drain electrode of the drain transistor Mesd is connected with a power supply VDD, the source electrode of the drain transistor Mesd is connected with a ground end VSS, and the setting range of the channel width W of the drain transistor Mesd is [1m, 2m ] m.
The working principle of the invention is as follows:
when the power supply is normally powered on, the power supply line VDD is raised from 0 to the working voltage (1.2V in the present invention for example) for a long time, since the power-on speed is slow, the transient trigger circuit does not respond, the port S1 is in a high state, when the signal at the end S1 passes through the third PMOS transistor P3, the signal is inverted and output to the input end of the static trigger circuit, since the inverted signal of the signal S1 is low, the first NMOS transistor M1 is in a closed state, the static trigger circuit does not respond at this time, and the output signal S2 is a low signal. The signal at the S2 end is output to the synthesis control circuit, so that the second NMOS transistor M2 is turned off, the synthesis control circuit is in a turned-off state, and the signal at the S3 end is at a low potential, so that the bleeder transistor Mesd is turned off, the ESD power clamp protection circuit does not operate, and the function of the internal circuit is not affected in a normal operating state.
When an ESD event occurs, the transient trigger circuit responds quickly because the charging speed is fast, S1 is in a low-voltage state, the signal at the S1 terminal is inverted and output to the input terminal of the static trigger circuit when passing through the third PMOS transistor P3, and the first NMOS transistor M1 is turned on because the inverted signal at the S1 terminal is at a high voltage, so that the static trigger circuit can operate. On the other hand, when the ESD signal is coming, the generated voltage is larger than the trigger voltage of the static trigger circuit, so the static trigger circuit is turned on, the generated current is copied by the PMOS transistors P1 and P2 and then flows through the resistor R3, and the output voltage at the S2 is high. The low signal S1 and the high signal S2 are combined in the combination control circuit to turn on both the transistors P3 and N2, so that the output S4 of the combination control circuit is at a high level. The high S4 signal causes the bleeder transistor MesdTurn on, discharge ESD events to temporary electrostatic charge。
Usually, the discharge time of the ESD event is required to be about 1 μ sec, so the conventional clamp protection circuit RC has a time constant exceeding 500ns, which requires a large layout area. In the structure of the invention, the delay time of discharge mainly comprises three parts: the delay generated by the RC network in the transient trigger circuit, the delay generated by the combining control circuit, and the delay generated by the current mirror in the static trigger circuit. The time constant of the RC network can be reduced by increasing the delay time of the two, so that the layout area is reduced.
When some special fast power-up events occur, the power line VDD will rise from 0 to the operating voltage (1.2V) in a short event. At this time, in accordance with the case when ESD occurs, since the charging speed is fast, the transient trigger circuit responds quickly, the S1 terminal is in a low-potential state, the S1 signal is inverted and outputted to the input terminal of the static trigger circuit when passing through the PMOS transistor P3, and since the inverted signal at the S1 terminal is high, the first NMOS transistor M1 is turned on, and the static trigger circuit can operate. On the other hand, the voltage of the fast power-on signal is much smaller than the trigger voltage of the static trigger voltage, so the static trigger circuit is in an off state, the output terminal S2 is at a low potential, the NMO S transistor M2 is in an off state, the synthesis control circuit is in an off state, and the output terminal S4 is at a low potential, so the bleeder transistor is off, and the ESD power clamp protection circuit does not work. The situation of false triggering can not occur.
The effect of the present invention will be further described with reference to simulation experiments.
1. Simulation experiment conditions are as follows:
the hardware platform of the simulation experiment of the invention is as follows: the processor is Intel (R) Pentium (R) CPU, the main frequency is 3GHz, and the memory is 4 GB.
The software platform of the simulation experiment of the invention is as follows: a Linux operating system and an IC 617.
The simulation of the invention is to use a Spectre RF simulation tool to simulate the circuit of the invention, and an SMIC 55nm CMOS process is adopted, the given power supply voltage VDD is 1.2V, and the working temperature is 27 ℃.
2. Simulation content and result analysis thereof:
the simulation experiments of the invention are three.
Simulation experiment 1, simulation under normal power-on condition.
A square wave pulse with the rising time of 0.1ms and the amplitude of 0-1.2V is added at the power supply voltage VDD of the circuit to simulate the normal power-on condition of a power supply, a spectrum RF simulation tool is adopted to carry out transient simulation on the circuit, the simulation time is 200ns, and simulation results of a graph 2(a) and a graph 2(b) are obtained.
Fig. 2(a) is a graph of the voltage at ports S1, S2, S4 and VDD versus time for the circuit of the present invention with the power supply normally powered up, with the abscissa in fig. 2(a) representing simulated time and the ordinate representing voltage. In fig. 2(a), a curve marked by a square represents a VDD terminal voltage, a curve marked by a diamond represents an S1 terminal voltage, a curve marked by a regular triangle represents an S2 terminal voltage, and a curve marked by an inverted triangle represents an S4 terminal voltage. As can be seen from fig. 2(a), the voltage at S1 follows the voltage at VDD to assume a high level, while the voltages at S2 and S4 remain low throughout the process. At this time, the bleeder transistor MesdIs always in the off state so as not to affect the normal operation of the internal circuit.
Fig. 2(b) is a graph of total leakage current over time for a normal power-up condition of the power supply of the present invention. The abscissa in fig. 2(b) represents the time of simulation, and the ordinate represents the leak current. As can be seen from fig. 2(b), the leakage current after the circuit is stabilized is only 49.7 nA.
The simulation results show that: the invention is closed under the normal power-on condition, the leakage current is very small, and the larger loss of the power supply power is avoided.
Simulation experiment 2, simulation under ESD shock condition.
A square wave pulse with the rise time of 10ns, the pulse width of 100ns and the amplitude of 0-5V is added to a power supply VDD of the circuit to simulate the ESD impact condition, a Spectre RF simulation tool is adopted to perform transient simulation on the circuit, the simulation time is 2us, and a simulation result chart 3 is obtained.
FIG. 3 is a graph of the voltage at ports S1, S2, S4 and VDD over time for the circuit of the present invention under an ESD strike. The abscissa in fig. 3 represents the time of the simulation and the ordinate represents the voltage. The curve marked by squares in fig. 3 represents the VDD terminal voltage, the curve marked by diamonds represents the S1 terminal voltage, the curve marked by regular triangles represents the S2 terminal voltage, and the curve marked by inverted triangles represents the S4 terminal voltage. As can be seen from fig. 3, the signal at the end S1 is initially at a low level, the signal at the end S2 is at a high level, the signal at the end S4 is also at a high level, and the drain transistor is turned on to drain the electrostatic charges. When the ESD surge is over, the signal at the terminal S1 starts to increase, the signal at the terminal S4 is pulled down to a low level, and the bleeder transistor is turned off. In the whole process, the turn-on time of the bleeder transistor is 1.3us, which is much longer than 0.5us in the prior art.
The simulation results show that: under the condition of ESD impact, the invention starts the discharge transistor to discharge large current, and the ES D has better protection performance.
Simulation experiment 3, simulation under the condition of voltage rapid electrification.
A square wave pulse with the rise time of 100ns and the amplitude of 0-1.2V is added at a power supply VDD of the circuit to simulate the situation of rapid power-on of the power supply, a Spectre RF simulation tool is adopted to perform transient simulation on the circuit, the simulation time is 200us, and a simulation result graph 4 is obtained.
FIG. 4 is a graph of the voltage at ports S1, S2, S4 and VDD over time for the circuit of the present invention with the power supply powered up quickly. The abscissa in fig. 4 represents the time of the simulation and the ordinate represents the voltage. The square-shaped curve in fig. 4 represents the VDD terminal voltage, the diamond-shaped curve represents the S1 terminal voltage, the regular triangle-shaped curve represents the S2 terminal voltage, and the inverted triangle-shaped curve represents the S4 terminal voltage. As can be seen from fig. 4, the voltage at the S1 terminal increases with time, the signal at the S2 terminal is low, and the signal at the S4 terminal is low, so the bleeder transistor Mesd is always in a strictly off state. The power supply power loss caused by the phenomenon that the traditional power supply clamping circuit is triggered and conducted by mistake is avoided.
The simulation results show that: under the condition that the voltage is quickly electrified, the bleeder transistor is always in a closed state, false triggering cannot occur, and power loss caused by the false triggering is avoided.
The above-described example is only one implementation of the present invention, and it is to be understood that changes in form and detail may be made by those skilled in the art without inventive faculty, based on the basic principles, construction and details of the invention. Therefore, modifications and changes that may be suggested by those skilled in the art are intended to be included within the scope of the appended claims.

Claims (4)

1. An ESD power supply clamp protection circuit with a double-trigger structure comprises a transient trigger circuit and a bleeder circuit, and is characterized in that: the circuit also comprises a static trigger circuit and a synthesis control circuit; the output end of the transient trigger circuit is connected with a first input end S1 of the synthesis control circuit, the output end of the static trigger circuit is connected with a second input end S2 of the synthesis control circuit, the feedback end S3 of the synthesis control circuit is connected with the input end of the static trigger circuit, and the output end S4 of the synthesis control circuit is connected with the input end of the bleeder circuit; a first PMOS transistor P1, a second detection resistor R2, a diode string D1 and a first NMOS transistor M1 of the static trigger circuit are sequentially connected in series, the grid electrode of the first NMOS transistor M1 is the input end of the static trigger circuit, the source electrode of the first NMOS transistor M1 is connected with the ground terminal VSS, the grid electrode of the first PMOS transistor P1 is connected with the grid electrode of the second PMOS transistor P2, the source electrode of the second PMOS transistor P2 is connected with the power supply VDD, and the drain electrode of the first PMOS transistor P2 is connected with the third detection resistor R3 and the second input end S2 of the synthesis control circuit; the drain of the third PMOS transistor P3 of the synthesized control circuit is connected to the power supply VDD, the gate thereof is connected to the transient circuit output terminal V1, the source thereof is connected to the drain of the second NMOS transistor M2, the fifth detection resistor R5 and the input terminal of the static trigger circuit, the gate of the second NMOS transistor M2 is connected to the output terminal S2 of the static trigger circuit, and the source thereof is connected to the fourth detection resistor R4 and the input terminal of the bleeder circuit.
2. The ESD power clamp protection circuit for dual trigger architecture of claim 1, wherein: the transient trigger circuit comprises a first detection resistor R1 and a first detection capacitor C1, one end of the first detection resistor R1 is connected with a power supply end VDD, the other end of the first detection resistor R3526 is connected with an upper electrode plate of the first detection capacitor C1 and an input end of the synthesis control circuit, and a lower electrode plate of the first detection capacitor C1 is connected with a ground end VSS.
3. The ESD power clamp protection circuit for dual trigger architecture of claim 1, wherein: the drain circuit comprises a drain transistor Mesd, the grid electrode of the drain transistor Mesd is connected with the output end S4 of the synthesis control circuit, the drain electrode of the drain transistor Mesd is connected with a power supply VDD, the source electrode of the drain transistor Mesd is connected with a ground end VSS, and the setting range of the channel width W of the drain transistor Mesd is [1m, 2m ] m.
4. The ESD power clamp protection circuit for dual trigger architecture of claim 1, wherein: the RC in the transient trigger module is frequently set within a range of [100, 500] nanoseconds, wherein the resistance range of the resistor R1 is [50, 100] kilo-ohms, and the capacitance range of the capacitor C1 is [2, 5] picofarads.
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