CN113064652B

CN113064652B - Apparatus, method, device and medium for boot code of central processing unit

Info

Publication number: CN113064652B
Application number: CN202110357152.7A
Authority: CN
Inventors: 申彦垒; 张飞; 李小波
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-04-01
Filing date: 2021-04-01
Publication date: 2023-03-14
Anticipated expiration: 2041-04-01
Also published as: CN113064652A

Abstract

The present disclosure provides apparatuses, methods, devices, and media for boot code for a central processing unit. The apparatus for boot code of a central processing unit comprises the central processing unit, a transceiver controller, and an interconnected intellectual property core, the central processing unit configured to: loading and executing the first boot code or the second boot code to generate boot data; and transmitting the startup data to the terminal through the interconnection intellectual property core, the transceiver controller and the data transmission protocol bus so that the terminal monitors or debugs the startup of the central processing unit based on the startup data, wherein the first startup code is a startup code which is transmitted to the central processing unit by the terminal and is used for starting the central processing unit, and the second startup code is a startup code which is fixedly stored in a read-only memory of the central processing unit and is used for starting the central processing unit. According to the embodiment of the disclosure, flexible transmission of the boot code and monitoring and debugging of the boot of the central processing unit can be realized.

Description

Apparatus, method, device and medium for boot code of central processing unit

Technical Field

The present disclosure relates to the field of embedded technology, and more particularly, to an apparatus, method, device, and medium for boot code (Bootcode) for a Central Processing Unit (CPU).

Background

With the continuous development of embedded technology, embedded systems are widely applied in the field of high-performance CPUs, and because the embedded systems have stronger pertinence, which is usually determined according to the requirements of customers, the hardware difference of the embedded systems is larger, so that no uniform specification code exists. A hardware platform is set up into a hardware environment capable of loading an operating system through a series of settings of a boot loader (Bootloader), and the hardware environment comprises the steps of carrying out necessary initialization on a basic hardware environment and establishing physical mapping from a virtual space to a physical space. The starting code in the embedded system has specificity, the boot loaders of different hardware platforms are different, different CPU architectures have different boot loaders, and the boot loaders not only depend on the architecture of a processor, but also depend on the configuration of board-level equipment. The boot loader of the CPU is a key part in the development of an embedded system generally, because the code of the part is closely connected with hardware and the knowledge involved therein is more, the code of the part generally needs to be transplanted by self, and the code of the part is not easy to debug and is easy to cause problems.

Disclosure of Invention

The present invention provides an apparatus, method, device and medium for a boot code of a CPU, which improves development efficiency and overall performance of a system, in view of the disadvantages of the conventional boot code scheme of a high-performance CPU.

In order to achieve the above purpose, the technical solution for solving the technical problem is as follows:

one aspect of the invention discloses an apparatus for boot code of a central processing unit, comprising a central processing unit, a transceiver controller and an interconnected intellectual property core, wherein the transceiver controller is configured to transmit a first boot code for booting the central processing unit, which is transmitted by a terminal via a data transmission protocol, to the interconnected intellectual property core, and transmit boot data transmitted by the interconnected intellectual property core to the terminal via the data transmission protocol; the interconnect intellectual property core is configured to communicate the first boot code communicated by the transceiver controller to the central processing unit and to communicate the boot data communicated by the central processing unit to the transceiver controller; and a second boot code for booting the central processing unit is fixedly stored in a read-only memory of the central processing unit, and the central processing unit is configured to: loading and executing the first boot code or the second boot code to generate boot data; and transmitting the boot data via the interconnecting intellectual property core, the transceiver controller and via the data transfer protocol bus to a terminal for the terminal to monitor or debug the booting of the central processing unit based on the boot data.

For example, an apparatus provided in accordance with an embodiment of the present disclosure, wherein the central processing unit loading and executing the first boot code or the second boot code includes: transmitting an option to load and execute the first boot code or the second boot code to a terminal, and loading and executing the first boot code or the second boot code based on a selection of the option by the terminal; or loading and executing the second boot code; and in response to a boot failure of the central processing unit based on the second boot code, loading and executing the first boot code.

For example, an apparatus provided according to an embodiment of the present disclosure further includes: a status register configured to read a boot loader from a memory to transfer the boot loader to the central processing unit via the interconnected intellectual property core, wherein the boot loader and parameters for booting of an operating system are modified by the central processing unit according to the first boot code and stored in the memory in booting of the central processing unit, and the modified boot loader and parameters for booting of an operating system are acquired from the memory by the central processing unit for booting the operating system when the operating system is booted.

For example, an apparatus provided in accordance with an embodiment of the present disclosure, wherein the initiation data includes: and configuring corresponding control registers, state registers, the first start code or the second start code in the starting of the central processing unit and data of a start instruction according to the central processing unit.

For example, an apparatus is provided in accordance with an embodiment of the present disclosure, wherein the interconnect intellectual property core includes data protocol conversion between an advanced peripheral bus and a bus interconnect.

For example, an apparatus is provided in accordance with an embodiment of the present disclosure, wherein the transceiver controller includes a universal asynchronous transceiver or a universal synchronous/asynchronous transceiver.

For example, an apparatus is provided in accordance with an embodiment of the present disclosure, wherein the data transfer protocol bus comprises an electrical characteristics bus of a balanced voltage digital interface circuit.

Another aspect of the present invention discloses a method for starting code of a central processing unit, which is applied to the central processing unit and comprises the following steps: loading and executing the first boot code or the second boot code to generate boot data; and transmitting the boot data to a terminal for the terminal to monitor or debug the booting of the central processing unit based on the boot data; the first starting code is a starting code which is transmitted by the terminal to the central processing unit and is used for starting the central processing unit, and the second starting code is a starting code which is fixedly stored in a read-only memory of the central processing unit and is used for starting the central processing unit.

For example, according to a method provided by an embodiment of the present disclosure, the loading and executing the first boot code or the second boot code includes: transmitting an option for loading and executing the first boot code or the second boot code to a terminal, and loading and executing the first boot code or the second boot code based on a selection of the option by the terminal; or loading and executing the second boot code; and in response to a boot failure of the central processing unit based on the second boot code, loading and executing the first boot code.

For example, a method provided in accordance with an embodiment of the present disclosure further includes: receiving a boot loader from a memory; wherein the boot loader and the parameters for booting the operating system are modified by the central processing unit according to the first boot code and stored in the memory during booting of the central processing unit, and the modified boot loader and the parameters for booting the operating system are acquired from the memory by the central processing unit when the operating system is booted for booting the operating system.

For example, a method is provided according to an embodiment of the present disclosure, wherein the start data includes: and configuring corresponding control registers, state registers, the first start code or the second start code in the starting of the central processing unit and data of a start instruction according to the central processing unit.

For example, a method is provided according to an embodiment of the disclosure, wherein the first boot code and boot data are transmitted via a link comprising an interconnected intellectual property core, a transceiver controller, a data transfer protocol bus.

For example, a method is provided in accordance with an embodiment of the present disclosure, wherein the interconnect intellectual property core includes data protocol conversion between an advanced peripheral bus and a bus interconnect.

For example, a method is provided according to an embodiment of the present disclosure, wherein the transceiver controller includes a universal asynchronous transceiver or a universal synchronous/asynchronous transceiver.

For example, a method is provided in accordance with an embodiment of the present disclosure, wherein the data transfer protocol bus comprises an electrical characteristics bus of a balanced voltage digital interface circuit.

Another aspect of the present invention discloses an apparatus for boot code of a central processing unit, comprising: a memory storing computer program instructions; and a processor executing computer program instructions stored by the memory to cause the processor to perform the method as described above.

Another aspect of the invention discloses a computer storage medium having stored thereon instructions executable by a processor to perform a method as described above.

According to the embodiments of the present disclosure, on the one hand, a boot code for booting a central processing unit may be received from the outside, thereby enabling flexible transfer of the boot code; and on the other hand, the starting data generated in the starting process of the central processing unit can be transmitted to the terminal, so that the starting of the central processing unit can be monitored and debugged conveniently based on the starting data.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly described below. It is to be expressly understood that the drawings in the following description are directed to only some embodiments of the disclosure and are not intended as limitations of the disclosure.

FIG. 1 shows a schematic diagram of an apparatus for boot code for a CPU according to an embodiment of the present disclosure.

FIG. 2 shows a schematic diagram of another apparatus for boot code for a CPU according to an embodiment of the present disclosure.

Fig. 3 shows a flowchart of a system booting method of a NAND flash memory according to an embodiment of the present disclosure.

Figure 4 illustrates a block diagram of a universal asynchronous receiver transmitter in accordance with an embodiment of the present disclosure.

Fig. 5 illustrates a block diagram of a NIC400-APB, according to an embodiment of the present disclosure.

FIG. 6 illustrates a method for boot code of a CPU according to an embodiment of the present disclosure.

Fig. 7 shows a flowchart of a Boot (Boot) process according to an embodiment of the present disclosure.

FIG. 8 shows a schematic diagram of an apparatus for boot code for a CPU according to an embodiment of the present disclosure.

FIG. 9 shows a schematic diagram of a computer storage medium according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the specific embodiments, it will be understood that they are not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. It should be noted that the method operations described herein may be implemented by any functional block or functional arrangement, and that any functional block or functional arrangement may be implemented as a physical entity or a logical entity, or a combination of both.

In order that those skilled in the art will better understand the present invention, the following detailed description of the invention is provided in conjunction with the accompanying drawings and the detailed description of the invention.

Note that the examples to be described next are only specific examples, and are not intended as limitations on the embodiments of the present invention, and specific shapes, hardware, connections, operations, numerical values, conditions, data, orders, and the like, shown and described are necessary. Those skilled in the art can, upon reading this specification, utilize the concepts of the present invention to construct more embodiments than those specifically described herein.

To facilitate understanding of the present disclosure, some terms used in the present disclosure are exemplarily explained and illustrated below. However, it is to be understood that the terminology used in the disclosure is for the purpose of description only and is selected as exemplary, and not limiting.

Boot (Boot), is the Boot of an initialization program (e.g., a Boot loader) of a chip or processor core after system power-on.

The Boot code (Boot code) is an initial code executed by a chip or a processor core after a system is powered on or reset, that is, when the Boot starts, a CPU jumps to a base address of a ROM (Read-Only Memory) to execute a code. Boot code is stored in BootRom on a chip (e.g., in ROM of a CPU), and the first stage in the boot process is usually completed by the boot code, which may directly affect the efficiency of the later development and the overall performance of the system.

Along with the increasing improvement of integrated circuit design capability and manufacturing process technology, the scale of the integrated circuit is gradually enlarged, and the integration level of electronic components on a single chip is broken through by 10 hundred million. In this case, the correctness, completeness and reliability of the high-performance CPU chip become the key and difficulty of the verification work.

The invention provides a device, a method, equipment and a storage medium for starting codes of a CPU (Central processing Unit), aiming at the defects of the traditional high-performance CPU system starting code scheme, thereby improving the development efficiency and the overall performance of the system.

FIG. 1 shows a schematic diagram of an apparatus for boot code for a CPU according to an embodiment of the present disclosure. For convenience of description, fig. 1 shows only components related to an embodiment of the present disclosure, however, it should be understood that some components may be omitted or other components may be added in fig. 1.

As shown in fig. 1, an apparatus 100 for boot code of a CPU includes a CPU102, an interconnected intellectual property core 104, and a transceiver controller 106. In addition, FIG. 1 also shows a connector 108 in communication with the device 100. The transceiver controller 106 may communicate with the socket 108 via a data transmission protocol, where the socket 108 may be a terminal or other device that is the end of a communication. For example, the transceiver controller 106 may communicate with the terminal through a data transmission protocol to perform data transmission with the terminal. In embodiments of the present disclosure, a "terminal" refers to any suitable device having computing and data processing capabilities, including but not limited to a server, a computer, a wireless communication device, a handheld device, a Personal Digital Assistant (PDA), or any other suitable device configured to communicate via a wireless or wired medium. Further, the terminal that transmits the first start code and the terminal that receives the start data may be the same or different.

The transceiver controller 106 may be configured to transmit a first boot code for booting the CPU102, which is transmitted by the terminal via a data transmission protocol, to the interconnected intellectual property core 104, and transmit boot data transmitted by the interconnected intellectual property core 104 to the terminal via the data transmission protocol.

Interconnected intellectual property cores 104 may be configured to communicate a first boot code communicated by transceiver controller 106 to CPU102 and to communicate boot data communicated by CPU102 to transceiver controller 106.

Thus, communication between the CPU102 and the data transfer protocol interface may be achieved by interconnecting the intellectual property core 104 and the transceiver controller 106. In other words, the first boot code and boot data may be transmitted via a link comprising the interconnected intellectual property core 104, the transceiver controller 106, the data transfer protocol bus.

A Read-Only Memory (ROM) of the CPU102 fixedly stores therein a second boot code for booting the CPU, and the CPU102 may be configured to: loading and executing the first Boot code or the second Boot code to generate Boot data (Boot data); and transmitting the startup data to the terminal via the interconnecting intellectual property core 104, the transceiver controller 106 and via the data transfer protocol bus for the terminal to monitor or debug the startup of the CPU102 based on the startup data, in particular for a user of the terminal to monitor or debug the startup of the CPU102 based on the startup data.

As such, the apparatus 100 according to the embodiment of the present disclosure may implement communication between the CPU102 and the data transfer protocol interface by interconnecting the intellectual property core 104 and the transceiver controller 106, so that the boot code may be received from outside the apparatus 100. Compared with the traditional boot code which only can be executed in the boot process of the CPU and is fixedly stored in the ROM, the device 100 of the embodiment of the disclosure can provide new boot code for the CPU, and provides more flexible, correct and complete boot code transmission, thereby being suitable for different structures of the device 100.

Furthermore, the apparatus 100 according to the embodiment of the present disclosure may also transmit boot data generated during execution of the boot code to the terminal for the terminal to monitor or debug the booting of the CPU102 based on the boot data. For example, the startup data may be transmitted to a terminal in communication with the data transfer protocol bus, where the startup data is displayed for monitoring or debugging by a technician or user. A technician may modify or write new boot code based on the boot data and communicate it to CPU102 in real-time to successfully complete the boot of CPU102.

In some embodiments, the loading and executing of the first boot code or the second boot code by the CPU102 comprises: and loading and executing the first boot code or the second boot code based on the selection of the option by the terminal, specifically, the first boot code or the second boot code is loaded and executed based on the selection of the option by a user of the terminal. Therefore, technicians or users of the terminal can select proper starting codes to start the CPU according to actual needs, and flexibility of selection of the starting codes is improved.

In some embodiments, the CPU102 loading and executing the first boot code or the second boot code includes executing the second boot code; and in response to a boot failure of the CPU102 based on the second boot code, loads and executes the first boot code. In this way, a technician or user can be prevented from writing the boot code in advance without sufficiently knowing the structure of the apparatus, and the user can sufficiently know the structure of the apparatus based on the boot data generated during execution of the second boot code in order to write the boot code suitable for the structure of the current apparatus.

FIG. 2 shows a schematic diagram of another apparatus for boot code for a CPU according to an embodiment of the present disclosure. For convenience of description, fig. 2 shows only components related to an embodiment of the present disclosure, however, it should be understood that some components may be omitted or other components may be added in fig. 2.

As shown in FIG. 2, similar to the apparatus 100 shown in FIG. 1, the apparatus 200 for CPU boot code includes a CPU102, NIC400-APB 204, universal Asynchronous Receiver/Transmitter (UART) 206, and the like. The apparatus 200 may also include a Real Time Clock (RTC) 210, a status register 212, and an LED 216. In addition, fig. 1 also shows other components in communication with the apparatus 200. The status register 212 may communicate with the memory 214 to read from and write to the memory 214.

In some respects, the embodiment of fig. 2 may be understood as a more detailed embodiment of the embodiment shown in fig. 1. It will be understood, however, that the various components, modules or functions illustrated in fig. 2 are merely exemplary to enable a person of ordinary skill in the relevant art to understand the disclosure, and are not intended to limit the disclosure.

In some embodiments, the interconnect intellectual property core 104 in fig. 1 may include data protocol translation between an advanced peripheral bus and a bus interconnect (e.g., NIC400, design ware, noC (net-on-chip), etc.). Referring to fig. 2, the interconnected intellectual property cores 104 of fig. 1 may include NICs 400-APB 204. Specifically, NIC400-APB 204 includes data protocol translation between the advanced peripheral bus and NIC 400. Thus, the NICs 400-APB 204 may communicate with the UART 206, the RTC 210, the status register 212, the LED 216, etc. via an Advanced Peripheral Bus (APB) Bus or other suitable Bus to enable efficient communication of the CPU102 with these components. It is understood that the NICs 400-APB 204 are exemplary only and not limiting.

In some embodiments, the memory 214 may include Flash memory (also referred to as Flash memory (Flash)), generally divided into NOR Flash memory (NOR Flash) and NAND Flash memory (NAND Flash). NAND flash memories have a high storage density, a low cost, and a data reliability that is not as good as NOR flash memories, and are generally used for storing a large amount of data. Due to the limitation of the NAND flash memory interface, a special system interface is required during the use, which is also a big difficulty in the use of the NAND flash memory. The NIC400 is used as an interconnection intellectual property core (interconnection IP core) of the ARM, and can be highly configured as a high-performance network interconnection to realize data transmission between buses, so that communication between the CPU and the NAND flash memory can be realized based on the NIC400-APB 204, and the problem of limitation of the NAND flash memory to a special system interface can be well solved. It will be appreciated that other existing or future technologies may be used to implement the CPU to NAND flash memory communication.

In some embodiments, the data transmission protocol bus of fig. 1 includes an electrical characteristics bus (RS 422) of a balanced voltage digital interface circuit. Specifically, RS422 as a series of specifications employs a 4-wire, full-duplex, differential transmission, data transmission protocol for multipoint communication, which employs a transmission line employing balanced transmission employing one-way/non-reciprocal, with or without an enable terminal. RS422 serial port communication has the excellent characteristics of point-to-point communication, long transmission distance, strong anti-interference capability, high transmission rate and the like. In this manner, efficient and reliable data transmission of the apparatus 200 with, for example, a terminal may be achieved. However, embodiments are not limited thereto, and the data transfer protocol may also be other suitable buses, such as a peripheral component interconnect express (PCIe) bus or an Inter-Integrated Circuit (I2C) bus, etc.

In some embodiments, the transceiver controller 106 of fig. 1 may include a Universal Asynchronous Receiver/Transmitter (UART) or a Universal Synchronous/Asynchronous Receiver/Transmitter (USART) or other suitable Transmitter to enable data transmission between the APB interface and the RS 422.

Referring to fig. 2, the rtc 210 may be configured to provide timing signals to the NIC400-APB 204, UART 206, status register 212, LED 216, etc. for operation of the respective components. The RTC 210 may be implemented by a pure logic algorithm, and includes a timing function and a register function of the RTC therein. The input/output of the RTC 210 is an APB bus signal to efficiently transfer timing signals and the like to the respective components. The RTC 210 can internally set the current time and read and write the current time. The RTC 210 may be driven by a system clock, and its internal frequency divider may be used to count years, months, days, hours, minutes, seconds, etc. and also to generate various timing and counting interrupts. Alternatively, the RTC 210 may be replaced by a system clock, and the above-described functions are also implemented.

Status register 212 may be configured to read the boot loader from memory 214 to transfer the boot loader to CPU102 via NIC400-APB 204. The boot loader and the parameter for starting the Operating System (OS) may be modified by the CPU according to the first boot code and stored in the memory 214 during the startup of the CPU 214, or the boot loader and the parameter for starting the operating system may be transmitted to the terminal through the data transmission bus and modified and stored in the memory 214, and the boot loader and the parameter for starting the operating system may be acquired from the memory 214 by the CPU102 as the startup parameter when the operating system is started.

For example, the status register 212 may be defined as a transparent bridge (transparent bridge) from a slave (slave) of the APB bus to a bus end of the memory 214 (such as a NAND flash memory), which includes a transceiving function of the APB bus and a receiving function of the NAND flash memory bus. The normal operating state only executes a read sequence for reading the boot loader of the memory module system from the NAND flash memory. The boot loader and the operating system partial boot parameters may be modified by the boot code and stored in a fixed NAND flash memory space, or the boot loader and the parameters for booting of the operating system may be transferred to the terminal via a data transfer bus (e.g., via a link including the status register 212, NIC400-APB 204, CPU102, NIC400-APB 204, UART 206, RS 422) to be modified and stored in the memory 214, and the boot loader and the parameters for booting of the operating system may be retrieved from the NAND flash memory at the time of booting of the operating system and used as boot parameters.

Thus, the boot loader and the os partial boot parameters can be modified by the boot code transmitted through the RS422, or the boot loader and the os partial boot parameters can be modified by the terminal, so as to achieve correct and reliable booting of the os kernel.

Fig. 3 shows a flowchart of a system booting method of a NAND flash memory according to an embodiment of the present disclosure. In the embodiment shown in FIG. 3, the NAND flash memory uses only one direction of read data flow: and data is transmitted to the APB bus from the NAND flash memory interface, so that the CPU can directly read and write the address space of the NAND flash memory.

As shown in fig. 3, in operation S302, a device (e.g., device 200) is powered on and a CPU starts up from a NAND flash memory. In operation S304, a master boot loader and a copy of backup boot loader are stored in the NAND flash memory in advance, and an offset between each backup boot loader address with respect to an original address is stored in the NAND flash memory in advance. In operation S306, upon system booting, the CPU transmits a read control command and an original address to the NAND flash memory, reads a boot loader from the NAND flash memory, and executes it. In operation S308, it is determined whether the execution of the boot loader is successful. If so, the method proceeds to operation S310. In operation S310, the CPU transmits a timing signal to the NIC 400-APB. In operation S312, the NIC400-APB determines whether the timing signal is received within a prescribed time. If so, the method proceeds to operation S314 to complete the boot, at which point the boot is successful. If not, the method proceeds to operation S316 to determine whether there is a boot loader that has not been read. For example, the status register 212 stores the number of copies of the boot loader in advance, and when the timing unit of the RTL 210 does not receive the timing signal for a predetermined time, the status register 212 determines the number of times the boot loader stored in the addition unit in the status register 212 boots. If the current boot times is less than the number of copies of the boot loader, the boot loader is not accessed, the boot can be rebooted, and a notification of the reboot is sent to the adding unit. The status register 212 additionally issues a reset signal to the CPU. In operation S316, if there is no boot loader that has not been read, the method proceeds to operation S314 to complete the boot, at which point the boot is successful. In operation S316, if there is a boot loader that has not been read, the method returns to operation S306 to continue reading the boot loader from the NAND flash memory and executing. Returning to operation S308, if the boot loader did not execute successfully, the method proceeds to operation S214 to complete the boot, at which point the boot did not succeed.

With continued reference to FIG. 2, UART 206 may be defined as a transparent bridge of the slave-to-RS 422 interface of the APB bus. RS422 contains two data flow directions: data is transmitted from the RS422 interface to the APB bus; data is transferred from the APB bus to the RS422 interface. The UART 206 may be configured to implement only pass-through functionality for serial-to-parallel bus conversion. The UART 206 may communicate with the dedicated data processing board through the RS422 interface, and complete data acquisition of the dedicated data processing board in cooperation with the CPU.

FIG. 4 illustrates a block diagram of a UART according to an embodiment of the present disclosure. Referring to fig. 4, APB interface 402 is used to provide signals conforming to the timing of the APB bus, enabling the functional configuration and control of various components within device 100 by the CPU. The format of the data (e.g., RS422_ RX, RS422_ TX) transmitted and received by UART 206 is a standard data format, e.g., exhibiting a high-low level according to the baud rate clock, with each bit of data being transmitted occupying one complete cycle of the baud rate clock. The data coding/decoding module 404 may code/decode received data and data to be transmitted. The encoding module can complete the code conversion from the standard data to the RS422 data, and the decoding module can complete the code conversion from the RS422 data to the standard data.

As shown in fig. 4, in the data receiving direction, the received RS422 serial data (RS 422_ RX) is decoded, written into the serial data shift register 406 bit by bit from high order to low order, then is processed by the serial to parallel module 408 to perform serial to parallel operation, and buffered in the receiving FIFO 410. And when the APB bus gives a read operation instruction, sending the cached data to the APB bus. Conversely, in the data transmission direction, the CPU buffers the data into the transmission FIFO 412 through the APB interface 402. After the UART 206 receives the transmission command, the data buffered in the transmission FIFO 412 is parallel-to-serial converted by the parallel-to-serial module 414, and then is processed by the serial data shift register 416, for example, according to the configuration information, the data format is specified, and RS422 data (RS 422_ TX) is transmitted through encoding.

The CPU can write a plurality of data (determined by the FIFO depth) into the transmission FIFO 412 at a time, and sequentially fetch the data from the transmission FIFO 412 when the data is transmitted, so that the CPU can process other processes in parallel during transmission until the transmission is finished, and perform a new operation.

The interrupt module 418 may be used to generate interrupt signals, the state of all of which, as well as the source of the interrupt, are represented in an interrupt identification register. The interrupt signal is sent from the UART 206 and the RTC 210 to the NIC400 module included in the NIC400-APB 204, and the interrupt processing is performed inside the NIC400 module. The CPU102 continuously polls the interrupt register of each sub-module/component in the device 200 through the data bus, reports the interrupt register of each sub-module to the NIC400 data bus, and periodically reads the interrupt register of each sub-module through the upper layer software to perform interrupt determination.

When the device is running, the CPU102 first configures the initial values of the internal registers through the APB interface, such as the configuration of interrupt enable, FIFO control, etc., and their control bits are predefined in the control and status register 420 for reading and writing. In the control and status register 420, the control register generates various control signals to other functional blocks, and the status register marks the operating status of the device.

Referring back to fig. 2, the nicb 400-APB module 204 is mainly responsible for communication between the APB bus and the NIC400, and needs to decode signals of the APB bus, so that read/write commands of the APB bus can be correctly received and executed by the NIC400, and the APB interface stores address information of registers of each sub-module inside the apparatus 200 and controls reading and writing of the registers. The NIC400-APB mainly implements a host (host) bridge from the NIC400 bus to the APB on-chip bus, communicates with a CPU as a host of the NIC400 bus, and communicates with a plurality of sub-modules as slave terminals of the APB on-chip bus.

Fig. 5 illustrates a block diagram of a NIC400-APB, according to an embodiment of the present disclosure. As shown in FIG. 5, NIC400-APB 204 has two directions of operation: in one direction of operation, a data stream (e.g., boot code transmitted via RS 422) is transmitted to CPU102 through APB host (master) 504, APB on-chip bus, APB slave 506, and through NIC400, and CPU102 then sends the received data to ROM 510, SRAM 512, CRU (control register unit) 514 through Advanced eXtensible Interface (AXI) bus; in another operation direction, according to configuration of corresponding control registers and status registers of the CPU102 and read-back of data (Boot data) in Boot process, data flow is transmitted from the CPU102 to the APB on-chip bus through the NIC400508 and the Boot data is transmitted to the terminal through the RS422 bus for real-time monitoring or debugging. The two operation directions can be controlled by the CPU102, and the CPU102 can periodically read the interrupt register of each sub-module through the data bus.

Referring to fig. 5, the main functions of the apb host 504 include generating corresponding register addresses during function configuration and performing read and write operations on the control registers and status registers. The APB slave 506 receives valid data on the APB bus following the APB bus timing protocol and transmits the valid data to the NIC400508 or receives data from the NIC400 in a certain control order. NIC400508 follows the NIC400 interface protocol and interacts with a module (e.g., CPU 102) to which NIC400 is coupled, such as for example, for reading and writing.

The data sent by the CPU102 is finally put on the APB interface via the NIC400-APB 204 (the NIC400-APB 204 samples and outputs serial data according to the standard time sequence of the NIC 400), the APB interface stores the data in the corresponding control register, selection register, and shift register according to the address of the bus, so as to implement the boot of the apparatus 200, and the NIC400-APB 204 can cooperate with the CPU102 to complete the data read-write access and management operation of the apparatus, so as to implement the data communication between high-speed devices.

Boot is the initialization program Boot of the chip or the processor core after the system is powered on. The Boot has a main function of automatically moving an initialization program and an operating system program of the CPU102 to corresponding positions after the chip is powered on, so that the CPU102 can automatically run. The Boot function is divided into four parts, the first is to realize automatic loading of an initialization program stored in the NAND flash memory after power-on, and received Boot code data streams respectively transmitted to the SRAM 512, the ROM 510 and the CRU 514 of the CPU102 through the RS422 bus and the NIC400 bus to realize the Boot of the CPU102, and then release a CPU reset signal. The second is to move the initialization program first, then start the CPU102, and after the CPU program is loaded, move the device 200 configuration bits from the off-chip NAND flash memory to the configuration modules (e.g., CRUs in fig. 5) of the device 200 according to the CPU configuration. Thirdly, after the CPU program is loaded, corresponding control registers, state registers, and data (Boot data) such as Boot codes (e.g., first Boot codes or second Boot codes) and Boot instructions in the Boot process are configured according to the CPU102 to read back, for example, the Boot data is sent to the terminal through the NIC400 bus, so that a user of the terminal can obtain enough information generated in the Boot process, so that the user can monitor or modulate the Boot process; fourthly, after the CPU program is loaded, the operating system data is transferred from the NAND flash memory to the NIC400 bus memory space according to the configuration of the corresponding control register of the CPU102. The functions of the Boot described above are exemplary, and may be appropriately combined and adjusted as necessary.

Referring to fig. 5, ROM 510 is disposed only in CPU102 for storing boot code, and ROM 510 provides read-only storage for code and data via an AXI bus. The SRAM 512 is used to store boot code and data, and other code is run in the SRAM except a small amount of the boot code that runs in the ROM 510. The SRAM controller needs to be initialized, and the contents include the timing of the read and write accesses of the CPU102 to the SRAM 512, the data width, and the like. After the configuration of the SRAM 512 is completed, the boot loader is moved from the NAND flash memory to the SRAM 512 for operation. The CRU 514 is a CPU configuration unit, and is used to implement functions such as timer, interrupt, and reset control, and to store various configuration registers. Joint Test Action Group (JTAG) 516 may provide debug support primarily for internal testing of device 200. It is to be understood that the structure of the CPU and the bit width of the AXI bus shown in fig. 5 are merely exemplary, and are not limited thereto.

FIG. 6 illustrates a method for boot code for a CPU according to an embodiment of the present disclosure. The method of fig. 6 may be applied to CPU102 in apparatus 100 as described in fig. 1 or apparatus 200 as shown in fig. 2.

As shown in fig. 6, in operation S602, first boot code or second boot code is loaded and executed to generate boot data. In operation S604, the boot data is transmitted to the terminal for the terminal to monitor or debug the booting of the CPU based on the boot data. The first starting code is a starting code which is transmitted to the CPU by the terminal and is used for starting the CPU, and the second starting code is a starting code which is fixedly stored in a read-only memory of the CPU and is used for starting the CPU.

As such, a method according to an embodiment of the present disclosure may receive a boot code from the outside. Compared with the traditional CPU starting process which only can execute self-displaced starting codes fixedly stored in the ROM, the method of the embodiment of the disclosure can provide the CPU with new starting codes, provides more flexible, correct and complete starting code transmission, and can adapt to different device structures.

In addition, the method according to the embodiment of the disclosure can also transmit the starting data generated in the process of executing the starting code to the terminal so as to be used for monitoring or debugging the starting of the CPU by the terminal based on the starting data. For example, the startup data may be transmitted to a terminal in communication with the data transfer protocol bus, where the startup data is displayed for monitoring or debugging by a technician or user. The technician can modify or write new boot code based on the boot data and transmit it to the CPU in real time to successfully complete the boot of the CPU.

In some embodiments, loading and executing the first boot code or the second boot code comprises: transmitting an option for loading and executing the first boot code or the second boot code to the terminal, and loading and executing the first boot code or the second boot code based on a selection of the option by the terminal; or loading and executing the second boot code; and loading and executing the first boot code in response to a boot failure of the CPU based on the second boot code. Therefore, technicians or users of the terminal can select proper starting codes to start the CPU according to actual needs, and flexibility of selection of the starting codes is improved. In addition, a technician or user may be facilitated to write boot code that is appropriate for the architecture of the current device.

In some embodiments, a method according to embodiments of the present disclosure further comprises: receiving a boot loader from a memory; the boot loader and the parameters for starting the operating system can be modified by the CPU according to the first starting code and stored in the memory during the starting of the CPU, and can be acquired from the memory by the CPU when the operating system is started so as to be used for starting the operating system. In this way, boot loader and operating system partial boot parameters can be modified by the boot code passed through RS422 to achieve correct and reliable booting of the operating system kernel.

In some embodiments, the startup data comprises: the corresponding control register, status register, and boot code (e.g., first boot code or second boot code) in the boot of the CPU, data of the boot instruction are configured according to the CPU. Therefore, the user of the terminal can obtain enough information generated in the Boot process, so that the user can monitor or modulate the Boot process conveniently.

In some embodiments, the first boot code and the boot data may be transmitted via a link comprising an interconnected intellectual property core, a transceiver controller, a data transfer protocol bus.

In some embodiments, the interconnect intellectual property core includes a data protocol conversion between the advanced peripheral bus and the bus interconnect. In this way, high-performance network interconnection of the CPU and the peripheral components can be realized.

In some embodiments, the transceiver controller comprises a universal asynchronous transceiver or a universal synchronous/asynchronous transceiver. As such, data transfer between the APB interface and a data transfer protocol (e.g., RS 422) may be implemented.

In some embodiments, the data transmission protocol bus comprises an electrical characteristics bus (RS 422) of a balanced voltage digital interface circuit. Therefore, the method can realize excellent characteristics of point-to-point communication, long transmission distance, strong anti-interference capability, high transmission rate and the like.

Fig. 7 shows a flow chart of a boot process according to an embodiment of the disclosure.

As shown in fig. 7, in operation S702, the system is powered on/rebooted, and internal Boot configuration is performed. In operation S704, the boot code in the ROM is loaded. In operation S706, the boot code data transmitted via the RS422 bus processed by the NIC400 bus is received and transmitted to the CPU for processing. In operation S708, it is determined whether the transmission of the boot code transmitted by the RS422 is completed. If the transmission is not complete, the method returns to operation S706 to continue receiving the initiation code transmitted by RS 422. If the transmission is completed, the method proceeds to operation S710 to determine whether the boot code to be used at this time is the boot code transmitted via the RS422 bus or the boot code fixedly stored in the internal ROM, and the determining method has already been described in conjunction with the apparatus 100, and is not described herein again. Then, the method proceeds to operation S712 to jump to a new start code position and set an exception vector table. When an exception or interrupt occurs in the Boot starting process, the CPU points to the entry address of the corresponding interrupt vector for the starting exception handling process. In operation S714, a CPU clock is set, an interrupt is masked, and an instruction cache (cache) is enabled. In operation S716, the timing, data width, SRAM space, and the like of the memory (SRAM) read and write access are initialized. In operation S718, the boot loader is moved from the NAND flash memory to the SRAM to be executed. In operation S720, the basic hardware resources are initialized: serial ports, network ports, etc. In operation S722, the core is copied from the NAND flash memory to the SRAM. In operation S724, a kernel boot parameter is set, may be modified by a boot code and stored in a fixed NAND flash memory space, and is obtained from the NAND flash memory when the system is running, and is used as the boot parameter. In operation S726, the kernel is automatically booted according to the boot parameters, and the operating system kernel is booted. In this way, the whole boot process, i.e., the execution process of the boot code of operation S602, can be completed through the above operations, and the boot of the CPU is realized.

In the whole Boot process, corresponding control registers, state registers, boot codes (such as first Boot codes or second Boot codes) and data (Boot data) such as Boot instructions in the Boot process are configured according to the CPU for readback. That is, the read-back boot data includes the corresponding control register and status register according to the CPU configuration, and the boot code and boot instruction data in the boot of the CPU. However, embodiments are not so limited, and as will be appreciated by those skilled in the art, the boot data may include data generated throughout the boot process or data received and processed by the CPU. Then, in operation S728, the Boot data is transmitted to the terminal via the NIC400-APB module in RS422 bus mode, so as to monitor or debug the Boot sequence, boot instruction, boot status, and the like in real time.

As such, an aspect of embodiments of the present disclosure may transfer additional boot code to the CPU, thereby providing more flexible, correct, and complete boot code transfer; on the other hand, the method can monitor the AXI bus in the CPU, and transmits the AXI bus data to the terminal through the RS422 in real time, so that technicians or users can conveniently monitor or debug. In addition, new boot code written based on the boot data may be transferred to the CPU for booting, so that different configurations of the apparatus 100 may be accommodated.

Referring to fig. 8, a device 800 may include various components 802, 804. As shown in fig. 8, device 800 may include one or more processors 802 and one or more memories 804. It is contemplated that device 800 may include other components, as desired.

The device 800 may load and thus include one or more applications. The applications are sets of instructions (e.g., computer program code) that, when executed by the one or more processors 802, control the operation of the device 800. To this end, the one or more memories 804 may include instructions/data executable by the one or more processors 802, whereby the device 800 may perform methods or processes in accordance with the methods disclosed in this disclosure, and the advantages of the methods or means of the methods disclosed in this disclosure may likewise be mapped to the device 800.

Fig. 9 shows a schematic diagram of a computer storage medium, in this example a computer storage medium 900 in the form of a data disk, according to an embodiment of the present disclosure. However, embodiments are not so limited and the computer storage medium 900 may also be other media such as a compact disk, digital video disk, flash memory, or other commonly used memory technologies. In one embodiment, the data disk 900 is a magnetic data storage disk. The data disc 900 is configured to carry instructions 902, which instructions 902 may be loaded into the memory 804 of a device, such as the device 800 shown in fig. 8. The instructions, when executed by the processor 802 of the device 800, cause the device 1500 to perform methods or processes in accordance with the methods disclosed in this disclosure, and the advantages of the methods or apparatus of the methods disclosed in this disclosure may likewise be mapped to this computer storage medium.

In the foregoing detailed description, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the various aspects and embodiments described in the disclosure. In some instances, detailed descriptions of well-known devices, components, circuits, and methods are omitted so as not to obscure the description of the embodiments disclosed herein with unnecessary detail. All statements herein reciting principles, aspects, and embodiments disclosed, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure. Thus, for example, it is to be understood that the block diagrams herein may represent conceptual views of illustrative circuitry or other functional units embodying the principles of the described embodiments. Similarly, it will be appreciated that any flow charts and the like represent various processes which may be substantially represented in computer storage media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. The functions of the various elements comprising the functional block may be provided through the use of hardware, such as circuit hardware and/or hardware capable of executing software in the form of coded instructions stored on computer storage media as described above. Accordingly, such functions and illustrated functional blocks are to be understood as being hardware implemented and/or computer implemented and thus machine implemented. For a hardware implementation, the functional blocks may include or encompass, but are not limited to, digital Signal Processor (DSP) hardware, reduced instruction set processor (risc), hardware (e.g., digital or analog) circuitry, including but not limited to application specific integrated circuit(s) (ASIC) and/or field programmable gate array(s) (FPGA), and, where appropriate, state machines capable of performing these functions. With respect to computer embodiments, a computer is generally understood to include one or more processors or one or more controllers. When provided by a computer or processor or controller, the functions may be provided by a single dedicated computer or processor or controller, by a single shared computer or processor or controller, or by a plurality of individual computers or processors or controllers, some of which may be shared or distributed. Moreover, use of the terms "processor," "controller," or "control logic" may also be construed to refer to other hardware capable of performing such functions and/or executing software, such as the example hardware listed above.

The embodiments in the present specification are all described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same and similar between the embodiments may be referred to each other.

In several embodiments provided herein, it will be understood that each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block/operation may occur out of the order noted in the figures. For example, two blocks/operations shown in succession may, in fact, be executed substantially concurrently, or the blocks/operations may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block/operation of the block diagrams and/or flowchart illustration, and combinations of blocks/operations in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the operations of the method according to the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

It is noted that, herein, relational terms such as first, second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the appended claims and their equivalents.

Claims

1. An apparatus for starting code of a central processing unit comprises the central processing unit, a transceiver controller and an interconnected intellectual property core, wherein

The transceiver controller is configured to transmit a first boot code for booting the central processing unit, transmitted by a terminal via a data transmission protocol, to the interconnected intellectual property cores, and transmit boot data transmitted by the interconnected intellectual property cores to the terminal via the data transmission protocol;

the interconnected intellectual property core is configured to communicate the first boot code communicated by the transceiver controller to the central processing unit and to communicate the boot data communicated by the central processing unit to the transceiver controller; and is

The read-only memory of the central processing unit is fixedly stored with a second starting code for starting the central processing unit, and the central processing unit is configured to:

loading and executing the first boot code or the second boot code to generate boot data; and

transmitting the boot data via the interconnected intellectual property cores, the transceiver controller and via the data transfer protocol bus to a terminal for the terminal to monitor or debug the booting of the central processing unit based on the boot data.

2. The apparatus of claim 1, wherein the central processing unit to load and execute the first boot code or the second boot code comprises:

transmitting an option for loading and executing the first boot code or the second boot code to a terminal, and loading and executing the first boot code or the second boot code based on a selection of the option by the terminal; or alternatively

Loading and executing the second boot code; and in response to a boot failure of the central processing unit based on the second boot code, loading and executing the first boot code.

3. The apparatus of claim 1, further comprising:

a status register configured to read a boot loader from memory to transfer the boot loader to the central processing unit via the interconnect intellectual property core,

wherein the boot loader and the parameters for booting of the operating system are modified by the central processing unit according to the first boot code and stored in the memory in booting of the central processing unit, and the modified boot loader and the parameters for booting of the operating system are acquired from the memory by the central processing unit for booting of the operating system when the operating system is booted.

4. The apparatus of claim 1, wherein the initiation data comprises: and configuring corresponding control registers, state registers, the first start code or the second start code in the starting of the central processing unit and data of a start instruction according to the central processing unit.

5. The apparatus of any of claims 1-4, wherein the interconnect intellectual property core comprises a data protocol conversion between an advanced peripheral bus and a bus interconnect.

6. The apparatus of any of claims 1-4, wherein the transceiver controller comprises a universal asynchronous transceiver or a universal synchronous/asynchronous transceiver.

7. The apparatus of any of claims 1-4, wherein the data transfer protocol bus comprises an electrical characteristics bus of a balanced voltage digital interface circuit.

8. A method for starting code for a central processing unit, applied to the central processing unit, and comprising:

transmitting the boot data to a terminal for the terminal to monitor or debug the booting of the central processing unit based on the boot data;

the first starting code is a starting code which is transmitted to the central processing unit by the terminal and is used for starting the central processing unit, and the second starting code is a starting code which is fixedly stored in a read-only memory of the central processing unit and is used for starting the central processing unit.

9. The method of claim 8, the loading and executing the first boot code or the second boot code comprising:

transmitting an option for loading and executing the first boot code or the second boot code to a terminal, and loading and executing the first boot code or the second boot code based on a selection of the option by the terminal; or

10. The method of claim 8, further comprising:

receiving a boot loader from a memory;

wherein the boot loader and the parameters for booting the operating system are modified by the central processing unit according to the first boot code and stored in the memory during booting of the central processing unit, and the modified boot loader and the parameters for booting the operating system are acquired from the memory by the central processing unit when the operating system is booted for booting the operating system.

11. The method of claim 8, wherein the initiation data comprises: and configuring corresponding control registers, state registers, the first start code or the second start code in the starting of the central processing unit and data of a start instruction according to the central processing unit.

12. The method of any of claims 8-11, wherein the first boot code and boot data are transmitted via a link comprising an interconnected intellectual property core, a transceiver controller, a data transfer protocol bus.

13. The method of claim 12, wherein the interconnect intellectual property core comprises a data protocol conversion between an advanced peripheral bus and a bus interconnect.

14. The method of claim 12, wherein the transceiver controller comprises a universal asynchronous transceiver or a universal synchronous/asynchronous transceiver.

15. The method of claim 12, wherein the data transfer protocol bus comprises an electrical characteristics bus of a balanced voltage digital interface circuit.

16. An apparatus for boot code for a central processing unit, comprising:

a memory storing computer program instructions; and

a processor that executes computer program instructions stored by the memory to cause the processor to perform the method of any of claims 8-15.

17. A computer storage medium having instructions stored thereon, the instructions being executable by a processor to perform the method of any one of claims 8-15.