CN113055319A - Signal equalization method and device - Google Patents

Signal equalization method and device Download PDF

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CN113055319A
CN113055319A CN201911382480.1A CN201911382480A CN113055319A CN 113055319 A CN113055319 A CN 113055319A CN 201911382480 A CN201911382480 A CN 201911382480A CN 113055319 A CN113055319 A CN 113055319A
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llr
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CN113055319B (en
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尚冬冬
李星
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure

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  • Error Detection And Correction (AREA)

Abstract

The embodiment of the application provides a signal equalization method and a signal equalization device, relates to the field of communication, and can reduce the power consumption of output LLR. The signal equalization device comprises an equalization module 01, a filtering module 02, a hard decision decoding module 03, an LLR calculation module 04 and a first FEC module 05; the equalization module 01 is used for performing equalization processing on an input initial signal to obtain an equalized signal; the filtering module 02 is configured to perform filtering processing on the equalized signal to obtain a filtered signal; the hard decision decoding module 03 is configured to perform hard decision decoding processing on the filtered signal to obtain a hard decision value estimated by the maximum likelihood sequence; the LLR calculation module 04 is used for determining LLR; the LLR of the n time is determined according to the hard decision value of the n time and the probability information of the n time; the first FEC decoding module 05 is configured to perform forward error correction processing on the LLR to obtain a forward error correction decoding result. The embodiment of the application is applied to a signal transmission system.

Description

Signal equalization method and device
Technical Field
The present application relates to the field of communications, and in particular, to a signal equalization method and apparatus.
Background
With the rise of technologies such as big data and cloud computing, people have more and more vigorous demands on system transmission capacity. Regardless of short-distance traffic or long-distance traffic, higher capacity and higher quality are always the goals pursued. However, during the transmission process of the signal, due to the limitation of the bandwidth of each device in the signal transmission system, an Inter Symbol Interference (ISI) problem occurs, which greatly affects the quality of the signal.
In order to eliminate or reduce ISI of a signal, it is usually necessary to equalize the signal, for example, the signal may be equalized by a Maximum Likelihood Sequence Estimation (MLSE) algorithm. The MLSE algorithm comprises a soft decision mode and a hard decision mode. It can be considered that a hard decision algorithm is used when the signal is a binary code (e.g., -1 or-1) and a soft decision algorithm is used when the signal is a multi-element code (e.g., -1.532, 1.187). Although the complexity of the hard decision algorithm is lower than that of the soft decision algorithm, the soft decision algorithm is generally adopted in the related art because of the higher performance of the soft decision algorithm.
In the related art, the soft decision manner of the MLSE algorithm may be implemented by using a Soft Output Viterbi Algorithm (SOVA)/BCJR (proposed by l.r.bahl, j.cocke, E Jelinek, and j.raviv, etc.) algorithm, that is, a soft value, that is, a Log Likelihood Ratio (LLR) may be output by the SOVA/BCJR algorithm. However, the algorithm of SOVA/BCJR is high in complexity and large in power consumption. For example, when an On-Off Keying (OOK) demodulation format is used and the memory length of a channel is 1, the SOVA power consumption reaches 190 ten thousand gates and the BCJR power consumption reaches 198 ten thousand gates.
Disclosure of Invention
The embodiment of the application provides a signal equalization method and device, which can reduce the power consumption of output LLR.
In a first aspect, an embodiment of the present application provides a signal equalization apparatus, including an equalization module, a filtering module, a hard decision decoding module, a log-likelihood ratio LLR calculation module, and a first forward error correction FEC module; the output end of the equalization module is connected with the input end of the filtering module, the output end of the filtering module is respectively connected with the input end of the hard decision decoding module and the input end of the LLR calculation module, the output end of the hard decision decoding module is connected with the input end of the LLR calculation module, and the output end of the LLR calculation module is connected with the input end of the first FEC module; the equalization module is used for performing equalization processing on the input initial signal to obtain an equalized signal; the filtering module is used for filtering the balanced signal to obtain a filtered signal; the hard decision decoding module is used for carrying out hard decision decoding processing on the filtering signal to obtain a hard decision value estimated by the maximum likelihood sequence; the LLR calculation module is used for determining LLR; the LLR of the n time is determined according to the hard decision value of the n time and the probability information of the n time, and the probability information of the LLR of the n time is determined according to the hard decision value of the n-1 time and the filtering signal of the n-M time; wherein M is a positive number, n is an integer greater than or equal to M, and M is the decoding depth of the hard decision decoding module; the first FEC decoding module is used for carrying out forward error correction processing on the LLR to obtain a forward error correction decoding result.
The signal equalization device provided by the embodiment of the application can determine the LLR through the hard-decision decoding module and the LLR calculation module. Because the complexity of the hard decision decoding algorithm adopted by the hard decision decoding module is low, and the complexity of the probability information obtained by the LLR calculation module based on the hard decision value and the filtering signal is also low, the complexity of the algorithm of the signal equalization device provided by the embodiment of the application is lower than that of the algorithms such as SOVA/BCJR adopted by the MLSE module in the related technology, and therefore the signal equalization device provided by the embodiment of the application can reduce the power consumption of outputting LLRs.
In one possible implementation, the determining the probability information of the LLR at the n time instant according to the hard decision value at the n-1 time instant and the filtered signal at the n-M time instant includes: the probability information of the n time is determined according to the product of the hard decision value of the n-1 time and the filter coefficient of the filter module and the filter signal of the n-M time.
In one possible implementation, when the signal equalization apparatus is configured as a binary on-off keying OOK demodulation format and the memory length of the channel is 1, the LLR at n time satisfies the following formula:
LLR(n)＝Vit out(n)×abs(sigin(n-M)-Vit out(n-1)×c)；
wherein, LLR (n) represents LLR of n time, Vit out (n) represents hard decision value of n time, Vit out (n) E [ -1,1], Vit out (n-1) represents hard decision value of n-1 time, Vit out (n-1) E [ -1,1], c represents filtering coefficient of filtering module, sign (n-M) represents filtering signal of n-M time, M represents decoding depth, abs represents absolute value operation.
In one possible implementation, when the signal equalization apparatus is configured in a 4-level pulse amplitude modulation PAM4 format and the memory length of the channel is 1, the LLR at n time instant satisfies the following formula:
LLR(n)＝[HSB(n)，LSB(n)]；
HSB(n)＝H S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
LSB(n)＝L S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
wherein LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -3, -1,1, 3 ]; vit out (n-1) represents a hard decision value at time n-1, and Vit out (n-1) E-3, -1,1, 3; c represents the filter coefficient of the filter module, sign (n-M) represents the filter signal at the time of n-M, M represents the decoding depth, and abs represents the operation of the absolute value;
H S2B(Vit out(n))∈[-1，-1，1，1]；
L S2B(Vit out(n))∈[-1，1，-1，1]；
the SS2B (x) has a conversion relationship of SS2B (x) being x-2 if x is greater than 1; if x is less than 1 and greater than-1, SS2B (x) ═ x-0; if x is less than-1, SS2B (x) ═ x +2, where x denotes sign (n-M) -Vit out (n-1).
In a possible implementation manner, the signal equalization apparatus further includes a second FEC module, an input end of the second FEC module is connected to an output end of the hard-decision decoding module, and an output end of the second FEC module is connected to an input end of the LLR calculating module; and the second FEC module is used for carrying out forward error correction decoding processing on the hard decision value estimated by the maximum likelihood sequence to obtain an error-corrected hard decision value. The error rate of the hard decision value after error correction is lower, and the performance of the signal equalization device can be improved.
In one possible implementation, the hard-decision decoding module is a Viterbi decoding module.
In one possible implementation, the equalization module is a feed-forward equalizer FFE or a MIMO equalizer.
In a second aspect, an embodiment of the present application provides a signal equalization method, applied to an optical receiver, the method including: carrying out equalization processing on an input initial signal to obtain an equalized signal; carrying out filtering processing on the equalized signal to obtain a filtered signal; carrying out hard decision decoding processing on the filtering signal to obtain a hard decision value estimated by the maximum likelihood sequence; determining LLR according to the filtering signal and the hard decision value; the LLR of the n time is determined according to the hard decision value of the n time and the probability information of the n time, and the probability information of the LLR of the n time is determined according to the hard decision value of the n-1 time and the filtering signal of the n-M time; wherein M is a positive number, n is an integer greater than or equal to M, and M is the decoding depth of the hard decision decoding module; and carrying out forward error correction processing on the LLR to obtain a forward error correction decoding result.
The signal equalization method provided by the embodiment of the application can determine the LLR according to the filtering signal and the hard decision value. Wherein, the LLR of the n time is determined according to the hard decision value of the n time and the probability information of the n time. Because the complexity of the hard decision decoding algorithm is low, and the complexity of probability information obtained based on the hard decision value and the filtering signal is also low, the complexity of the signal equalization method provided by the embodiment of the application is lower than that of algorithms such as SOVA/BCJR adopted by an MLSE module in the related technology, and the like, so that the power consumption of output LLR can be reduced.
In one possible implementation, the determining the probability information of the LLR at the n time instant according to the hard decision value at the n-1 time instant and the filtered signal at the n-M time instant includes: the probability information of the n time is determined according to the product of the hard decision value of the n-1 time and the filter coefficient of the filter module and the filter signal of the n-M time.
In one possible implementation, when the optical receiver is configured as a binary on-off keying OOK demodulation format and the memory length of the channel is 1, the LLR for n time instant satisfies the following formula:
LLR(n)＝Vit out(n)×abs(sigin(n-M)-Vit out(n-1)×c)；
wherein, LLR (n) represents LLR of n time, Vit out (n) represents hard decision value of n time, Vit out (n) E [ -1,1], Vit out (n-1) represents hard decision value of n-1 time, Vit out (n-1) E [ -1,1], c represents filtering coefficient of filtering module, sign (n-M) represents filtering signal of n-M time, M represents decoding depth, abs represents absolute value operation.
In one possible implementation, when the optical receiver is configured in a 4-level pulse amplitude modulation PAM4 format and the memory length of the channel is 1, the LLR at n time instant satisfies the following equation:
LLR(n)＝[HSB(n)，LSB(n)]；
HSB(n)＝H S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
LSB(n)＝L S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
wherein LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -3, -1,1, 3 ]; vit out (n-1) represents a hard decision value at time n-1, and Vit out (n-1) E-3, -1,1, 3; c represents the filter coefficient of the filter module, sign (n-M) represents the filter signal at the time of n-M, M represents the decoding depth, and abs represents the operation of the absolute value;
H S2B(Vit out(n))∈[-1，-1，1，1]；
L S2B(Vit out(n))∈[-1，1，-1，1]；
the SS2B (x) has a conversion relationship of SS2B (x) being x-2 if x is greater than 1; if x is less than 1 and greater than-1, SS2B (x) ═ x-0; if x is less than-1, SS2B (x) ═ x +2, where x denotes sign (n-M) -Vit out (n-1).
In one possible implementation, the method further includes: and carrying out forward error correction decoding processing on the hard decision value estimated by the maximum likelihood sequence to obtain an error-corrected hard decision value.
In a third aspect, an embodiment of the present application provides an optical receiver, including: a memory, a processor and a computer program stored on the memory and capable of running on the processor, the processor implementing any one of the methods provided by the second aspect when executing the computer program.
In a fourth aspect, the present application provides a computer-readable storage medium, which includes instructions that, when executed on a computer, cause the computer to perform any one of the methods provided in the second aspect.
In a fifth aspect, the present application provides a computer program product containing instructions, which when run on a computer, causes the computer to perform any one of the methods provided in the second aspect.
In a sixth aspect, an embodiment of the present application provides a chip system, where the chip system includes a processor and may further include a memory, and is configured to implement any one of the methods provided in the second aspect. The chip system may be formed by a chip, and may also include a chip and other discrete devices.
Drawings
Fig. 1 is a schematic diagram of a signal transmission system in the related art;
fig. 2 is a schematic diagram of another signal transmission system in the related art;
fig. 3 is a schematic diagram of a signal equalization apparatus in the related art;
fig. 4 is a schematic diagram of a signal equalization apparatus according to an embodiment of the present application;
fig. 5 is a schematic diagram of another signal equalizing apparatus according to an embodiment of the present application;
fig. 6 is a schematic diagram of another signal equalizing apparatus according to an embodiment of the present application;
fig. 7 is a schematic diagram of another signal equalizing apparatus according to an embodiment of the present application;
FIG. 8 is a Gaussian distribution plot of the noise of an LLR according to an embodiment of the present application;
FIG. 9 is a Gaussian distribution plot of noise for one type of LLR in the related art;
fig. 10 is a graph illustrating a comparison of performance after equalization processing is performed on a signal according to an embodiment of the present application;
fig. 11 is a graph comparing performances of signals after equalization processing according to another embodiment of the present application;
fig. 12 is a schematic flowchart of an equalization method according to an embodiment of the present application;
fig. 13 is a schematic structural diagram of an optical receiver according to an embodiment of the present application.
Detailed Description
For clarity and conciseness of the following description of the various embodiments, a brief introduction to related concepts or technologies is first presented:
as shown in fig. 1, the signal transmission system may include a transmitting end, a transmission link (1ink), and a receiving end. The transmitting end may be an optical transmitting end (optical transmitter) or an electrical transmitting end (electrical transmitter), the transmission link may be a wireless link, a cable, an optical fiber, or the like, and the receiving end may be an optical receiving end (optical receiver) or an electrical receiving end (electrical receiver), which is not limited in this application. Illustratively, the signal transmission system may be, for example, a direct alignment detection system or a coherent system. The direct alignment detection system or the coherent system may include a short-distance transmission system (e.g., a 2km signal transmission system or a 10km signal transmission system, etc.) and a long-distance transmission system (e.g., a 100km signal transmission system or a 1000km signal transmission system).
In the following, a transmitting side is an optical transmitter, and a receiving side is an optical receiver. As shown in fig. 2, a transmitting end of a signal transmission system may include a Laser (Laser), a driver, and a modulator. The laser may be a Direct Modulation Laser (DML) or an electro-absorption modulated laser (EML). The receiving end may include a photoelectric conversion device (PD), an Analog Digital Converter (ADC), and a Digital Signal Processing (DSP) unit. The modulator and the photoelectric conversion device are connected through a transmission link. The optical signal emitted by the laser is driven by the driver and modulated by the modulator in sequence. For example, the modulator may perform soft forward error correction coding (soft FEC encode) on the optical signal, and include KP4 (also referred to as rs (reed solomon) -544 code), which improves the baud rate and improves the pre-correction limit performance. The optical signal modulated by the modulator can be transmitted to a receiving end through a transmission link. The photoelectric conversion device can convert optical signals into electric signals, the analog-to-digital converter performs analog-to-digital conversion on the electric signals, and the digital signal processing unit performs equalization processing on the signals after the analog-to-digital conversion to recover data. In addition, if the transmitting end is an electrical transmitter, the electrical transmitter may transmit an electrical signal (e.g., a serdes signal), and the receiving end may receive the electrical signal, which is specifically referred to in the prior art and will not be described herein.
It will be appreciated that ISI can occur during transmission of a signal due to the bandwidth limitations of the various components in the signal transmission system. To eliminate ISI as much as possible, the signal may be equalized at the DSP to ensure signal quality. It can be seen that the resources and power consumption of the DSP are very important, which determines the competitiveness of the signal transmission system. Current equalization algorithms include Feed Forward Equalization (FFE) algorithms, Decision Feedback Equalization (DFE) algorithms, MLSE algorithms, and the like. The Bit Error Rate (BER) is an index for measuring the accuracy of signal transmission, and the MLSE algorithm has better performance in terms of bit error rate, so the MLSE algorithm becomes the research focus in the field of signal equalization. The MLSE algorithm may include both soft and hard decision modes. It may be considered that a hard decision algorithm is used when the signal is a binary code (e.g., -1 or-1) and a soft decision algorithm is used when the signal is a multi-element code (e.g., -1.532, 1.187). Although the complexity of the hard decision algorithm is lower than that of the soft decision algorithm, the soft decision algorithm is generally adopted in the related art because of the higher performance of the soft decision algorithm.
As shown in fig. 3, in the related art, the digital signal processing unit may include a Feed Forward Equalizer (FFE), a filter (postfilter), an MLSE module, and an FEC module. The FFE can perform primary equalization processing on signals, the signals output by the FFE are free of ISI and nonlinear, but noise in the signals is changed into colored noise from white noise, the colored noise can be converted into the white noise by adopting a filter, controllable ISI is introduced at the same time, the introduced ISI can be solved by adopting an MLSE algorithm through an MLSE module to obtain an optimal solution, and then the optimal solution obtained by the solving is subjected to error correction processing through an FEC module to obtain more accurate output signals.
The FEC decoding method may include hard decision decoding and soft decision decoding. The input to the hard decision FEC (hard FEC) is two levels, e.g. the input to the hard decision FEC decoder may be 0, 1 or 1, -1. The input of the soft decision FEC (soft FEC) is a multi-level quantization level, for example, the input of the soft decision FEC may be 1.532, -1.1873. Under the conditions of the same code rate and the same pre-correction limit (pre-correction performance, namely the performance of a signal before FEC processing is not carried out, namely the error rate of the signal), the soft-decision decoding mode has higher gain than the hard-decision decoding mode, so that the soft-decision decoding mode can be adopted to carry out error correction decoding on the signal so as to improve the link budget. In order to match soft FEC, the MLSE module is required to output a "soft value", that is, the MLSE module is required to adopt a soft decision algorithm.
In the related art, the MLSE module may output a "soft value", i.e., an LLR, by using a SOVA/BCJR algorithm (the BCJR algorithm may also be referred to as a maximum a posteriori probability (MAP) algorithm). However, the algorithm of SOVA/BCJR is high in complexity and large in power consumption. For example, when the OOK demodulation format is adopted and the memory length of the channel is 1, the SOVA power consumption reaches 190 ten thousand gates, and the BCJR power consumption reaches 198 ten thousand gates. The BCJR/SOVA algorithm has very large power consumption, so that the MLSE outputs a soft value with huge power consumption, and the advantage of soft FEC is seriously weakened. There is therefore a need for a method and apparatus that can reduce the power consumption of MLSE output soft values.
The embodiment of the application provides a signal equalization device and a signal equalization method, which can reduce the power consumption of an MLSE output soft value. The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the present application, unless otherwise specified, "at least one" means one or more, "a plurality" means two or more. In addition, in order to facilitate clear description of technical solutions of the embodiments of the present application, in the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.
The embodiment of the present application provides a signal equalization apparatus, which is applied to a receiving end, for example, a digital signal processing unit in an optical receiver. As shown in fig. 4, the signal equalization apparatus includes an equalization module 01, a filtering module 02, a hard decision decoding module 03, an LLR calculation module 04, and a first FEC module 05. The output end of the equalization module 01 is connected with the input end of the filtering module 02, the output end of the filtering module 02 is respectively connected with the input end of the hard decision decoding module 03 and the input end of the LLR calculation module 04, the output end of the hard decision decoding module 03 is connected with the input end of the LLR calculation module 04, and the output end of the LLR calculation module 04 is connected with the input end of the first FEC module 05; wherein:
the equalizing module 01 is configured to perform equalization processing on an input initial signal to obtain an equalized signal. Illustratively, the equalization module 01 may be an FFE or (multiple input multiple output, MIMO) equalizer.
The filtering module 02 is configured to perform filtering processing on the equalized signal to obtain a filtered signal.
The hard decision decoding module 03 is configured to perform hard decision decoding processing on the filtered signal to obtain a hard decision value estimated by the maximum likelihood sequence. The hard decision decoding module can obtain a hard decision value according to the filtering signal and the filtering coefficient of the filtering module. Illustratively, the hard-decision decoding module 03 may be a Viterbi decoding module (abbreviated as Viterbi module). The hard decision decoding module 03 is taken as a Viterbi module for the following description.
The LLR calculating block 04 may determine LLRs according to input information of the Viterbi block (i.e., output information of the filtering block 02) and output information of the Viterbi block. Each time instance may correspond to an LLR, each LLR comprising two portions, the first portion being a symbol portion of the LLR and the second portion being a magnitude portion of the LLR. The LLR is the product of the first portion and the second portion. In the following, the process of determining LLRs at time n (i.e., LLR (n)) is described as an example, and the process of determining LLRs at other time (e.g., LLRs at time n-1, time n +1, etc.) can be analogically inferred. n may be an integer greater than or equal to 1.
Llr (n) is determined based on the hard decision value (i.e., the output information of the Viterbi block at time n, or the symbol output by the Viterbi block at time n) at time n and the probability information at time n. The sign part of llr (n) is determined according to the hard decision value at n time, i.e. the sign of llr (n) is the same as the sign of the hard decision value at n time, so that the pre-correction performance of llr (n) (i.e. the performance before FEC processing is not performed) can be ensured. The magnitude of LLR (n) is determined in part from the probability information of LLR (n) (i.e., the absolute value of the euclidean distance). Specifically, the probability information of LLR (n) is determined according to the hard decision value of n-1 time (output information of Viterbi at n-1 time) and the filtered signal of n-M time (input information of Viterbi module at n-M time).
Wherein M is a positive number, and n is an integer greater than or equal to M. M is the decoding depth of the hard-decision decoding module 03, which may also be referred to as a traceback length, and means that the filtered signal input to the hard-decision decoding module 03 at n-M moments is output at n moments through M moments, so that the input signal and the output signal of the Viterbi module can be aligned, and a delay (delay) generated in the process of processing the input signal by the Viterbi module is offset. M may be, for example, 1, 2, 3, etc.
Optionally, before performing the equalization processing on the initial signal, a Clock Data Recovery (CDR) module may also perform clock recovery processing on the initial signal.
The signal equalization device in the application completes the calculation of the soft value mainly through the Viterbi module and the LLR calculation module. The Viterbi block and the LLR calculation block may be collectively referred to as a D-SOVA block, which functions similarly to the MLSE block in the related art.
The signal equalization device provided by the embodiment of the application can determine the LLR through the D-SOVA module (the Viterbi module and the LLR calculation module). Because the complexity of the hard decision decoding algorithm adopted by the Viterbi module is lower, and the complexity of probability information obtained by the LLR calculation module based on the hard decision value and the filtering signal is also lower, the complexity of the algorithm of the D-SOVA module is lower than that of algorithms such as SOVA/BCJR adopted by the MLSE module in the related technology, and the like, the signal equalization device provided by the embodiment of the application can reduce the power consumption of outputting LLRs.
Soft values output by the D-SOVA module (i.e., signals after sequence decoding by the D-SOVA module) have excellent pre-correction performance, and can be used in cooperation with "soft FEC", i.e., LLRs can be input into the first FEC decoding module, and the first FEC decoding module can perform forward error correction decoding processing on the input LLRs to obtain a forward error correction decoding result. The first FEC decoding module is 'soft FEC', and because the 'soft FEC' has lower power consumption and delay than the 'hard FEC' under the same pre-correction limit, the power consumption and the delay can be reduced by adopting the 'soft FEC' to carry out error correction decoding on the signal, and on the basis, the scheme that a D-SOVA module is connected with a soft FEC in a cascading mode can be used as the solution of the next generation transmission system.
In one possible design, as shown in fig. 5, the signal equalization apparatus further includes a second FEC module 06, an input of the second FEC module 06 is connected to an output of the hard-decision decoding module 03, and an output of the second FEC module 06 is connected to an input of the LLR calculating module 04; the second FEC module 06 is configured to perform forward error correction decoding processing on the hard decision value output by the Viterbi module to obtain an error-corrected hard decision value. The error rate of the hard decision value after error correction is lower (namely, the accuracy rate is higher), and the performance of the signal equalization device can be improved.
Furthermore, one or more FEC modules may be further disposed after the second FEC module 06, and the hard decision value is iteratively decoded, so as to better reduce the error rate of the hard decision value. Because the LLR (n) is determined according to the hard decision value at the n moment and the probability information at the n moment, and the probability information at the n moment is determined according to the hard decision value at the n-1 moment and the filtering signal at the n-M moment, the error rate of the hard decision value (the hard decision value at the n moment and/or the hard decision value at the n-1 moment) is improved, the accuracy of the LLR (n) can be improved, and the performance of the signal equalizing device can be improved.
It can be appreciated that the more accurate the hard decision value, the more accurate the LLR. Therefore, the error rate of the hard decision value can be gradually improved by iterative processing by using a Turbo technology, or the hard decision value is iteratively decoded by using a plurality of FEC modules, or the hard decision value is output by using other modules (higher than the hard decision value output by the Viterbi module) capable of outputting the hard decision value with higher accuracy, so that the error rate of the hard decision value is better reduced, and the performance of the signal equalization device is improved.
In addition, as shown in fig. 6, the LLR may be determined according to the magnitudes of the output values of the hard decision decoding module 03 and the equalizer.
In the embodiment of the present application, the principle (calculation logic) of the D-SOVA module to obtain the probability information of the LLR is similar to the principle of the DFE algorithm, and the DFE algorithm satisfies the following formula:
y(n)＝sigin(n)–slicer(y(n-1))×c；
y (n) represents the output (magnitude/value) of the DFE algorithm at time n, y (n-1) represents the output (magnitude/value) of the DFE algorithm at time n-1 (i.e., the time immediately preceding time n), sign (n) represents the input (magnitude/value) of the DFE algorithm at time n, slicer (y (n-1)) represents the feedback of the DFE algorithm, and c represents the filter coefficients. The probability information of LLRs is obtained from the output amplitude of DFE equation (i.e., y (n)), i.e., the probability information of LLRs is the same as the computation logic of y (n).
The function of the LLR calculating module 04 is specifically described below for different demodulation formats and channel memory lengths.
As shown in fig. 7, when the memory length of the channel is 1, the LLR calculating block 04 may determine the LLR for the n time instant according to the hard decision value (Vit out (n)) for the n time instant and the probability information for the n time instant. Wherein the probability information of n time is based on the hard decision value (Vit out (n-1) of n-1 time, and can pass through Z-1The module (Z (-1) delays the Vit out (n) by a time instant to obtain the product of the Vit out (n-1)) and the filter coefficient (c) of the filter module 02 and the filtered signal (sign (n-M)) at the time instant n-M.
For example, when the initial signal is an OOK signal and the memory length of the channel is 1, the LLR for n time instants determined by the LLR calculating module 04 satisfies equation (1):
llr (n) × abs (sign (n-M) -Vit out (n-1) × c); formula (1)
Wherein, LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -1,1], Vit out (n-1) represents hard decision value at time n-1, Vit out (n-1) e [ -1,1], c represents filter coefficient of filter module 02, sign (n-M) represents filter signal at time n-M, M represents decoding depth, abs represents absolute value operation.
It can be understood that, when the memory length of the channel is 1, that is, the modulation order of the filtering module 02 is 2, the filtering coefficient at the time n may be [ c, 1], where c is a weight coefficient of the hard decision value at the time n-1, and 1 is a weight coefficient of the hard decision value at the time n. Accordingly, the filtered signal sign (n-M) input to the LLR calculating module 04 at the time n-M is ffe (n-M-1) × c + ffe (n-M). Wherein ffe (n-M) ═ Viterbi (n) + noise, ffe (n-M-1) ═ Viterbi (n-1) + noise. Since ISI is contained in the signal (n-M), the hard decision value output by the Viterbi block is reliable (trustworthy).
To remove ISI, the product of the hard decision value output by the Viterbi block at time n-1 and the filter coefficient c may be subtracted from the filtered signal. Namely, sign (n-M) -Vit out (n-1) × c is ffe (n-M) + c × noise. Where ffe (n-M) + c × noise is a signal without ISI and with a higher signal-to-noise ratio than ffe (n-M), and the absolute value of the signal indicates probability information (probability value) of LLR at time n.
It should be noted that the names of the signals and coefficients in the embodiment of the present application are only an example, and may also be other names, for example, sign may also be represented by pf _ dout, and c may also be represented by pf _ coef, and the present application is not limited thereto.
When the memory length of the channel is 2, the LLR calculating module 04 may determine probability information of the LLR at the n time according to the hard decision value at the n-1 time, the hard decision value at the n-2 time, and the filtered signal at the n-M time.
Illustratively, when the signal equalization apparatus is configured in the OOK format and the memory length of the channel is 2, the LLR for n time instants satisfies the following formula:
llr (n) × abs (sign (n-M) -Vit out (n-1) × c-Vit out (n-2) × d); formula (2)
Wherein, the reference numerals in formula 2 can refer to the related descriptions in formula 1.
It can be understood that, when the memory length of the channel is 2, that is, when the modulation order of the filtering module 02 is 3, the filtering coefficient at time n may be [ d, c, 1], where d is the weight coefficient of the hard decision value at time n-2, c is the weight coefficient of the hard decision value at time n-1, and 1 is the weight coefficient of the hard decision value at time n. Accordingly, the filter signal sign (n-M) input to the LLR calculation block 04 at the time n-M is ffe (n-M-2) × d + ffe (n-M-1) × c + ffe (n-M). Wherein ffe (n-M) ═ Viterbi (n) + noise, ffe (n-M-1) ═ Viterbi (n-1) + noise, and ffe (n-M-2) ═ Viterbi (n-2) + noise. Since ISI is contained in the sign (n-M), the hard decision value output by the Viterbi block is reliable.
To remove ISI, the filtered signal may be subtracted from the product of the hard decision value output by the Viterbi block at time n-1 and the filter coefficient c, and from the product of the hard decision value output by the Viterbi block at time n-2 and the filter coefficient d. Namely, sign (n-M) -Vit out (n-1) × c-Vit out (n-2) × d-ffe (n-M) + c × noise. Where ffe (n-M) + c × noise is a signal with higher signal-to-noise ratio than ffe (n-M) without ISI, and the absolute value of the signal indicates probability information of LLR at n time.
It should be noted that, when the signal equalization apparatus is configured in the OOK format and the memory length of the channel is other values, for example, 3, 4, or 5, etc., the formula satisfied by the llr (n) may be analogized according to the above description, which is not described herein again.
Illustratively, when the signal equalization apparatus is configured in PAM4 format and the memory length of the channel is 1, the LLR at n time satisfies the following equation:
llr (n) ═ hsb (n), lsb (n) ]; formula (3)
Hsb (n) ═ H S2B (Vit out (n)) × abs (SS2B (sign (n-M) -Vit out (n-1) × c)); formula (4)
Lsb (n) -L S2B (Vit out (n)) × abs (SS2B (sign (n-M) -Vit out (n-1) × c)) formula (5)
Wherein LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -3, -1,1, 3 ]; vit out (n-1) represents a hard decision value at time n-1, and Vit out (n-1) E-3, -1,1, 3; c represents the filter coefficient of the filter module 02, sign (n-M) represents the filter signal at the time of n-M, M represents the decoding depth, and abs represents the absolute value calculation;
H S2B(Vit out(n))∈[-1，-1，1，1]；
L S2B(Vit out(n))∈[-1，1，-1，1]；
the SS2B (x) has a conversion relationship of SS2B (x) being x-2 if x is greater than 1; if x is less than 1 and greater than-1, SS2B (x) ═ x-0, i.e., SS2B (x) ═ x; if x is less than-1, SS2B (x) ═ x +2, where x denotes sign (n-M) -Vit out (n-1).
It should be noted that when the signal equalization apparatus is configured in the PAM4 format, the hard decision value output by the Viterbi block at time n may include two bits, i.e., a high bit and a low bit, respectively, and the timing of the high bit is earlier than that of the low bit. Compared with the OOK demodulation format, the hard decision value output at the time n only includes one bit, and the rate of the signal equalization device adopting the PAM4 format can be doubled.
Illustratively, the Vit out (n) e-3, -1,1, 3, which can be decomposed into-1-1, -11, 1-1, 11, since the high bit is timed earlier than the low bit, i.e., the high bit e-1, -1,1, 1, the low bit e-1, 1, -1, 1. It can be seen that the high bit can take the value of-1 or 1 and the low bit can take the value of-1 or 1.
LLR (n) includes LLRs for two bits, i.e., LLR (n) includes hsb (n) for high bits and lsb (n) for low bits. Wherein, HSB (n) is determined according to the high bit of the hard decision value at the time n and the probability information at the time n. Lsb (n) is determined based on the low bits of the hard decision value at time n and the probability information at time n.
It will be appreciated that for hsb (n) or lsb (n), to remove ISI, the product of the hard decision value output by the Viterbi block at time n-1 and the filter coefficient c, i.e., sign (n-M) -Vit out (n-1) × c ffe (n-M) + c × noise, may be subtracted from the filtered signal. Where ffe (n-M) + c × noise is a signal without ISI and with a higher signal-to-noise ratio than ffe (n-M), and the absolute value of the signal indicates probability information (probability value) of LLR at time n.
Illustratively, when the signal equalization apparatus is configured in PAM4 format and the memory length of the channel is 2, the LLR at n time satisfies the following equation:
llr (n) ═ hsb (n), lsb (n) ]; formula (6)
Hsb (n) ═ H S2B (Vit out (n)) × abs (SS2B (sign (n-M) -Vit out (n-1) × c-Vit out (n-2) × d)); formula (7)
Lsb (n) -L S2B (Vit out (n)) × abs (SS2B (sign (n-M) -Vit out (n-1) × c-Vit out (n-2) × d)); formula (8)
The meanings of the parameters in the formulas (6) to (8) can refer to the descriptions in the formulas (2) to (5), which are not repeated herein.
It can be understood that, when the signal equalization apparatus is configured in the PAM4 format and the memory length of the channel is other values, for example, 3, 4, or 5, etc., the formula that the LLR at the n time satisfies may be analogized according to the above description, and details are not described here.
The performance and power consumption of the signal equalization apparatus provided in the present application will be described below by taking the demodulation format OOK and the channel memory length 1 as examples.
As shown in fig. 8, the signal equalization apparatus of the present application determines a gaussian distribution of noise of LLRs at a plurality of time points. As shown in fig. 9, the noise gaussian distribution diagram of the LLRs at a plurality of time points determined by the signal equalization apparatus using the SOVA algorithm in the related art is shown. In fig. 8 and 9, the abscissa represents the amplitude value (i.e., probability information), and the ordinate represents the number of times. The noise of the LLRs at the plurality of time instants determined by the signal equalization apparatus of the present application and the noise of the LLRs at the plurality of time instants determined by the signal equalization apparatus of the related art both follow a gaussian distribution (normal distribution), and the noise variance is approximately the same ("fat-thin") which reflects the magnitude of the noise variance, so that the performance of the signal equalization apparatus of the present application and the performance of the signal equalization apparatus of the related art are equivalent. The LLR calculated by the LLR calculating block 04 may be slightly different from the LLR obtained by the SOVA algorithm because the output value of the Viterbi block may be erroneous. It will be appreciated that if the noise of the LLRs is different, the noise variance is different (i.e., the "width" of the curve shape in the gaussian profile is different).
Meanwhile, when the signal equalization device in the related art adopts the BCJR/SOVA algorithm, the distribution range of output LLR is influenced by factors such as decoding depth, parallelism and the like, and the peak value of Gaussian distribution is changed due to different noise sizes. Illustratively, as shown in FIG. 9, the peak of the Gaussian distribution of the noise of the LLR in the correlation technique may be-5, 5 or-4, 4. As shown in fig. 8, the peak of the gaussian distribution of the noise of the LLR in the present application continues to be-1, 1. Compared with the related technology, the noise Gaussian distribution of the LLR in the application is more stable, is not influenced by factors such as decoding depth, parallelism and the like, is beneficial to the control of FEC entrance gain, and is more convenient to design.
For example, fig. 10 and fig. 11 are graphs comparing performances of signals after equalization processing is performed on the signals by using a signal equalization apparatus in the related art and a signal equalization apparatus provided in an embodiment of the present application, respectively. Where the abscissa is the received power (ROP) and the ordinate is the Bit Error Rate (BER). In fig. 10 and fig. 11, the relationship curve between ROP and be of the "pre-correction signal" output by the BCJR/HARD/SOVA algorithm (the "pre-correction signal" is a signal that is not processed by the FEC module) in the signal equalization apparatus in the related art is curve a, that is, curve a is the relationship curve between ROP and be of the "pre-correction signal" obtained based on the BCJR/HARD/SOVA algorithm. The relation curve between the ROP and the Ber of the "signal before correction" output by the signal equalization apparatus in the embodiment of the present application is also curve a. A relationship curve between ROP and be of a signal (i.e., a corrected signal) output by a signal equalization device in the related art after the signal (a HARD decision value) output by a HARD decision algorithm (HARD decision algorithm of MLSE) is processed by an FEC module is a curve B, that is, the curve B is a relationship curve between ROP and be of the corrected signal obtained based on the HARD decision algorithm; in the related art, a relation curve of ROP and be of a signal (soft value, namely LLR) output by a BCJR/SOVA algorithm and processed by an FEC module is a curve D, namely the curve D is the relation curve of the ROP and the be of the corrected signal obtained based on the BCJR/SOVA algorithm; the relationship curve between the ROP and the Ber of the signal (soft value, i.e., LLR) output by the D-SOVA module of the signal equalization apparatus in this application and processed by the first FEC module 05 ("signal after correction") is curve C, i.e., curve C is the relationship curve between the ROP and the Ber of the "signal after correction" output by the signal equalization apparatus in this application. Fig. 10 and 11 differ in that a curve B/C/D in fig. 10 is obtained by an FEC algorithm based on a BCH code (BCH is formed by a combination of initials of names of three persons, r.c. bose, d.k.ray-Chaudhuri, and a.hocquenghem), and a curve B/C/D in fig. 11 is obtained by an FEC algorithm based on a Low Density Parity Check (LDPC) code, and FEC of the BCH code and FEC of the LDPC code are FEC with different code rates.
Illustratively, as shown in fig. 10, when the BER is 1.00E-04, the abscissa of the curve D has a value of about-9.3 dBm, and the abscissa of the curve B has a value of about-8.3 dBm, i.e., the difference between the abscissa of the curve D and the abscissa of the curve B is about 1dBm, which may indicate the full performance gain of the soft FEC (i.e., the optimal performance gain that can be achieved after soft FEC processing on the soft values obtained by using the BCJR/SOVA algorithm). The abscissa of curve C has a value of about-9.1 dBm, and the difference between the abscissa of curve C and the abscissa of curve B is about 0.8dBm, i.e., the signal equalization apparatus in the present application can achieve 80% of the performance gain of the soft FEC gain. As shown in fig. 11, the abscissa of curve D has a value of about-27.5 dBm and the abscissa of curve B has a value of about-26.5 dBm for a BER of 1.00E-04, i.e., the abscissa of curve D differs from the abscissa of curve B by about 1dBm, which may represent the full performance gain of soft FEC. The abscissa of curve C has a value of about-27.3 dBm and the difference between the abscissa of curve C and the abscissa of curve B is about 0.8dBm, i.e., the signal equalization apparatus in the present application can achieve 80% of the performance gain of the soft FEC gain. It can be seen that the performance of the signal equalization apparatus provided by the present application is substantially consistent with that of the signal equalization apparatus in the related art.
Moreover, under the same parallelism and traffic rate, as shown in table 1, the signal equalizing apparatus in the present application consumes only half (50%) to 1/3 (33%) of the SOVA/BCJR algorithm in the related art, which is much lower than the resources consumed in the related art.
TABLE 1
Figure BDA0002342635240000101
It should be noted that, as the memory length increases and the demodulation format changes, the algorithm complexity of the BCJR/SOVA module becomes higher (exponentially increased), and the algorithm complexity of the D-SOVA module increases slowly and is far lower than that of the BCJR or SOVA module, so that the resource power consumption advantage of the D-SOVA module becomes more obvious as the memory length and the demodulation format increase.
In summary, the signal equalization apparatus provided in the embodiment of the present application may determine the LLR through the hard-decision decoding module and the LLR calculating module. Because the complexity of the hard decision decoding algorithm adopted by the hard decision decoding module is low, and the complexity of probability information obtained by the LLR calculation module based on the hard decision value and the filtering signal is also low, the complexity of the algorithm of the signal equalization device provided by the embodiment of the application is lower than that of algorithms such as SOVA/BCJR in the related technology, and therefore the signal equalization device provided by the embodiment of the application can reduce the power consumption of outputting LLRs.
The embodiment of the present application provides a signal equalization method, which may be used in an optical receiver, as shown in fig. 12, and the method includes:
1201. and carrying out equalization processing on the input initial signal to obtain an equalized signal.
1202. And carrying out filtering processing on the equalized signal to obtain a filtered signal.
1203. And carrying out hard decision decoding processing on the filtering signal to obtain a hard decision value of the maximum likelihood sequence estimation.
1204. An LLR is determined based on the filtered signal and the hard decision value.
The LLR of the n time is determined according to the hard decision value of the n time and the probability information of the n time, and the probability information of the LLR of the n time is determined according to the hard decision value of the n-1 time and the filtering signal of the n-M time; wherein, M is a positive number, n is an integer greater than or equal to M, and M is the decoding depth of the hard decision decoding module.
1205. And carrying out forward error correction processing on the LLR to obtain a forward error correction decoding result.
In one possible implementation, the determining the probability information of the LLR at the n time instant according to the hard decision value at the n-1 time instant and the filtered signal at the n-M time instant includes: the probability information at time n is determined from the product of the hard decision value at time n-1 and the filter coefficients of the filter module 02 and the filtered signal at time n-M.
In one possible implementation, when the optical receiver is configured in the OOK demodulation format and the memory length of the channel is 1, the LLR for n time instants satisfies the following equation:
LLR(n)＝Vit out(n)×abs(sigin(n-M)-Vit out(n-1)×c)；
wherein, LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -1,1], Vit out (n-1) represents hard decision value at time n-1, Vit out (n-1) e [ -1,1], c represents filter coefficient of filter module 02, sign (n-M) represents filter signal at time n-M, M represents decoding depth, abs represents absolute value operation.
In one possible implementation, when the optical receiver is configured in a 4-level pulse amplitude modulation PAM4 format and the memory length of the channel is 1, the LLR at n time instant satisfies the following equation:
LLR(n)＝[HSB(n)，LSB(n)]；
HSB(n)＝H S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
LSB(n)＝L S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
wherein LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -3, -1,1, 3 ]; vit out (n-1) represents a hard decision value at time n-1, and Vit out (n-1) E-3, -1,1, 3; c represents the filter coefficient of the filter module 02, sign (n-M) represents the filter signal at the time of n-M, M represents the decoding depth, and abs represents the absolute value calculation;
H S2B(Vit out(n))∈[-1，-1，1，1]；
L S2B(Vit out(n))∈[-1，1，-1，1]；
the SS2B (x) has a conversion relationship of SS2B (x) being x-2 if x is greater than 1; if x is less than 1 and greater than-1, SS2B (x) ═ x-0; if x is less than-1, SS2B (x) ═ x +2, where x denotes sign (n-M) -Vit out (n-1).
In a possible implementation manner, forward error correction decoding processing may be performed on the hard decision value of the maximum likelihood sequence estimation to obtain an error-corrected hard decision value.
In summary, the signal equalization method provided in the embodiment of the present application may determine the LLR according to the filtered signal and the hard decision value, where the LLR at n time is determined according to the hard decision value at n time and the probability information at n time. Because the complexity of the hard decision decoding algorithm is low, and the complexity of probability information obtained based on the hard decision value and the filtering signal is also low, the complexity of the signal equalization method provided by the embodiment of the application is lower than that of algorithms such as SOVA/BCJR adopted by an MLSE module in the related technology, and the like, so that the power consumption of output LLR can be reduced.
As shown in fig. 13, an embodiment of the present application further provides an optical receiver, including: a memory 1301 and a processor 1302, wherein the memory 1301 stores a computer program capable of running on the processor 1302, and when the processor 1302 executes the computer program, the signal equalization method as shown in fig. 12 is implemented.
Embodiments of the present application also provide a computer-readable storage medium, which includes instructions that, when executed on a computer, cause the computer to implement the signal equalization method shown in fig. 12.
Embodiments of the present application also provide a computer program product containing instructions, which when run on a computer, cause the computer to implement the signal equalization method as shown in fig. 12.
An embodiment of the present application further provides a chip system, where the chip system includes a processor and may further include a memory, and is used to implement the signal equalization method shown in fig. 12. The chip system may be formed by a chip, and may also include a chip and other discrete devices.
Those skilled in the art will recognize that in one or more of the examples described above, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above-mentioned embodiments, objects, technical solutions and advantages of the present application are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present application, and are not intended to limit the scope of the present application, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present application should be included in the scope of the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Claims (14)

1. A signal equalization device is characterized by comprising an equalization module, a filtering module, a hard decision decoding module, a log-likelihood ratio (LLR) calculation module and a first Forward Error Correction (FEC) module; the output end of the equalization module is connected with the input end of the filtering module, the output end of the filtering module is respectively connected with the input end of the hard decision decoding module and the input end of the LLR calculation module, the output end of the hard decision decoding module is connected with the input end of the LLR calculation module, and the output end of the LLR calculation module is connected with the input end of the first FEC module;
the equalization module is used for performing equalization processing on an input initial signal to obtain an equalized signal;
the filtering module is used for filtering the balanced signal to obtain a filtered signal;
the hard decision decoding module is used for carrying out hard decision decoding processing on the filtering signal to obtain a hard decision value estimated by a maximum likelihood sequence;
the LLR calculation module is used for determining LLR; the LLR of the n time is determined according to the hard decision value of the n time and the probability information of the n time, and the probability information of the LLR of the n time is determined according to the hard decision value of the n-1 time and the filtering signal of the n-M time; wherein, M is a positive number, n is an integer greater than or equal to M, and M is the decoding depth of the hard decision decoding module;
and the first FEC decoding module is used for carrying out forward error correction processing on the LLR to obtain a forward error correction decoding result.
2. The signal equalization apparatus as claimed in claim 1, wherein the probability information of the LLR for the n time instant is determined based on the hard decision value for the n-1 time instant and the filtered signal for the n-M time instant includes:
the probability information of the n time is determined according to the product of the hard decision value of the n-1 time and the filter coefficient of the filter module and the filter signal of the n-M time.
3. The signal equalization apparatus as claimed in claim 2, wherein when the signal equalization apparatus is configured as a binary on-off keying OOK demodulation format and the memory length of the channel is 1, the LLR for the n time instant satisfies the following formula:
LLR(n)＝Vit out(n)×abs(sigin(n-M)-Vit out(n-1)×c)；
wherein, LLR (n) represents LLR at n time, Vit out (n) represents hard decision value at n time, Vit out (n) E [ -1,1], Vit out (n-1) represents hard decision value at n-1 time, Vit out (n-1) E [ -1,1], c represents filtering coefficient of the filtering module, sign (n-M) represents filtering signal at n-M time, M represents decoding depth, abs represents absolute value operation.
4. The signal equalization apparatus as claimed in claim 2, wherein when the signal equalization apparatus is configured in a 4-level pulse amplitude modulation PAM4 format and a memory length of a channel is 1, the LLR at the n time instant satisfies the following equation:
LLR(n)＝[HSB(n)，LSB(n)]；
HSB(n)＝H S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
LSB(n)＝L S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
wherein LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -3, -1,1, 3 ]; vit out (n-1) represents a hard decision value at time n-1, and Vit out (n-1) E-3, -1,1, 3; c represents the filter coefficient of the filter module, sign (n-M) represents the filter signal at the time of n-M, M represents the decoding depth, and abs represents the operation of taking the absolute value;
H S2B(Vit out(n))∈[-1，-1，1，1]；
L S2B(Vit out(n))∈[-1，1，-1，1]；
the SS2B (x) has a conversion relationship of SS2B (x) being x-2 if x is greater than 1; if x is less than 1 and greater than-1, SS2B (x) ═ x-0; if x is less than-1, SS2B (x) ═ x +2, where x denotes sign (n-M) -Vit out (n-1).
5. The signal equalization apparatus as claimed in any one of claims 1 to 4, further comprising a second FEC module, an input of the second FEC module being connected to the output of the hard-decision decoding module, an output of the second FEC module being connected to the input of the LLR calculation module;
and the second FEC module is used for carrying out forward error correction decoding processing on the hard decision value estimated by the maximum likelihood sequence to obtain an error-corrected hard decision value.
6. The signal equalizing method of any one of claims 1 through 5, wherein the hard-decision decoding block is a Viterbi decoding block.
7. The signal equalization method according to any one of claims 1 to 6, wherein the equalization module is a Feed Forward Equalizer (FFE) or a MIMO equalizer.
8. A method of signal equalization for use in an optical receiver, the method comprising:
carrying out equalization processing on an input initial signal to obtain an equalized signal;
carrying out filtering processing on the equalized signal to obtain a filtered signal;
carrying out hard decision decoding processing on the filtering signal to obtain a hard decision value estimated by a maximum likelihood sequence;
determining an LLR according to the filtering signal and the hard decision value; the LLR of the n time is determined according to the hard decision value of the n time and the probability information of the n time, and the probability information of the LLR of the n time is determined according to the hard decision value of the n-1 time and the filtering signal of the n-M time; wherein, M is a positive number, n is an integer greater than or equal to M, and M is the decoding depth of the hard decision decoding module;
and carrying out forward error correction processing on the LLR to obtain a forward error correction decoding result.
9. The signal equalization method of claim 8, wherein the probability information of the LLR for the n time instant is determined based on the hard decision value for the n-1 time instant and the filtered signal for the n-M time instant comprises:
the probability information of the n time is determined according to the product of the hard decision value of the n-1 time and the filter coefficient of the filter module and the filter signal of the n-M time.
10. The signal equalization method as claimed in claim 9, wherein when the optical receiver is configured in a binary on-off keying (OOK) demodulation format and the memory length of the channel is 1, the LLR at the n time instant satisfies the following formula:
LLR(n)＝Vit out(n)×abs(sigin(n-M)-Vit out(n-1)×c)
wherein, LLR (n) represents LLR at n time, Vit out (n) represents hard decision value at n time, Vit out (n) E [ -1,1], Vit out (n-1) represents hard decision value at n-1 time, Vit out (n-1) E [ -1,1], c represents filtering coefficient of the filtering module, sign (n-M) represents filtering signal at n-M time, M represents decoding depth, abs represents absolute value operation.
11. The signal equalization method as claimed in claim 9, wherein when the optical receiver is configured in a 4-level pulse amplitude modulation PAM4 format and the memory length of the channel is 1, the LLR at the n time instant satisfies the following equation:
LLR(n)＝[HSB(n)，LSB(n)]；
HSB(n)＝H S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
LSB(n)＝L S2B(Vit out(n))×abs(SS2B(sigin(n-M)-Vit out(n-1)×c))；
wherein LLR (n) represents LLR at time n, Vit out (n) represents hard decision value at time n, Vit out (n) e [ -3, -1,1, 3 ]; vit out (n-1) represents a hard decision value at time n-1, and Vit out (n-1) E-3, -1,1, 3; c represents the filter coefficient of the filter module, sign (n-M) represents the filter signal at the time of n-M, M represents the decoding depth, and abs represents the operation of taking the absolute value;
H S2B(Vit out(n))∈[-1，-1，1，1]；
L S2B(Vit out(n))∈[-1，1，-1，1]；
the SS2B (x) has a conversion relationship of SS2B (x) being x-2 if x is greater than 1; if x is less than 1 and greater than-1, SS2B (x) ═ x-0; if x is less than-1, SS2B (x) ═ x +2, where x denotes sign (n-M) -Vit out (n-1).
12. A method for equalizing a signal according to any one of claims 8-11, further comprising:
and carrying out forward error correction decoding processing on the hard decision value estimated by the maximum likelihood sequence to obtain an error-corrected hard decision value.
13. An optical receiver, characterized in that the optical receiver comprises: a memory, a processor and a computer program stored on the memory and capable of running on the processor, when executing the computer program, implementing the signal equalization method of any of claims 8-12.
14. A computer-readable storage medium comprising instructions which, when executed on a computer, cause the computer to perform the signal equalization method of any one of claims 8-12.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115987726A (en) * 2022-12-23 2023-04-18 吉林大学 Decoding algorithm based on combination of nonlinear equalization and FEC
WO2024060744A1 (en) * 2022-09-21 2024-03-28 深圳市中兴微电子技术有限公司 Maximum likelihood sequence detection circuit, detection method, detection apparatus and electronic device

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1705301A (en) * 2004-06-01 2005-12-07 北京大学 Channel equalization method of OFDM system
CN101237434A (en) * 2008-03-10 2008-08-06 电子科技大学 A soft judgement method for Graham M-PSK modulation
CN101356790A (en) * 2006-09-29 2009-01-28 日本电气株式会社 Logarithmic likelihood ratio calculating circuit, transmitter apparatus, logarithmic likelihood ratio calculating method and program
CN101582699A (en) * 2009-06-24 2009-11-18 重庆金美通信有限责任公司 Soft-decision LLR calculating method of Turdo and LDPC transcode used for two-level modulation input
US20100074319A1 (en) * 2008-09-25 2010-03-25 Sunplus Technology Co., Ltd. Decoding system for LDPC code concatenated with 4QAM-NR code
JP2013225748A (en) * 2012-04-20 2013-10-31 Nippon Telegr & Teleph Corp <Ntt> Radio communication device and radio communication method
CN105337918A (en) * 2014-08-07 2016-02-17 展讯通信（上海）有限公司 Method and device for obtaining log-likelihood ratio
EP3113436A1 (en) * 2014-02-24 2017-01-04 Mitsubishi Electric Corporation Soft decision value generation apparatus and soft decision value generation method
CN106656885A (en) * 2017-02-22 2017-05-10 北京航空航天大学 Balancing method and apparatus of OFDM system for defending large-delay multipath interference
CN108353047A (en) * 2015-11-04 2018-07-31 三菱电机株式会社 The method and receiver be decoded to the symbol sent by channel
CN109995474A (en) * 2019-03-29 2019-07-09 舟山美通信息技术有限责任公司 A kind of SISO communication equipment implementation based on SDFE and Turbo code iterative equalization and decoding
CN110061761A (en) * 2018-01-19 2019-07-26 华为技术有限公司 Signal equalizing method and device, photoreceiver

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1705301A (en) * 2004-06-01 2005-12-07 北京大学 Channel equalization method of OFDM system
CN101356790A (en) * 2006-09-29 2009-01-28 日本电气株式会社 Logarithmic likelihood ratio calculating circuit, transmitter apparatus, logarithmic likelihood ratio calculating method and program
CN101237434A (en) * 2008-03-10 2008-08-06 电子科技大学 A soft judgement method for Graham M-PSK modulation
US20100074319A1 (en) * 2008-09-25 2010-03-25 Sunplus Technology Co., Ltd. Decoding system for LDPC code concatenated with 4QAM-NR code
CN101582699A (en) * 2009-06-24 2009-11-18 重庆金美通信有限责任公司 Soft-decision LLR calculating method of Turdo and LDPC transcode used for two-level modulation input
JP2013225748A (en) * 2012-04-20 2013-10-31 Nippon Telegr & Teleph Corp <Ntt> Radio communication device and radio communication method
EP3113436A1 (en) * 2014-02-24 2017-01-04 Mitsubishi Electric Corporation Soft decision value generation apparatus and soft decision value generation method
CN105337918A (en) * 2014-08-07 2016-02-17 展讯通信（上海）有限公司 Method and device for obtaining log-likelihood ratio
CN108353047A (en) * 2015-11-04 2018-07-31 三菱电机株式会社 The method and receiver be decoded to the symbol sent by channel
CN106656885A (en) * 2017-02-22 2017-05-10 北京航空航天大学 Balancing method and apparatus of OFDM system for defending large-delay multipath interference
CN110061761A (en) * 2018-01-19 2019-07-26 华为技术有限公司 Signal equalizing method and device, photoreceiver
CN109995474A (en) * 2019-03-29 2019-07-09 舟山美通信息技术有限责任公司 A kind of SISO communication equipment implementation based on SDFE and Turbo code iterative equalization and decoding

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024060744A1 (en) * 2022-09-21 2024-03-28 深圳市中兴微电子技术有限公司 Maximum likelihood sequence detection circuit, detection method, detection apparatus and electronic device
CN115987726A (en) * 2022-12-23 2023-04-18 吉林大学 Decoding algorithm based on combination of nonlinear equalization and FEC

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