CN113055224B

CN113055224B - Equipment message forwarding fault detection and device

Info

Publication number: CN113055224B
Application number: CN202110162200.7A
Authority: CN
Inventors: 程基; 吕进文; 闫波
Original assignee: New H3C Security Technologies Co Ltd
Current assignee: New H3C Security Technologies Co Ltd
Priority date: 2021-02-05
Filing date: 2021-02-05
Publication date: 2022-05-27
Anticipated expiration: 2041-02-05
Also published as: CN113055224A

Abstract

The application provides a method and a device for detecting message forwarding faults in equipment, which are applied to switch equipment, wherein the switch comprises a CPU (central processing unit), a switching chip and an FPGA (field programmable gate array), and the method comprises the following steps: the CPU receives an interrupt event reported by the FPGA; the CPU obtains a plurality of recorded latest timestamps from the FPGA; the CPU extracts a first time stamp corresponding to the BFD message with the represented session state being a down state and a second time stamp which is later than the first time stamp from the plurality of latest time stamps; if the CPU confirms that the time interval between the second time stamp and the first time stamp is not smaller than the set session detection interval, the message forwarding in the switch equipment is confirmed to be fault-free; and if the CPU confirms that the time interval between the second time stamp and the first time stamp is smaller than the set session detection interval, confirming that a fault exists in message forwarding in the switch equipment. Therefore, the condition whether the message forwarding fault exists in the switch equipment can be quickly positioned, and an effective basis is provided for the correctness of the detection result.

Description

Equipment message forwarding fault detection and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for detecting a message forwarding fault in a device.

Background

Bidirectional Forwarding Detection (BFD) is a general, standardized, media independent and protocol independent fast failure Detection mechanism for detecting the connectivity status of links in an IP network and ensuring that communication failures can be detected quickly between devices, so that measures can be taken in time to ensure continuous operation of services. And when the diag value is 1 when looking UP- > DOWN in the BFD session state DOWN, the detection of the local terminal is over time. In actual networking, the timeout of local terminal detection is not necessarily caused by link forwarding failure, and may also be caused by congestion when the BFD detection packet is forwarded in the local terminal device. And after a certain BFD session shock occurs, the BFD session shock is quickly recovered, so that effective information can not be provided at present to confirm what the BFD session shock is caused, and particularly in the current network environment, the BFD session shock can be butted with various brands of manufacturer equipment, and the environment is complex. If the local terminal of the device detects the time-out, if the fault caused by congestion delay or packet loss due to forwarding in the device itself cannot be accurately eliminated, a larger amount of time and energy are consumed to solve the problem of the BFD session oscillation, and the labor input is greatly increased.

Therefore, how to quickly detect whether the BFD session is caused by forwarding inside the local device when the BFD session oscillates is one of the considerable technical problems to save the examination time and reduce the cost.

Disclosure of Invention

In view of this, the present application provides a method and an apparatus for detecting a message forwarding failure in a device, so as to quickly detect whether the message forwarding failure is caused by forwarding inside a local device when a BFD session oscillates, thereby saving a troubleshooting time and reducing a cost.

Specifically, the method is realized through the following technical scheme:

according to a first aspect of the present application, a method for detecting a message forwarding fault in a device is provided, which is applied to a switch device, where the switch device includes a central processing unit CPU, a switching chip, and a field programmable gate array FPGA, and the method includes:

the CPU receives an interrupt event reported by the FPGA, wherein the interrupt event is triggered when the BFD session represented by the BFD message is determined to be in a down state after the BFD message forwarded by the switching chip is received by the FPGA;

the CPU obtains a plurality of recorded latest timestamps from the FPGA, wherein each timestamp is extracted from a corresponding BFD message by the FPGA, and each timestamp is the entering time when the corresponding BFD message enters the exchange chip and is written into the corresponding BFD message by the exchange chip;

the CPU extracts a first time stamp corresponding to the BFD message with the represented session state being a down state and a second time stamp which is later than the first time stamp from the plurality of latest time stamps;

if the CPU confirms that the time interval between the second time stamp and the first time stamp is not smaller than the set session detection interval, the CPU confirms that the message forwarding in the switch equipment is faultless;

and if the CPU confirms that the time interval between the second time stamp and the first time stamp is smaller than the set session detection interval, confirming that a fault exists in message forwarding in the switch equipment.

According to a second aspect of the present application, there is provided an in-device message forwarding fault detection apparatus, applied to a switch device, where the switch device includes a central processing unit CPU, a switch chip, and a field programmable gate array FPGA, the apparatus includes:

a receiving module, configured to receive an interrupt event reported by the FPGA, where the interrupt event is triggered when a session state of a BFD session represented by a BFD packet is determined to be a down state after the BFD packet forwarded by the switch chip is received by the FPGA;

the first acquisition module is used for acquiring a plurality of recorded latest timestamps from the FPGA, wherein each timestamp is extracted from the corresponding BFD message by the FPGA, and each timestamp is the entering time when the corresponding BFD message enters the exchange chip and is written into the corresponding BFD message by the exchange chip;

the extracting module is used for extracting a first time stamp corresponding to the BFD message with the represented session state being a down state from the plurality of latest time stamps and extracting a second time stamp which is later than the first time stamp;

the first judging module is used for judging whether the time interval between the second timestamp and the first timestamp is not less than a set session detection interval or not;

a determining module, configured to determine that there is no failure in forwarding a message in the switch device if a determination result of the first determining module is not smaller than a set session detection interval;

the determining module is further configured to determine that there is a failure in forwarding a message in the switch device if the determination result of the first determining module is smaller than the set session detection interval.

The beneficial effects of the embodiment of the application are as follows:

by implementing the method for detecting the forwarding fault in the equipment provided by the embodiment, whether the message forwarding fault exists in the switch equipment can be quickly positioned, and an effective basis is provided for the correctness of the detection result.

Drawings

Fig. 1 is a schematic flowchart of a method for detecting a message forwarding fault in a device according to an embodiment of the present application;

fig. 2 is a schematic internal structure diagram of a switch device according to an embodiment of the present application;

fig. 3 is a schematic flowchart of another method for detecting a message forwarding fault in a device according to an embodiment of the present application;

fig. 4 is a schematic view of an application scenario of a method for detecting a message forwarding fault in a device according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an in-device message forwarding fault detection apparatus according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects such as the present application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.

It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if," as used herein, may be interpreted as "at … …" or "when … …" or "in response to a determination," depending on the context.

The method for detecting a message forwarding fault in a device provided by the present application is described in detail below.

Referring to fig. 1, fig. 1 is a flowchart of a method for detecting a message forwarding fault in a device according to the present invention, where the method is applied to a switch device shown in fig. 2, where the switch device includes a central processing unit CPU, a switching chip, and a field programmable gate array FPGA, and when the switch device implements the method, the following steps may be performed:

s101, the CPU receives the interrupt event reported by the FPGA.

The interrupt event is triggered when the session state of the BFD session represented by the BFD message is determined to be a down state after the BFD message forwarded by the switching chip is received by the FPGA.

Specifically, the BFD session table entry is established on the FPGA, and the FPGA is responsible for receiving and sending BFD messages, and when the BFD messages enter the switch device, the BFD messages first reach the switch chip of the switch device, and then the switch chip sends the BFD messages to the FPGA chip in the switch device, and finally the FPGA forwards the BFD messages to the outside; specifically, after the BFD message reaches a Port a of the switch device, the switch chip captures the BFD message that conforms to the ACL rules through the access control list ACL, and then sends the captured BFD message to the FPGA through an interconnection Port GE Port between the switch chip and the FPGA. The FPGA side starts a timer, and detects whether the detection time is exceeded or not after receiving the BFD message. When the FPGA detects that the BFD message is overtime and is detection, the BFD message indicates that the session state of the BFD session represented by the BFD message is a down state, and then the FPGA reports an interrupt event about the down state to the CPU.

S102, the CPU obtains a plurality of recorded latest timestamps from the FPGA.

Each time stamp is extracted from the corresponding BFD message by the FPGA, and each time stamp is the entering time when the corresponding BFD message enters the exchange chip and is written into the corresponding BFD message by the exchange chip.

Specifically, in order to verify that the detection of the switch equipment is accurate and correct, the application provides that a timestamp stamping work is added at an input port of the switch chip, namely, after the switch chip receives each BFD message, the switch chip adds the time of entering the BFD message, namely, the timestamp, to the BFD message, and then sends the BFD message with the timestamp to the FPGA, so that after the FPGA receives each BFD message, the timestamp can be extracted from the BFD message, the timestamp is the time of entering the BFD message when the BFD message enters the switch equipment, namely, the time of entering the switch chip, and then the timestamp of the BFD message is recorded. Based on the principle, the FPGA records the time stamp of each received BFD message.

In addition, the FPGA can judge the current session state of the BFD message while analyzing a timestamp from each BFD message, if the BFD session represented by the BFD message is detected to be overtime, the session state represented by the BFD message is confirmed to be a down state, meanwhile, an interrupt event about the down state is reported to a CPU, and the corresponding relation between the timestamp of the BFD message and the down state is recorded; if the BFD session represented by the BFD message is not overtime, determining that the session represented by the BFD message is in an up state, and simultaneously recording the corresponding relation between the up state of the BFD message and the timestamp. Therefore, the FPGA can obtain the time stamp of each BFD message based on the BFD session and the session state represented by the time stamp.

On the basis, after the CPU receives the interrupt event, a plurality of timestamps which are recorded recently can be obtained from the FPGA. The actual number of the plurality of timestamps may be determined according to an actual situation, which aims to prevent the occurrence of a situation that the timestamp corresponding to the BFD message in the down state is covered, that is, the plurality of timestamps may include the timestamp in the BFD message corresponding to the down state. For example, the number of timestamps may be 5 timestamps, based on experience. For example, the detection interval of the BFD session is 3 × 10ms, and when the CPU receives a down event, the last 5 timestamps acquired from the FPGA are 20ms, 30ms, 40ms, 50ms, and 82ms, respectively, and 50ms is a timestamp extracted from the BFD message corresponding to the down state.

Optionally, each timestamp is located in a packet header of the corresponding BFD packet.

S103, the CPU extracts a first time stamp corresponding to the BFD message with the represented session state being a down state and a second time stamp which is later than the first time stamp from the plurality of latest time stamps.

Specifically, when recording the timestamp and the session state of each BFD packet, the FPGA may mark the timestamp only in the down state, and the timestamp corresponding to the up state is not marked, and then the FPGA records the timestamp according to the reception sequence of the BFD packets, that is, the timestamp arranged in the front is earlier than the timestamp arranged in the rear, so that after the timestamp is reported to the CPU, the CPU may identify the timestamp corresponding to the down state from the plurality of timestamps according to the mark, and record the timestamp as the first timestamp; a timestamp later than the first timestamp is then identified and noted as a second timestamp. Further, taking the above 5 time stamps as an example, it can be recognized that the first time stamp corresponding to the down state is 50ms, and the time stamp later than 50ms is 82ms, and is recorded as the second time stamp.

S104, judging whether the time interval between the second time stamp and the first time stamp is not less than a set session detection interval or not; if yes, go to step S105; if the determination result is negative, step S106 is executed.

In this step, the above 5 timestamps are also taken as an example for explanation, it can be confirmed that the time interval between the second timestamp 82ms and the first timestamp 50ms is 32ms, and 32ms is greater than the set detection interval of the session 3 × 10ms, so that the detection in the switch device is correct, and there is no message forwarding failure in the device switch, that is, step S105 is executed; in this embodiment, a message forwarding failure refers to a condition of congestion or packet loss in a message forwarding process in the switch device, and a message forwarding failure refers to a condition of normal message forwarding and no congestion or packet loss in the switch device.

Specifically, if the CPU obtains 5 timestamps from the FPGA: 20ms, 30ms, 40ms, 50ms (mark) and 60ms, the set detection interval of the session is still 3 × 10ms, it can be determined that the timestamp corresponding to the down state is 50ms, i.e. the first timestamp, the timestamp later than 50ms is 60ms, and 60ms is the timestamp corresponding to the up state, i.e. the second timestamp, based on which the CPU can determine that the time interval between the second timestamp 60ms and the first timestamp 50ms is 10ms, and 10ms is less than the set time interval of 30ms, it can be determined that there is a failure in the forwarding of the message in the switch device at this time, i.e. step S106 is executed, that is, the condition of congestion occurs in the forwarding process of the BFD message from port a to the FPGA in the switch device, that is, the rapid positioning of the congestion problem in the switch device is also realized, and then an alarm can be sent to investigate the forwarding congestion condition of the switch device at this end.

And S105, confirming that the message forwarding in the switch equipment has no fault.

S106, confirming that the message forwarding in the switch equipment has a fault.

By implementing the method shown in fig. 1, whether a message forwarding fault exists in the switch device can be quickly located, and an effective basis is provided for the correctness of the detection result.

Optionally, this embodiment further provides the following scheme for solving the problem of packet loss in the packet forwarding process in the switch device: that is, the monitoring function may be turned on for the BFD session, on the basis of which the following process shown in fig. 3 may be performed:

s301, after receiving the interrupt event, if the monitoring function for the BFD session is enabled, the CPU sends an Access Control List (ACL) corresponding to the BFD session to the switch chip.

Specifically, if the packet loss problem of the message forwarding in the switch device needs to be detected, a monitoring function for a certain BFD session may be started in advance. After receiving the interrupt event, if it is confirmed that the monitoring function has been turned on for the BFD session, an ACL for the BFD session may be transmitted to the switch chip.

Optionally, when the CPU sends the ACL to the switch chip, since the ACL issue time is relatively long, a new ACL for adding the statistical identifier (the ACL in step S301) may be issued to the switch chip first, where the priority of the ACL is higher than that of the ACL currently used in the switch chip, and the enable state of the new ACL is disable; and after the sending is successful, when the BFD session starts to be detected, enabling the new ACL in the switching chip, namely, changing the enabled state of the new ACL from disable to enable, so that the switching chip starts to perform message matching work by using the new ACL after the new ACL is enabled due to the higher priority of the new ACL.

S302, after receiving the ACL, the switching chip starts a message counting function, matches the subsequently received BFD messages and counts the first message quantity of the BFD messages matched with the ACL.

In this step, the switching chip starts a message statistic function while starting a new ACL, and then performs message matching on subsequent BFD messages entering from port a by using the ACL to obtain BFD messages matched with the new ACL, thereby obtaining a first message quantity of the matched BFD messages.

Optionally, when the switching chip starts the packet statistics function, the method further includes: and the switching chip sends a message counting starting instruction to the FPGA so as to trigger the FPGA to execute a message counting task. Similarly, when the message counting function is closed by the switching chip, a message counting end instruction is sent to the FPGA so that the FPGA stops executing the message counting task. Therefore, the synchronism of the message statistics of the switching chip and the FPGA is ensured, and the accuracy of the message counting is further ensured.

It should be noted that, when the switch chip suspends the message statistics task, the enable state of the new ACL is switched from enable to disable.

S303, the exchange chip adds a statistic identifier to each BFD message matched with the ACL, and forwards the BFD message added with the statistic identifier to the FPGA.

Specifically, after each BFD packet is matched by using a new ACL, the switching chip adds a statistical identifier to the matched BFD packet, and then sends the BFD packet added with the statistical identifier to the FPGA.

Optionally, when adding a statistical identifier to each matched BFD packet, the statistical identifier may be added to a packet header of the BFD packet, that is, the statistical identifier is added to a forwarding packet header of the BFD packet.

S304, the FPGA counts the received BFD messages with the counting identification to obtain the quantity of the second messages.

In this step, after receiving the BFD message, the FPGA may determine whether there is a statistical identifier in the BFD message, if so, the count is incremented by 1, otherwise, the count result remains unchanged.

Alternatively, step S304 may be implemented according to the following procedure: when receiving the message counting starting instruction, the FPGA starts to count the received BFD message with the counting identification; and when receiving the message counting ending instruction, the FPGA stops counting the BFD messages with the counting identification and obtains the second message quantity.

Specifically, after receiving a message statistics start instruction of the switch chip, the FPGA may start a counting function, for example, start a counter; analyzing the BFD message received from the exchange chip to judge whether the statistical identification can be analyzed, and if the statistical identification can be analyzed, adding 1 to the counter; and stopping the message unification task of the BFD message by the FPGA until a message counting ending instruction sent by the exchange chip is received, wherein the result of the counter is the second message quantity. The process can ensure the synchronization of the message statistics of the exchange chip and the two sides of the FPGA, thereby ensuring the accuracy of the statistical results of the messages on the two sides.

S305, the CPU obtains the first message quantity and the second message quantity;

in this step, after the switch chip and the FPGA obtain the first message quantity and the second message quantity respectively, the first message quantity and the second message quantity may be reported to the CPU respectively, and then the CPU may compare the first message quantity and the second message quantity.

S306, if the first message quantity is not equal to the second message quantity, determining that a fault exists in message forwarding in the switch.

In this step, if it is determined in step S305 that the first packet quantity is not equal to the second packet quantity, that is, there is a difference, it indicates that a packet loss occurs in the BFD packet during the packet forwarding process from port a to FPGA, and the session state of the BFD session is a down state due to the packet loss, that is, there is a problem of a packet forwarding failure in the switch device.

S307, if the CPU determines that the number of the first messages is equal to the number of the second messages, the CPU executes a step of acquiring a plurality of recorded latest timestamps from the FPGA.

In this step, when it is determined in step S305 that the number of the first messages is equal to the number of the second messages, it is determined that there is no packet loss currently in the switch device, and then, in combination with the implementation of the embodiment in fig. 1, it can be determined whether there is a congestion problem in the switch device, and if there is a congestion problem, it is determined that there is a message forwarding failure in the switch device, that is, whether there is a failure in the switch device due to a rapid location; if the switch equipment has no congestion, the switch equipment can confirm that no message forwarding fault exists in the switch equipment, and the fault condition of the local switch can be eliminated.

For better understanding of the embodiment, the following description will be given by taking an application scenario shown in fig. 4 as an example, in fig. 4, three layer networks of Switch a and Switch B are reachable, Switch a and Switch B establish a BFD session based on a BGP protocol, the BFD session has a shock condition within a certain period of time, when Switch a reports BFD session UP- > DOWN, a value of diag is 1, it is determined that Switch a detection is overtime, and the office point requires intervention to investigate whether Switch a has a problem, which causes a false alarm event in BFD detection. Based on this scenario, Switch a may implement the method for detecting the in-device packet forwarding failure according to the flow shown in fig. 1 and fig. 3, assuming that the preset session detection interval of the BFD session is 3 × 10ms, by implementing the method shown in fig. 3, after the CPU down of the BFD session, by collecting statistical information of the BFD session, that is, the first packet number counted by the Switch chip and the second packet number counted by the FPGA, it is found that the Switch chip counts 16777215 packets in total in the time period for which the statistical function is turned on, and the statistical count at the FPGA side is also 16777215 packets, which indicates that the packet loss problem does not occur on the device reporting the down event Switch a this time. In addition, the CPU can calculate whether the received BFD message of the peer device is accurate by implementing the method shown in fig. 1, that is, after the statistical time period is started, according to the transceiving interval configured by BFD, i.e., by collecting the first timestamp of the BFD session corresponding to the down state and the second timestamp later than the first timestamp, and then determining whether the time interval between the second timestamp and the first timestamp is not less than 3 × 10ms, if not less than 30ms, determining that there is no message forwarding congestion in the Switch a device, otherwise determining that there is a message forwarding congestion problem in the Switch a device, thereby implementing fast checking whether there is a BFD session detection abnormality caused by its own problem in the Switch a, and providing an effective basis for the accuracy of the detection result of this time; if there is no message forwarding failure in the Switch a device, the problem of the intermediate link and the Switch B device may be directly solved, the detection of the message forwarding in the Switch B device may refer to the detection method of Switch a, and the detection of the intermediate link may refer to the current process, which is not listed in detail herein.

Based on the same inventive concept, the application also provides an in-device message forwarding fault detection device corresponding to the in-device message forwarding fault detection method. The implementation of the device for detecting a message forwarding fault in equipment may refer to the above description of the method for detecting a message forwarding fault in equipment, and is not discussed here one by one.

Referring to fig. 5, fig. 5 is a device for detecting a message forwarding fault in a device according to an exemplary embodiment of the present application, which is applied to a switch device, where the switch device includes a central processing unit CPU, a switching chip, and a field programmable gate array FPGA, and the device includes:

a receiving module 501, configured to receive an interrupt event reported by the FPGA, where the interrupt event is triggered when a session state of a BFD session represented by a BFD packet is determined to be a down state after the BFD packet forwarded by the switch chip is received by the FPGA;

a first obtaining module 502, configured to obtain a plurality of recorded latest timestamps from the FPGA, where each timestamp is extracted from a corresponding BFD packet by the FPGA, and each timestamp is an entry time when the corresponding BFD packet enters the switch chip, and the switch chip writes the timestamp into the corresponding BFD packet;

an extracting module 503, configured to extract, from the latest timestamps, a first timestamp corresponding to a BFD packet whose represented session state is a down state, and extract a second timestamp later than the first timestamp;

a first determining module 504, configured to determine whether a time interval between the second timestamp and the first timestamp is not less than a set session detection interval;

a determining module 505, configured to determine that there is no failure in forwarding the message in the switch device if the determination result of the first determining module 504 is not smaller than the set session detection interval;

the determining module 505 is further configured to determine that there is a failure in forwarding the message in the switch device if the determination result of the first determining module 504 is smaller than the set session detection interval.

The receiving module 501, the first obtaining module 502, the extracting module 503, the first judging module 504, and the determining module 505 are all disposed in the CPU.

Optionally, the apparatus for detecting a failure of forwarding a message in a device provided in the embodiment of the present application further includes:

a first sending module (not shown in the figure), configured to send, after receiving the interrupt event, an access control list ACL corresponding to the BFD session to the switch chip if the monitoring function for the BFD session is enabled

A first message counting module (not shown in the figure) for starting a message counting function after receiving the ACL, and matching the subsequently received BFD messages to count the first message number of the BFD messages matched with the ACL;

an adding module (not shown in the figure) for adding a statistical identifier to each BFD packet matched with the ACL;

a second sending module (not shown in the figure), configured to forward the BFD packet to which the statistical identifier is added to the FPGA;

a second message counting module (not shown in the figure) for counting the received BFD messages with the counting identifiers to obtain a second message number;

a second obtaining module (not shown in the figure) configured to obtain the first packet quantity and the second packet quantity;

a second determining module (not shown in the figure) configured to determine whether the first packet quantity is equal to the second packet quantity;

the determining module 505 is further configured to determine that a failure exists in forwarding of the packet in the switch if the determination result of the second determining module is unequal;

the first obtaining module 502 is further configured to, if the determination results of the second determining modules are equal, execute a step of obtaining the recorded latest timestamps from the FPGA.

It should be noted that the first sending module is disposed in the CPU, the first packet counting module, the adding module, and the second sending module are all disposed in the switch chip, the second packet counting module is disposed in the FPGA, and the second obtaining module and the second determining module are disposed in the CPU.

Optionally, the apparatus for detecting a forwarding failure of a packet in a device provided in this embodiment further includes:

a third sending module (not shown in the figure), configured to send a message statistics start instruction to the FPGA when the first message statistics module starts a message statistics function;

the third sending module (not shown in the figure) is further configured to send a message statistics ending instruction to the FPGA when the switching chip closes the message statistics function;

the second packet counting module (not shown in the figure) is specifically configured to, when the packet counting start instruction is received, start counting the received BFD packets with the counting identifiers; and when the message counting ending instruction is received, stopping counting the BFD messages with the counting identification and obtaining the quantity of the second messages.

The third sending module is disposed in the switch chip.

Optionally, the statistical identifier is located in a packet header of the BFD packet.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The specific details of the implementation process of the functions and actions of each unit/module in the above device are the implementation processes of the corresponding steps in the above method, and are not described herein again.

For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are only schematic, where the units/modules described as separate parts may or may not be physically separate, and the parts displayed as units/modules may or may not be physical units/modules, may be located in one place, or may be distributed on multiple network units/modules. Some or all of the units/modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A method for detecting message forwarding fault in equipment is applied to switch equipment, wherein the switch comprises a Central Processing Unit (CPU), a switching chip and a Field Programmable Gate Array (FPGA), and the method comprises the following steps:

2. The method of claim 1, further comprising:

after receiving the interrupt event, if the monitoring function aiming at the BFD session is started, the CPU sends an Access Control List (ACL) corresponding to the BFD session to the exchange chip;

after receiving the ACL, the switching chip starts a message counting function and matches the subsequently received BFD messages so as to count the first message quantity of the BFD messages matched with the ACL;

the exchange chip adds a statistical identifier to each BFD message matched with the ACL, and forwards the BFD message added with the statistical identifier to the FPGA;

the FPGA counts the received BFD messages with the counting identification to obtain the quantity of second messages;

the CPU obtains the first message quantity and the second message quantity; if the first message quantity is determined to be not equal to the second message quantity, determining that a fault exists in message forwarding in the switch;

and if the CPU determines that the number of the first messages is equal to the number of the second messages, executing a step of acquiring a plurality of recorded latest timestamps from the FPGA by the CPU.

3. The method of claim 2, wherein when the switch chip starts a message statistic function, the method further comprises: the switching chip sends a message counting starting instruction to the FPGA;

when the message counting function of the exchange chip is closed, sending a message counting ending instruction to the FPGA;

then, the FPGA counts the received BFD messages with the statistical identifier to obtain a second message quantity, which includes:

when receiving the message counting starting instruction, the FPGA starts to count the received BFD message with the counting identification;

and when receiving the message counting end instruction, the FPGA stops counting the BFD messages with the counting identification and obtains the quantity of the second messages.

4. The method of claim 1, wherein each timestamp is located in a packet header of a corresponding BFD packet.

5. The method according to claim 2 or 3, wherein the statistical identifier is located in a packet header of the BFD packet.

6. The utility model provides an in-equipment message forwarding fault detection device which characterized in that, is applied to switch equipment, the switch includes central processing unit CPU, switching chip and field programmable gate array FPGA, the device includes:

a determining module, configured to determine that there is no failure in forwarding the message in the switch device if the determination result of the first determining module is not smaller than the set session detection interval;

7. The apparatus of claim 6, further comprising:

a first sending module, configured to send, to the switch chip, an access control list ACL corresponding to the BFD session if a monitoring function for the BFD session is enabled after the interrupt event is received

The first message counting module is used for starting a message counting function after the ACL is received, matching the subsequently received BFD messages and counting the first message quantity of the BFD messages matched with the ACL;

the adding module is used for adding a statistical identifier to each BFD message matched with the ACL;

the second sending module is used for forwarding the BFD message added with the statistical identifier to the FPGA;

the second message counting module is used for counting the received BFD messages with the counting identifiers to obtain the quantity of the second messages;

a second obtaining module, configured to obtain the first packet quantity and the second packet quantity;

the second judging module is used for judging whether the first message quantity is equal to the second message quantity;

the determining module is further configured to determine that a failure exists in forwarding of the packet in the switch if the determination result of the second determining module is unequal;

the first obtaining module is further configured to execute the step of obtaining the recorded latest timestamps from the FPGA if the determination results of the second determining module are equal to each other.

8. The apparatus of claim 7, further comprising:

the third sending module is used for sending a message counting starting instruction to the FPGA when the first message counting module starts a message counting function;

the third sending module is further configured to send a message statistics ending instruction to the FPGA when the switching chip closes the message statistics function;

the second message counting module is specifically configured to, when the message counting start instruction is received, start counting the received BFD messages with the counting identifiers; and when the message counting ending instruction is received, stopping counting the BFD messages with the counting identification and obtaining the quantity of the second messages.

9. The apparatus of claim 6, wherein each timestamp is located in a packet header of a corresponding BFD packet.

10. The apparatus according to claim 7 or 8, wherein the statistical identifier is located in a packet header of a BFD packet.