CN113054035A - Thin film transistor, preparation method thereof, display substrate and display device - Google Patents

Thin film transistor, preparation method thereof, display substrate and display device Download PDF

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Publication number
CN113054035A
CN113054035A CN202110268983.7A CN202110268983A CN113054035A CN 113054035 A CN113054035 A CN 113054035A CN 202110268983 A CN202110268983 A CN 202110268983A CN 113054035 A CN113054035 A CN 113054035A
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region
carrier injection
electrode
thin film
film transistor
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Inventor
朱磊
李志勇
杨润洲
胡伟
税守坚
薛锐
周宇
王春雷
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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Priority to CN202110268983.7A priority Critical patent/CN113054035A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Thin Film Transistor (AREA)

Abstract

A thin film transistor and a preparation method thereof, a display substrate and a display device are provided, the thin film transistor comprises an active layer, a gate electrode, a source electrode, a drain electrode and a carrier injection electrode which are arranged on a substrate, the active layer comprises a source region, a drain region, a channel region and a carrier injection region, the source electrode is electrically connected to the source region, the drain region is electrically connected to the drain region, the carrier injection region is electrically connected to the carrier injection region, and the polarity of the carrier injection region is different from that of the source region and the drain region. According to the thin film transistor provided by the embodiment of the disclosure, carriers are injected into a channel through the carrier injection region, so that the degradation of a device is inhibited, and the service life of the device is prolonged.

Description

Thin film transistor, preparation method thereof, display substrate and display device
Technical Field
The present disclosure relates to but not limited to display technologies, and in particular, to a thin film transistor, a method for fabricating the same, a display substrate, and a display device.
Background
In flat panel display, Low Temperature Poly-Silicon (LTPS) Thin Film Transistors (TFTs) have the advantages of high electron mobility, Low power consumption, fast response, flexible display, and the like, and have gradually become the mainstream choice. And the quality of the TFT performance directly affects the display quality. In actual use, the variation in gate electrode voltage tends to cause hot carrier degradation of the TFT, thereby deteriorating the TFT.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the disclosure provides a thin film transistor, a preparation method thereof, a display substrate and a display device, and the performance of the thin film transistor is improved.
In one aspect, embodiments of the present disclosure provide a thin film transistor including an active layer, a gate electrode, a source electrode, a drain electrode, and a carrier injection electrode disposed on a substrate, the active layer including a source region, a drain region, a channel region, and a carrier injection region, the source electrode being electrically connected to the source region, the drain region being electrically connected to the drain region, the carrier injection region being electrically connected to the carrier injection region, the carrier injection region being of a different polarity than the source region and the drain region.
In an exemplary embodiment, a side of the channel region close to the gate electrode is a first side, the source region is disposed at a second side of the channel region, the drain region is disposed at a third side of the channel region, and the carrier injection region is disposed at least one side of the channel region except the first side, the second side, and the third side.
In an exemplary embodiment, the carrier injection electrode is disposed in the same layer as the source and drain electrodes; or the carrier injection electrode is arranged in a different layer from the source electrode and the drain electrode.
In an exemplary embodiment, the source region is heavily doped with a first polarity, the drain region is heavily doped with a first polarity, and the carrier injection region is heavily doped with a second polarity.
In an exemplary embodiment, the gate electrode is connected to a first power supply terminal, the carrier injection electrode is connected to a second power supply terminal, the thin film transistor is an N-type thin film transistor, and when the voltage of the first power supply terminal is in a falling edge period, the voltage of the second power supply terminal is a ground voltage or a positive voltage; or, the thin film transistor is a P-type thin film transistor, and when the voltage of the first power supply terminal is in a rising edge period, the voltage of the second power supply terminal is a ground voltage or a negative voltage.
In another aspect, the present disclosure provides a display substrate including the thin film transistor.
In another aspect, an embodiment of the present disclosure provides a display device, including the above display substrate.
In another aspect, an embodiment of the present disclosure provides a method for manufacturing a thin film transistor, including:
forming an active layer and a gate electrode on a substrate, wherein the active layer comprises a source region, a drain region, a channel region and a carrier injection region, and the carrier injection region has different polarities from the source region and the drain region;
forming a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and a carrier injection electrode electrically connected to the carrier injection region.
In an exemplary embodiment, forming the active layer on the substrate includes:
forming a polysilicon pattern on a substrate;
doping the polysilicon pattern with a first polarity to form a source region and a drain region;
and carrying out second polarity doping on the polysilicon pattern to form a carrier injection region.
In an exemplary embodiment, the forming the source electrode, the drain electrode, and the carrier injection electrode includes:
and depositing a metal film, and forming the source electrode, the drain electrode and the carrier injection electrode by a one-time composition process.
The embodiment of the application comprises a thin film transistor and a preparation method thereof, a display substrate and a display device, wherein the thin film transistor comprises an active layer, a gate electrode, a source electrode, a drain electrode and a carrier injection electrode which are arranged on a substrate, the active layer comprises a source region, a drain region, a channel region and a carrier injection region, the source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, the carrier injection region is electrically connected to the carrier injection region, and the carrier injection region, the source region and the drain region are different in polarity. According to the thin film transistor provided by the embodiment of the disclosure, carriers are injected into a channel through the carrier injection region, so that the degradation of a device is inhibited, and the service life of the device is prolonged.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic diagram of a thin film transistor provided in an embodiment of the present disclosure;
fig. 2 is a front view of the thin film transistor shown in fig. 1;
FIG. 3 is a side view of the thin film transistor shown in FIG. 1;
FIG. 4 is a top view of the TFT of FIG. 1;
fig. 5 is a schematic diagram of a carrier injection region injecting holes into a channel region in a thin film transistor provided in an exemplary implementation;
FIG. 6 is a cross-sectional view after patterning a polysilicon active layer in an exemplary embodiment;
FIG. 7 is another cross-sectional view after patterning the polysilicon active layer in an exemplary embodiment;
FIG. 8 is a top view of an exemplary embodiment after patterning a polysilicon active layer;
FIG. 9 is a cross-sectional view after forming a second insulating layer pattern in an exemplary embodiment;
FIG. 10 is another cross-sectional view after forming a second insulating layer in an exemplary embodiment;
FIG. 11 is a top view of an exemplary embodiment after forming a gate electrode pattern;
fig. 12 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, the embodiments of the present disclosure are not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or numerical values shown in the drawings.
The ordinal numbers such as "first", "second", "third", etc., in this disclosure are provided to avoid confusion among the constituent elements, and do not indicate any order, number, or importance.
In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the disclosure are not limited thereto, and may be replaced as appropriate.
In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.
In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.
In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other.
In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.
In the present disclosure, "film" and "layer" may be interchanged with one another. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".
In the LTPS TFT, the gate voltage is usually an alternating voltage, and in long-term use, the N-type TFT is liable to suffer TFT deterioration due to the hot carrier effect. In current practical circuit designs, appropriate circuit compensation techniques are typically employed to compensate for characteristic drift during cancellation, such as 4T1C, 6T1C, 7T1C, and the like. Increasing the number of TFTs in the compensation circuit can achieve more accurate compensation, but at the same time, the complexity of the driving circuit increases and the power consumption increases. With the development of display technology towards high definition, high image quality and high refresh rate, the operating frequency of the pixel driving circuit responding to the display technology is higher, the degradation of the device is more serious, and the compensation circuit can only alleviate the degradation of the device to a certain extent. In the embodiments of the present disclosure, TFT degradation is suppressed from the device level, the lifetime of the device can be increased, and the complexity of the compensation circuit can be reduced.
The embodiment of the disclosure provides a thin film transistor, and a carrier injection electrode is added on the basis of a gate electrode, a source electrode and a drain electrode. The carrier injection region corresponding to the carrier injection electrode can inject carriers into the channel region when the voltage of the gate electrode changes, the carriers are diffused to the source region and the drain region, the unbalanced state of the channel is eliminated, and the dynamic hot carrier deterioration of the device is inhibited, so that the effect of inhibiting the degradation of the device is achieved, and the service life of the device is prolonged.
Fig. 1 is a schematic perspective view of a thin film transistor provided in an embodiment of the present disclosure. Fig. 2 is a front view of the thin film transistor shown in fig. 1; fig. 3 is a side view of the thin film transistor shown in fig. 1, and fig. 4 is a top view of the thin film transistor shown in fig. 1. Fig. 1 is a schematic diagram, which only shows a part of the film layers of the thin film transistor, and a part of the film layers are omitted. As shown in fig. 1, 2, 3 and 4, a thin film transistor provided by an embodiment of the present disclosure includes: the light emitting diode comprises a substrate 1, a light shielding layer 2 arranged on the substrate 1, a buffer layer 3 arranged on one side of the light shielding layer 2 far away from the substrate 1, an active layer arranged on one side of the buffer layer 3 far away from the substrate 1, a first insulating layer 7 arranged on one side of the active layer far away from the substrate 1, a gate electrode 8 arranged on one side of the first insulating layer 7 far away from the substrate 1, a second insulating layer 9 arranged on one side of the gate electrode 8 far away from the substrate 1, a drain electrode 10 arranged on one side of the second insulating layer 9 far away from the substrate 1, a source electrode 11 and a carrier injection electrode 12, wherein the active layer can comprise a source and drain region 4, a channel region 5 and a carrier injection region 6, the source and drain region 4 can comprise a source region 42 and a drain region 41, the channel region 5 is arranged between the source region 42 and the drain region 41, and the drain electrode 10 is connected to the drain region 41 through, the source electrode 11 is connected to the source region 42 through another first via 13, and the carrier injection electrode 12 is connected to the carrier injection region 6 through a second via 14. The active layer may be a polysilicon active layer, but is not limited thereto. The carrier injection region 6 is of a different polarity than the source and drain regions 42, 41. The source region 42 and the drain region 41 are of the same polarity.
The first insulating layer 7 is also referred to as a gate insulating layer, and the second insulating layer 9 is also referred to as an interlayer dielectric layer.
The polarity refers to P type or N type. The source region 42 and the drain region 41 may be of a first polarity and the carrier injection region may be of a second polarity, for example, in an N-type thin film transistor, the source region 42 and the drain region 41 may be N-type doped and the carrier injection region 6 may be P-type doped. In the P-type thin film transistor, the source region 42 and the drain region 41 may be doped P-type, and the carrier injection region 6 may be doped N-type.
The embodiments of the present disclosure are described taking an N-type TFT device as an example, and are referred to as a four-terminal N-type TFT device. In a four-terminal N-type TFT device, the normal work of the device cannot be influenced by the introduction of a carrier injection electrode, when the voltage of a gate electrode is at a falling edge, a P + N junction formed by the P-type carrier injection electrode and an intrinsic conductive channel is forward biased, a hole can be injected into a channel region by the carrier injection electrode, and the injected hole is diffused to a source electrode and a drain electrode, so that the effect of inhibiting the degradation of the device is achieved, and the service life of the device is prolonged.
In an exemplary embodiment, the source region 42 and the drain region 41 may include heavily doped regions, the carrier injection region may include heavily doped regions, for example, in an N-type thin film transistor, the source region 42 and the drain region 41 may be N + doped regions, and the carrier injection region may be a P + doped region; in the P-type thin film transistor, the source region 42 and the drain region 41 may be P + doped regions, and the carrier injection region may be an N + doped region.
In another exemplary embodiment, the source region 42 and the drain region 41 may include a heavily doped region and a lightly doped region (a region with a doping concentration one order of magnitude lower than that of the heavily doped region), for example, in an N-type thin film transistor, the source region 42 may include an N + doped region and an N-doped region, the N-doped region being located between the N + doped region and the channel region; the drain region 41 may include an N + doped region and an N-doped region, the N-doped region being located between the N + doped region and the channel region. The arrangement of the lightly doped region is equivalent to the fact that a large resistor is connected in series between the source electrode, the drain electrode and the channel, so that a horizontal electric field of the channel is reduced, hot carriers generated by impact ionization caused by acceleration of the electric field are reduced, and leakage current can be effectively inhibited. When the source region 42 and the drain region 41 are not provided with the lightly doped region, the process can be reduced, and the cost can be reduced.
In an exemplary embodiment, a side of the channel region 5 close to the gate electrode 8 is referred to as a first side, the source region 42 is disposed at a second side of the channel region 5, the drain region 41 is disposed at a third side of the channel region 5, and the carrier injection region 6 may be disposed at least one side of the channel region 5 except the first side, the second side, and the third side. For example, as shown in fig. 1, the thin film transistor may be a top gate type thin film transistor, and the gate electrode 8 is disposed on the upper side (first side) of the channel region 5. The source region 42 and the drain region 41 are respectively located at the left and right sides (second side, third side) of the channel region, and the carrier injection region 6 may be disposed at the front side of the channel region 5. In another embodiment, the carrier injection region 6 may be disposed at a rear side or a lower side of the channel region 5, or the carrier injection region 6 may be disposed at one or more of a front side, a rear side, and a lower side of the channel region 5. The front side and the rear side are opposite to each other.
In an exemplary embodiment, the thin film transistor may be a bottom gate thin film transistor, and when the gate electrode 8 is located on a side of the channel region 5 close to the substrate, that is, the gate electrode 8 is located on a lower side of the channel region 5, the carrier injection region 6 may be disposed on one or more of a front side, a rear side, and an upper side of the channel region 5.
In an exemplary embodiment, the substrate 1 may be a rigid substrate, or may be a flexible substrate or a substrate of other nature. The material of the rigid substrate may be, for example, glass or quartz. The material of the flexible substrate may be, for example, Polyimide (PI), polyethylene terephthalate (PET), Triacetyl Cellulose (TAC), Cyclic Olefin Polymer (COP), or Polyimide (CPI), or other suitable materials, which is not limited in the embodiments of the present disclosure.
In an exemplary embodiment, the material of the first and second insulating layers 7 and 9 may be, for example, silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al2O3), aluminum nitride (AlN), or the like. The gate electrode may be made of, for example, aluminum (Al), copper (Cu), or the like.
In an exemplary embodiment, an orthographic projection of the active layer is located within an orthographic projection of the light shielding layer 2 on a plane parallel to the substrate 1. Since the channel region 5 of the thin film transistor is made of a semiconductor material, and the performance of the semiconductor material is unstable after being irradiated by light (e.g., ambient light), the thin film transistor is subjected to negative drift, that is, the threshold voltage of the thin film transistor is changed, thereby affecting the operating performance of the thin film transistor. The light shielding layer 2 can shield the active layer, so that the active layer is not affected by light, thereby improving the working performance of the thin film transistor.
In an exemplary embodiment, the display substrate may not have the light shielding layer 2, such as an Organic Light Emitting Diode (OLED) display device, and the light shielding layer 2 may not be provided.
In an exemplary embodiment, the material of the light shielding layer 2 may be, for example, a metal material, and the metal material may be, for example, an opaque metal or alloy such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mu), etc.; or may be other opaque materials, which are not limited in this disclosure.
In an exemplary embodiment, the material of the buffer layer 3 may be, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (si (on) x), or the like. The buffer layer 3 may planarize the light-shielding layer 2; and the buffer layer 3 can prevent the light-shielding layer 2 from contacting the active layer.
In an exemplary embodiment, the active layer may be a polysilicon active layer, but is not limited thereto, and may be other types of active layers, such as an active layer made of amorphous silicon, zinc oxynitride ZnON, indium zinc tin oxide IZTO, or the like.
In an exemplary embodiment, the active layer is formed of a metal oxideThe layer may be formed by thin film doping of the active layer. Taking an N-type thin film transistor as an example, after forming a polysilicon pattern, a pentavalent element may be doped to form an N-type source region 42 and a drain region 41, and a trivalent element may be doped to form a P-type carrier injection region 6, for example, B may be doped3+A P-type carrier injection region 6 is formed. Alternatively, trivalent elements may be doped to form the P-type carrier injection region 6, and then pentavalent elements may be doped to form the N-type source region 42 and the drain region 41.
In an exemplary embodiment, the carrier injection electrode 12 may be disposed in the same layer as the source electrode 11 and the drain electrode 10, or may be disposed in a different layer.
In an exemplary embodiment, the source electrode 11, the drain electrode 10, and the carrier injection electrode 12 may be made of a metal material, such as Ag, Cu, Al, Mo, or the like, or an alloy material of the above metals, such as AlNd, MoNb, or the like, and may have a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, or the like.
In an exemplary embodiment, the state of the carrier injection pole 12 can be floating, grounded, negatively biased, weakly positively biased. The gate electrode 8 is connected with a first power supply end, the carrier injection electrode 12 is connected with a second power supply end, the thin film transistor is an N-type thin film transistor, and when the voltage of the first power supply end is in a falling edge period, the voltage of the second power supply end is the ground voltage or is greater than the ground voltage; at this time, the deterioration of the carrier injection electrode can be more effectively suppressed, or the thin film transistor is a P-type thin film transistor, and when the voltage of the first power supply terminal is in the rising edge period, the voltage of the second power supply terminal is the ground voltage or less. In this case, the carrier injecting electrode can more effectively suppress deterioration.
For LTPS TFTs, the gate voltage is an alternating voltage, and N-type TFTs are susceptible to degradation due to hot carrier effects. When the gate voltage is reduced, the conductive channel is in a hole accumulation state, but the intrinsic polysilicon channel can only generate holes through thermal excitation, and the thermal excitation time of the holes is longer and is far longer than the time of the falling edge of the gate, so that the channel is in an unbalanced depletion state. In the time of the falling edge of the gate electrode, the potential of the channel region is at a negative potential, so that a PN + junction of a drain terminal is in a reverse bias state, a depletion region expands towards the channel region through ionization emission of a defect state, and carriers emitted by deep level defect state ionization are exposed in a strong electric field of the depletion region and form hot carriers through acceleration of the electric field, so that the dynamic hot carriers generated during the TFT are deteriorated.
In the four-terminal TFT device, a P + doped carrier injection region forms a P + N junction with an intrinsic channel, a potential of the channel region is at a negative potential during a time of a falling edge of a gate electrode voltage, when a carrier injection electrode is grounded or weakly biased, the P + N junction is in a forward bias state, the carrier injection region can inject holes into the channel region, and the injected holes diffuse to a source region 42 and a drain region 41, so as to eliminate a non-equilibrium state of the channel region and suppress dynamic hot carrier deterioration of the device, as shown in fig. 5, S (N +) is an N + type source region 42, and D (N +) is an N + type drain region 41. Holes and electrons exist in the carrier injection region 6. When the carrier injection pole is suspended, the P + N junction cannot inject holes, so that hot carrier deterioration cannot be suppressed. When the carrier injection electrode is a negative voltage, holes can be instantaneously injected only when the potential of the channel region is more negative than the voltage of the carrier injection electrode. Therefore, carrier injection with a very weak positive bias is more effective in suppressing deterioration than a negative bias.
The structure of the thin film transistor of this embodiment is explained below by the manufacturing process of the thin film transistor. The "patterning process" in the embodiments of the present disclosure includes depositing a film, coating a photoresist, exposing through a mask, developing, etching, and stripping the photoresist. The deposition may employ any one or more selected from sputtering, evaporation and chemical vapor deposition, the coating may employ any one or more selected from spray coating and spin coating, and the etching may employ any one or more selected from dry etching and wet etching. "thin film" refers to a layer of a material deposited or coated onto a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. When the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The "a and B being disposed in the same layer" in the embodiments of the present disclosure means that a and B are simultaneously formed by the same patterning process.
The preparation process of the thin film transistor comprises the following steps:
depositing a first metal film on the substrate, and forming a light shielding layer 2 by patterning; depositing a buffer layer film, and forming a buffer layer 3 by composition;
depositing an amorphous silicon film, performing laser annealing treatment on the amorphous silicon film to generate a polycrystalline silicon film, and patterning the polycrystalline silicon film to form a polycrystalline silicon pattern; the laser can adopt XeCl laser, ArF laser, KrF laser, XeF laser and the like, the excimer laser generates laser beams in an ultraviolet band, the amorphous silicon film is irradiated by short pulse laser beams in the ultraviolet band, and the amorphous silicon film can rapidly absorb laser energy to melt and recrystallize. In another embodiment, the amorphous silicon pattern can be formed by patterning first, and then the polysilicon pattern can be generated by laser annealing treatment;
doping the polysilicon pattern, including: coating photoresist on the substrate with the polysilicon pattern, exposing and developing, forming an unexposed region in a channel region and a carrier injection region, carrying out first ion injection treatment, carrying out N-type ion injection on the N-type thin film transistor, wherein the N-type ions can adopt phosphorus ions to form an N + doped source region 42 and a drain region 41, and stripping the photoresist; a channel region 5 is arranged between the source region 42 and the drain region 41;
coating photoresist on the above structure, exposing and developing to form unexposed region in the channel region, source region 42 and drain region 41, performing second ion implantation to perform P-type ion implantation for N-type TFT, wherein the P-type ion can be B3+Forming a P + doped carrier injection region 6, and stripping the photoresist to form a polysilicon pattern including a source region 42, a drain region 41, and the carrier injection region 6; as shown in fig. 6, 7 and 8.
A first insulating film and a gate metal film are deposited in sequence on the aforementioned structure, and a first insulating layer 7 and a gate electrode 8 are formed by a patterning process. Depositing a second insulating film, patterning to form a second insulating layer 9, wherein the second insulating layer 9 is provided with a first via hole 13 and a second via hole 14, the second insulating layer 9 and the first insulating layer 7 in the first via hole 13 are etched away to expose the source region 42 and the drain region 41, and the second insulating layer 9 and the first insulating layer 7 in the second via hole 14 are etched away to expose the carrier injection region 6; as shown in fig. 9, 10 and 11.
Depositing a second metal film, and patterning to form a source electrode 11, a drain electrode 10 and a carrier injection pole 12, wherein the source electrode 11 is electrically connected with the source region 42 through a first via 13, the drain electrode 10 is electrically connected with the drain region 41 through another first via 13, and the carrier injection pole 12 is electrically connected with the carrier injection region 6 through a second via 14, thereby forming the LTPS thin film transistor, as shown in fig. 2, 3 and 4.
According to the display substrate provided by the embodiment, by adding the carrier injection region and the carrier injection electrode, the carrier injection region corresponding to the carrier injection electrode can inject carriers into the channel region when the gate voltage changes, and the carriers diffuse to the source region 42 and the drain region 41, so that the unbalanced state of the channel is eliminated, the dynamic hot carrier deterioration of the device is inhibited, the effect of inhibiting the device degradation is achieved, and the service life of the device is prolonged.
The preparation process disclosed by the embodiment of the disclosure can be realized by utilizing the existing mature preparation equipment, the improvement on the existing process is small, the preparation process can be well compatible with the LTPS preparation process, the process is simple to realize and easy to implement, the production efficiency is high, the production cost is low, and the yield is high.
The embodiment of the disclosure provides a display substrate, which comprises the thin film transistor. The display substrate provided by the embodiment uses the thin film transistor, and the thin film transistor for compensation can be reduced due to the improved performance of the thin film transistor, so that the complexity of a compensation circuit can be reduced.
The embodiment of the disclosure also provides a display device, which includes the display substrate of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The display device may be a liquid crystal display, an organic light emitting diode display, or the like.
Fig. 12 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 12, a method for manufacturing a thin film transistor provided in the embodiment of the present disclosure may include:
step 1201, forming an active layer and a gate electrode on a substrate, wherein the active layer comprises a source region, a drain region, a channel region and a carrier injection region, and the carrier injection region has different polarities from the source region and the drain region;
in an exemplary embodiment, the active layer may be formed first, and then the gate electrode may be formed; alternatively, the gate electrode may be formed first, and then the active layer may be formed.
Step 1202, forming a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and a carrier injector electrically connected to the carrier injection region.
In an exemplary embodiment, forming the active layer on the substrate may include:
patterning the substrate to form a polysilicon pattern;
doping the polysilicon pattern with a first polarity to form a source region and a drain region;
and carrying out second polarity doping on the polysilicon pattern to form a carrier injection region.
In an exemplary embodiment, the source region and the drain region may be formed first, and then the carrier injection region may be formed; alternatively, the carrier injection region may be formed first, and then the source and drain regions may be formed.
In an exemplary embodiment, the forming of the source electrode, the drain electrode, and the carrier injection electrode may include:
and depositing a metal film, and forming the source electrode, the drain electrode and the carrier injection electrode by a one-time composition process.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A thin film transistor comprising an active layer, a gate electrode, a source electrode, a drain electrode and a carrier injection electrode disposed on a substrate, the active layer comprising a source region, a drain region, a channel region and a carrier injection region, the source electrode being electrically connected to the source region, the drain electrode being electrically connected to the drain region, the carrier injection region being electrically connected to the carrier injection region, the carrier injection region being of a different polarity than the source and drain regions.
2. The thin film transistor according to claim 1, wherein a side of the channel region close to the gate electrode is a first side, the source region is disposed at a second side of the channel region, the drain region is disposed at a third side of the channel region, and the carrier injection region is disposed at least at one side of the channel region other than the first side, the second side, and the third side.
3. The thin film transistor according to claim 1, wherein the carrier injection electrode is provided in the same layer as the source and drain electrodes; or the carrier injection electrode, the source electrode and the drain electrode are arranged in different layers.
4. The thin film transistor of claim 1, wherein the source region is heavily doped with a first polarity, the drain region is heavily doped with a first polarity, and the carrier injection region is heavily doped with a second polarity.
5. The thin film transistor according to any one of claims 1 to 4, wherein the gate electrode is connected to a first power supply terminal, the carrier injection electrode is connected to a second power supply terminal, the thin film transistor is an N-type thin film transistor, and when the voltage of the first power supply terminal is in a falling edge period, the voltage of the second power supply terminal is a ground voltage or a positive voltage; or, the thin film transistor is a P-type thin film transistor, and when the voltage of the first power supply terminal is in a rising edge period, the voltage of the second power supply terminal is a ground voltage or a negative voltage.
6. A display substrate comprising the thin film transistor according to any one of claims 1 to 5.
7. A display device comprising the display substrate according to claim 6.
8. A method for manufacturing a thin film transistor includes:
forming an active layer and a gate electrode on a substrate, wherein the active layer comprises a source region, a drain region, a channel region and a carrier injection region, and the carrier injection region has different polarities from the source region and the drain region;
forming a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, and a carrier injection electrode electrically connected to the carrier injection region.
9. The method of manufacturing a thin film transistor according to claim 8, wherein the forming an active layer on a substrate comprises:
forming a polysilicon pattern on a substrate;
doping the polysilicon pattern with a first polarity to form the source region and the drain region;
and carrying out second polarity doping on the polysilicon pattern to form the carrier injection region.
10. The method for manufacturing a thin film transistor according to claim 8 or 9, wherein the forming of the source electrode, the drain electrode, and the carrier injection electrode includes:
and depositing a metal film, and forming the source electrode, the drain electrode and the carrier injection electrode by a one-time composition process.
CN202110268983.7A 2021-03-12 2021-03-12 Thin film transistor, preparation method thereof, display substrate and display device Pending CN113054035A (en)

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