CN113053921B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN113053921B CN113053921B CN202110272319.XA CN202110272319A CN113053921B CN 113053921 B CN113053921 B CN 113053921B CN 202110272319 A CN202110272319 A CN 202110272319A CN 113053921 B CN113053921 B CN 113053921B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/17—Passive-matrix OLED displays
- H10K59/179—Interconnections, e.g. wiring lines or terminals
Abstract
The application provides an array substrate, display panel and display device, the array substrate includes: a substrate base plate; the grid layer is arranged on the substrate and used for forming a scanning line; the source-drain layer is arranged on the gate layer and is used for forming a plurality of first power supply voltage lines and a plurality of second power supply voltage lines; each first power supply voltage line extends along a first direction, a plurality of first power supply voltage lines and a plurality of second power supply voltage lines are distributed in a net shape, each second power supply voltage line extends along a second direction, and the first direction and the second direction are crossed. This application through inciting somebody to action first mains voltage line with second mains voltage line all in the preparation forms in the source drain electrode layer, has avoided first mains voltage line and second mains voltage line to differ greatly because the impedance that the material difference of different retes leads to, thereby improves the impedance homogeneity of first mains voltage line and second mains voltage line.
Description
Technical Field
The application relates to the technical field of display devices, in particular to an array substrate, a display panel and a display device.
Background
Since a power voltage line (VDD) on a display panel (e.g., an active matrix organic light emitting diode panel) is connected to each pixel, a current flows through the power voltage line when light emission is driven. Considering that the power voltage line itself has impedance, there will be voltage drop, resulting in difference in VDD of each pixel, resulting in current difference between different pixels. As a result, the current flowing through the OLED is different, the brightness is also different, and the AMOLED panel is not uniform.
In order to ensure the uniformity of the panel brightness, the power voltage line VDD in the prior art uses a large-line width, double-layer metal to reduce the internal resistance voltage drop (RC loading) and power voltage drop (IR drop) effects, and uses a mesh structure (mesh) to improve the voltage uniformity in the whole plane.
Because the power voltage lines of the mesh structure are made of different metal layers and are generally respectively manufactured in the gate layer and the source drain layer, however, the gate layer is generally made of high-impedance metal, the impedance of the gate layer is about 10 times of that of the source drain layer, that is, the impedance difference between the power voltage lines of the mesh structure is large, so that the problem of uneven impedance still exists in the whole panel, and the brightness of the AMOLED panel is also uneven.
Disclosure of Invention
The application provides an array substrate, a display panel and a display device to solve the problem that a power voltage line of the array substrate has uneven impedance.
In one aspect, the present application provides an array substrate, including:
a substrate base plate;
the source-drain layer is arranged on the substrate and used for forming a data line, a plurality of first power supply voltage lines and a plurality of second power supply voltage lines;
the first power supply voltage lines extend along a first direction, the second power supply voltage lines extend along a second direction, the first direction and the second direction are crossed, and the orthographic projections of the first power supply voltage lines and the second power supply voltage lines on the substrate are distributed in a net shape.
In one possible implementation manner of the present application, the gate layer includes a first gate layer and a second gate layer, and the second gate layer is disposed on the first gate layer;
the first gate layer is used for forming a scanning line, and the scanning line extends along the first direction;
the second gate layer is used for forming a first reset signal line extending along the first direction.
The gate layer comprises a first gate layer and a second gate layer, the first gate layer is arranged on the source drain layer, and the second gate layer is arranged on the first gate layer;
the first gate layer is used for forming the scanning line, and the scanning line extends along the first direction;
the second gate layer is used for forming a first reset signal line extending along the first direction.
In a possible implementation manner of the present application, the source drain layer is further configured to form a data line, the data line is disposed along a first direction, the data line crosses the second power voltage line, and a crossing portion of the data line and the second power voltage line is disposed at an interval.
In one possible implementation manner of the present application, the source/drain layer is further configured to form a data line, the second power voltage line includes a first sub-voltage line and a second sub-voltage line, and the array substrate further includes:
the first insulating layer is arranged between the second gate layer and the source drain layer, and a first through hole and a second through hole which penetrate through the first insulating layer are formed in the first insulating layer;
the first sub-voltage line is filled in the first via hole;
the first via hole and the second via hole are respectively arranged at two sides of the data line, and the second sub-voltage line is filled in the second via hole;
the first via hole and the second via hole are respectively communicated with the second gate layer, and the first sub-voltage line is electrically connected with the second sub-voltage line through the second gate layer.
In one possible implementation manner of the present application, the source drain layer is further configured to form a second reset signal line, the second reset signal line extends along the first direction, the second reset signal line and the first power voltage line are spaced apart from each other in the second direction, the second reset signal line crosses the second power voltage line, and the second reset signal line and the crossing portion of the second power voltage line are spaced apart from each other.
In a possible implementation manner of the present application, the second reset signal line includes a first sub-signal line and a second sub-signal line, and a third via hole and a fourth via hole are further disposed on the first insulating layer;
the third via hole penetrates through the first insulating layer, and the first sub-signal line is filled in the third via hole;
the fourth via hole penetrates through the first insulating layer, the third via hole and the fourth via hole are respectively arranged on two sides of the second power supply voltage line, and the second sub-signal line is filled in the fourth via hole;
the third via hole and the fourth via hole are respectively communicated with the second gate layer, and the second sub-signal line are electrically connected through the second gate layer.
In a possible implementation manner of the present application, the first gate layer is further used for forming a capacitor upper electrode plate, the second gate layer is further used for forming a capacitor lower electrode plate, and the capacitor upper electrode plate and the capacitor lower electrode plate are opposite to each other in arrangement.
In one possible implementation of the present application, the first power voltage line and the second power voltage line are made of a three-layer metal laminate of aluminum, titanium, and aluminum.
In one possible implementation manner of the present application, the array substrate further includes:
and the active layer is arranged between the substrate and the gate layer and is used for forming a signal line, and the adjacent data line and the first power supply voltage line are electrically connected through the signal line.
In a possible implementation manner of the present application, a plurality of first reset signal lines are disposed on the array substrate at intervals, and every two first reset signal lines are connected to each other through the signal lines.
On the other hand, the application also provides a display panel which comprises the array substrate.
On the other hand, the application also provides a display device which comprises the display panel.
The application provides a pair of array substrate, display panel and display device, through be the basis of cross arrangement at first mains voltage line and second mains voltage line, will first mains voltage line with second mains voltage line all in preparation formation in the source drain layer compares among the prior art first mains voltage line and second mains voltage line preparation formation in the rete of difference respectively, has avoided first mains voltage line and second mains voltage line because the different impedance that leads to of material of different rete differs great, thereby improves the impedance homogeneity of first mains voltage line and second mains voltage line.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a top view of an array substrate according to an embodiment of the present disclosure.
Fig. 2 is a schematic cross-sectional view of the array substrate along a second power voltage line according to an embodiment of the present disclosure.
Fig. 3 is a top view of an array substrate according to another embodiment of the present disclosure.
Fig. 4 is a schematic cross-sectional structure view of the array substrate along a second reset signal line according to the embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the recitation of a first feature "on" or "under" a second feature may include the recitation of the first and second features being in direct contact, and may also include the recitation of the first and second features not being in direct contact, but being in contact with another feature between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Further, the present application may repeat reference numerals and/or reference letters in the various examples for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or arrangements discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
Referring to fig. 1 and fig. 2, an array substrate according to an embodiment of the present disclosure includes a substrate 100 and a source/drain layer 200.
A substrate 100, the substrate 100 may be a glass substrate or a flexible substrate. The material of the substrate 100 includes one or more of glass, silica, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide, or polyurethane.
As shown in fig. 2, fig. 2 is a cross-sectional film diagram of the second power voltage line 102 in the second direction B, the source-drain layer 200 is disposed on the substrate 100, and the source-drain layer 200 is used to form a plurality of first power voltage lines 101(VDD-1) and a plurality of second power voltage lines 102 (VDD-2); the material of the source drain layer 200 may include, but is not limited to, gold (Au), silver (Ag), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), or an alloy thereof, and the source drain layer 200 may have a single-layer structure or a multilayer structure including different metal layers, for example, the multilayer structure may be a multi-metal layer stack, for example, made of an aluminum, titanium, and aluminum three-layer metal stack (Al/Ti/Al), and by setting different metal stacks for both the first power voltage line 101 and the second power voltage line 102, compared with the setting of a single metal layer, it is more favorable to improve the electron mobility between metal layers, thereby being favorable to reducing the impedance of the metal lines.
Wherein a plurality of the first power voltage lines 101 extend along a first direction a, and each of the second power voltage lines 102 extends along a second direction B, the first direction a and the second direction B crossing each other. Specifically, the first direction a and the second direction B are perpendicular to each other, the second direction B is a horizontal direction, that is, a horizontal direction, and the first direction a is a vertical direction, that is, a vertical direction. Wherein the first supply voltage line 101 and the second supply voltage line 102 are used to provide a voltage signal. The number of the first power voltage line 101 and the second power voltage line 102 is plural, so that the orthographic projections of the first power voltage line 101 and the second power voltage line 102 on the substrate 100 form a net structure.
The array substrate of the embodiment of the application is formed by manufacturing the first power voltage line 101 and the second power voltage line 102 in the source drain layer 200, and compared with the prior art in which the first power voltage line 101 and the second power voltage line 102 are formed in different films respectively, the array substrate avoids the problem that the impedance difference between the first power voltage line 101 and the second power voltage line 102 is large due to the fact that materials of different films are different, and therefore the impedance uniformity of the first power voltage line 101 and the second power voltage line 102 is improved.
In some embodiments, the substrate 100 further includes a gate layer 300, the gate layer 300 is disposed on the substrate 100, the material of the gate layer 300 may include, but is not limited to, gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy thereof, and the gate layer may have a single-layer structure or a structure including different metal layers.
The gate layer 300 includes a first gate layer 310 and a second gate layer 320, the first gate layer 310 is disposed on the source drain layer 200, specifically, the first gate layer 310 is disposed on a side of the source drain layer 200 departing from the substrate 100, the second gate layer 320 is disposed on the first gate layer 310, and specifically, the second gate layer 320 is disposed on a side of the first gate layer 310 departing from the source drain layer 200.
The first gate layer 310 is configured to form the scan lines 201, the number of the scan lines 201 is multiple, and the multiple scan lines 201 extend along the second direction B.
The second gate layer 320 is used to form a first reset signal line 301(VI-1), and the first reset signal line 301 extends along the second direction B. The first reset signal line 301 is used for receiving a reset signal.
In some embodiments, the source and drain layers 200 are further configured to form a Data line (Data)103, the Data line 103 extends along a first direction a, the Data line 103 crosses the second power voltage line 102, and a crossing portion of the Data line 103 and the second power voltage line 102 is spaced apart from each other. Since the data line 103 and the second power voltage line 102 are disposed in the same layer, and the data line 103 and the second power voltage line 102 are disposed in the first direction a and the second direction B, respectively, wherein the data line 103 and the second power voltage line 102 intersect, by disposing the intersecting portion of the data line 103 and the second power voltage line 102 at intervals, the data line 103 and the second power voltage line 102 are prevented from interfering with each other, and the normal operation of the data line 103 and the second power voltage line 102 is ensured.
Specifically, in some embodiments, the second power voltage line 102 includes a first sub-voltage line 1021 and a second sub-voltage line 1022, and the array substrate further includes a first insulating layer 500.
The first insulating layer 500 is disposed between the second gate layer 320 and the source/drain layer 200, and the first via hole 21 and the second via hole 22 are disposed on the first insulating layer 500.
The first via hole 21 penetrates the first insulating layer 500, and the first sub-voltage line 1021 is filled in the first via hole 21.
The second via hole 22 penetrates through the first insulating layer 500, the first via hole 21 and the second via hole 22 are respectively disposed at two sides of the data line 103, and the second sub-voltage line 1022 is filled in the second via hole 22.
The first via 21 and the second via 22 are respectively communicated with the second gate layer 320, and the first sub-voltage line 1021 and the second sub-voltage line 1022 are electrically connected through the second gate layer 320. Since the second power voltage line 102 and the data line 103 are both formed in the source and drain layer 200, and the second power voltage line 102 extends along the second direction B, and the data line 103 extends along the first direction a, in order to prevent the second power voltage line 102 and the data line 103 from cross interference, in this embodiment, the second power voltage line 102 is formed in a segmented manner, i.e. divided into the first sub-voltage line 1021 and the second sub-voltage line 1022, and the first via 21 and the second via 22 are disposed, so that the first sub-voltage line 1021 and the second sub-voltage line 1022 are respectively communicated with the second gate layer 320 through the first via 21 and the second via 22, thereby avoiding the data line 103 and realizing the normal operation of the second power voltage line 102.
It is to be understood that the present application may also be implemented by manufacturing the second power voltage line 102 in a whole segment, and disposing the data line 103 in a segment at the crossing position of the data line 103 and the second power voltage line 102, that is, disposing the first via 21 and the second via 22 on the data line 103, and disposing the first via 21 and the second via 22 on two sides of the second power voltage line 102, so that the segmented data line 103 is communicated with the second gate layer 320 through the first via 21 and the second via 22, respectively. The data line 103 is also made in segments, so that the data line 103 and the second power supply voltage line 102 are prevented from interfering with each other, and the normal operation of the data line 103 and the second power supply voltage line 102 is ensured.
In some embodiments, referring to fig. 3, the source/drain layer 200 is further used to form a second reset signal line 104(VI-2), wherein the second reset signal line 104 is also used to access a reset signal. The second reset signal line 104 extends along the first direction a, the second reset signal line 104 is connected to the first reset signal line 301 through a hole, the second reset signal line 104 is spaced apart from the first power voltage line 101 in the second direction B, the second reset signal line 104 crosses the second power voltage line 102, and the second reset signal line 104 is spaced apart from a crossing portion of the second power voltage line 102.
The number of the first reset signal lines 301 and the second reset signal lines 104 is multiple, so that the first reset signal lines 301 and the second reset signal lines 104 form a mesh structure. The second reset signal line 104 is additionally arranged, so that the luminous reduction capability of the panel is enhanced, and the luminous efficiency of the panel is improved. In addition, the second reset signal line 104 is formed in the source/drain layer 200, and thus, an additional film layer is not required, which is beneficial to simplifying the process.
In some embodiments, referring to fig. 4, fig. 4 is a cross-sectional film view of the second reset signal line 104 along the first direction a, where the second reset signal line 104 includes a first sub-signal line 1041 and a second sub-signal line 1042, and a third via 23 and a fourth via 24 are further disposed on the first insulating layer 500.
The third via hole 23 penetrates through the first insulating layer 500, and the first sub-signal line 1041 is filled in the third via hole 23.
A fourth via hole 24 penetrating through the first insulating layer 500, wherein the third via hole 23 and the fourth via hole 24 are respectively disposed at two sides of the second power voltage line 102, and the second sub-signal line 1042 is filled in the fourth via hole 24.
The third via 23 and the fourth via 24 are respectively communicated with the second gate layer 320, and the second sub-signal line 1042 are electrically connected by the second gate layer 320. Since the second reset signal line 104 and the second power voltage line 102 are both formed in the source drain layer 200, and the second reset signal line 104 extends along the first direction a, and the second power voltage line 102 extends along the second direction B, in order to prevent the second reset signal line 104 and the second power voltage line 102 from cross interference, in this embodiment, the second reset signal line 104 is formed in a segmented manner, i.e. divided into the first sub-signal line 1041 and the second sub-signal line 1042, and the third via 23 and the fourth via 24 are disposed, so that the first sub-signal line 1041 and the second sub-signal line 1042 are respectively communicated with the second gate layer 320 through the third via 23 and the fourth via 24, thereby avoiding the second power voltage line 102, and realizing the normal operation of the second reset signal line 104.
In some embodiments, the first gate layer 310 is further configured to form a capacitor upper plate 501, the second gate layer 320 is further configured to form a capacitor lower plate 502, and the capacitor upper plate 501 and the capacitor lower plate 502 are disposed opposite to each other.
The array substrate further includes an active layer 400. The active layer 400 is disposed between the substrate base plate 100 and the gate layer, the active layer 400 is used for forming a signal line 401, and the adjacent data line 103 is electrically connected to the first power voltage line 101 through the signal line 401.
A plurality of first reset signal lines 301 arranged at intervals are arranged on the substrate base plate 100, and every two first reset signal lines 301 are connected through the signal line 401.
On the other hand, in order to better implement the array substrate of the present application, embodiments of the present application further provide a display panel, where the display panel includes the array substrate. Since the display panel has the array substrate, all the same beneficial effects are achieved, and the description of the invention is omitted here.
On the other hand, the embodiment of the application also provides a display device, and the display device comprises the display panel. The display panel may be a liquid crystal display panel, an OLED panel, or the like, and is not particularly limited herein. Since the display device has the display panel, all the same beneficial effects are achieved, and the description of the invention is omitted here.
The embodiment of the application is not specifically limited to the application of the display device, and the display device can be any product or part with a display function, such as a television, a notebook computer, a tablet computer, wearable display equipment (such as an intelligent bracelet, an intelligent watch and the like), a mobile phone, virtual reality equipment, augmented reality equipment, vehicle-mounted display, an advertising lamp box and the like.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate, the display panel and the display device provided by the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (9)
1. An array substrate, comprising:
a substrate base plate;
the source-drain layer is arranged on the substrate and used for forming a plurality of first power supply voltage lines and a plurality of second power supply voltage lines;
each first power supply voltage line extends along a first direction, each second power supply voltage line extends along a second direction, the first direction and the second direction are crossed, and the orthographic projection of the first power supply voltage lines and the orthographic projection of the second power supply voltage lines on the substrate are distributed in a net shape, wherein the second power supply voltage lines comprise first sub-voltage lines and second sub-voltage lines, and the array substrate further comprises:
a gate layer comprising a second gate layer;
the first insulating layer is arranged between the second gate layer and the source drain layer, and a first through hole and a second through hole are formed in the first insulating layer;
the first via hole penetrates through the first insulating layer, and the first sub-voltage line is filled in the first via hole;
the second via hole penetrates through the first insulating layer, the first via hole and the second via hole are respectively arranged on two sides of the data line, and the second sub-voltage line is filled in the second via hole;
the first via hole and the second via hole are respectively communicated with the second gate layer, and the first sub-voltage line is electrically connected with the second sub-voltage line through the second gate layer.
2. The array substrate of claim 1, wherein the gate layer further comprises a first gate layer disposed on the source drain layer, and the second gate layer is disposed on the first gate layer;
the first gate layer is used for forming a scanning line, and the scanning line extends along the first direction;
the second gate layer is used for forming a first reset signal line extending along the first direction.
3. The array substrate of claim 2, wherein the source and drain layers are further configured to form a data line, the data line is disposed along a first direction, the data line crosses the second power voltage line, and the crossing portion of the data line and the second power voltage line is spaced apart from each other.
4. The array substrate of claim 1, wherein the source and drain layers are further configured to form a second reset signal line, the second reset signal line extends along the first direction, the second reset signal line is spaced apart from the first power voltage line in a second direction, the second reset signal line crosses the second power voltage line, and the second reset signal line is spaced apart from a crossing portion of the second power voltage line.
5. The array substrate of claim 4, wherein the second reset signal line comprises a first sub-signal line and a second sub-signal line, and a third via hole and a fourth via hole are further formed on the first insulating layer;
the third through hole penetrates through the first insulating layer, and the first sub-signal line is filled in the third through hole;
the fourth via hole penetrates through the first insulating layer, the third via hole and the fourth via hole are respectively arranged on two sides of the second power supply voltage line, and the second sub-signal line is filled in the fourth via hole;
the third via hole and the fourth via hole are respectively communicated with the second gate layer, and the second sub-signal line are electrically connected through the second gate layer.
6. The array substrate of any of claims 1-5, wherein the first supply voltage line and the second supply voltage line are made of a tri-layer metal stack of aluminum, titanium, and aluminum.
7. The array substrate of any one of claims 3-5, wherein the array substrate further comprises:
and the active layer is arranged between the substrate and the gate layer and is used for forming a signal line, and the adjacent data line and the first power supply voltage line are electrically connected through the signal line.
8. A display panel comprising the array substrate according to any one of claims 1 to 7.
9. A display device comprising the display panel according to claim 8.
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| CN202110272319.XA CN113053921B (en) | 2021-03-12 | 2021-03-12 | Array substrate, display panel and display device |
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| CN111025798B (en) * | 2019-12-02 | 2021-06-25 | 武汉华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111681549B (en) * | 2020-06-16 | 2022-03-18 | 昆山国显光电有限公司 | Array substrate and display panel |
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