CN113053807A - Through hole structure preparation method, through hole structure and semiconductor device - Google Patents
Through hole structure preparation method, through hole structure and semiconductor device Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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Abstract
The embodiment of the invention provides a through hole structure, a preparation method of the through hole structure and a semiconductor device, and relates to the technical field of semiconductors. The lower part of the first conductive through hole is provided with the second conductive through hole in an expanding shape, and the second conductive through hole is in contact with the first conductive layer, so that the contact area with the first conductive layer is increased during subsequent filling, the contact resistance is reduced, and the performance of a semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a through hole structure preparation method, a through hole structure and a semiconductor device.
Background
In the field of integrated circuit manufacturing, it is generally necessary to implement electrical connections for different metal layers, and the common approach includes providing metal vias on a dielectric layer, and the metal vias are always one of the most main sources of back-end resistance, and when the contact resistance of the metal vias is large, the performance of the semiconductor device is affected.
Traditional back end metal through-hole is continuous appearance/profile, draws when connecting lower floor's metal, and metal through-hole's bottom linewidth can be far less than through-hole top linewidth, because metal through-hole's bottom linewidth is less, consequently can cause the bottom to the area of contact of lower floor's metal to reduce, and then has increased contact resistance. The contact resistance of the via in the back section tends to dominate the device performance of the whole back section, so a higher via contact resistance means a poorer semiconductor device performance.
Disclosure of Invention
The purpose of the present invention includes, for example, providing a method for manufacturing a via structure, and a semiconductor device, which can reduce contact resistance and improve the performance of the semiconductor device.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a method for manufacturing a via structure, including:
forming a hole on the dielectric layer and exposing the stop layer below the hole to form a first conductive through hole penetrating through the dielectric layer;
forming a hole on the stop layer positioned in the first conductive through hole, and exposing the first conductive layer below to form a second conductive through hole penetrating through the stop layer;
the first conductive through hole is communicated with the second conductive through hole, and the line width of the second conductive through hole is larger than that of the adjacent first conductive through hole.
In an alternative embodiment, the step of opening a hole in the dielectric layer and exposing the underlying stop layer comprises:
and etching the dielectric layer and exposing the stop layer below.
In an alternative embodiment, the step of opening a hole in the stop layer located in the first conductive via and exposing the underlying first conductive layer comprises:
and laterally etching the stop layer in the first conductive through hole, and exposing the first conductive layer below.
In an alternative embodiment, after the step of opening the stop layer located in the first conductive via and exposing the first conductive layer therebelow, the preparation method further comprises:
sequentially filling the second conductive through hole and the first conductive through hole with a conductive material to form a conductive column;
forming a second conductive layer on the dielectric layer;
wherein the conductive post is in electrical contact with the first conductive layer and the second conductive layer is in electrical contact with the conductive post.
In an alternative embodiment, the step of forming a second conductive layer on the dielectric layer comprises:
sputtering metal on the dielectric layer to form the second conductive layer.
In an alternative embodiment, the step of filling the first and second conductive vias with a conductive material comprises:
and sequentially filling the second conductive through hole and the first conductive through hole with a metal material to form a conductive column.
In an alternative embodiment, the first conductive layer is a conductive layer.
In an alternative embodiment, the etch rate of the stop layer is less than the etch rate of the dielectric layer.
In a second aspect, the present invention provides a via structure comprising:
a first conductive layer;
a stop layer formed on the first conductive layer;
a dielectric layer formed on the stop layer;
the dielectric layer is provided with a first conductive through hole, the stop layer is provided with a second conductive through hole, the first conductive through hole is communicated with the second conductive through hole, and the line width of the second conductive through hole is larger than that of the adjacent first conductive through hole.
In an alternative embodiment, the via structure further includes a second conductive layer formed on the dielectric layer, and the second conductive via and the first conductive via are both filled with a conductive material to form a conductive pillar, the conductive pillar being in electrical contact with the first conductive layer, and the second conductive layer being in electrical contact with the conductive pillar.
In a third aspect, the present invention provides a semiconductor device comprising the aforementioned via structure.
The beneficial effects of the embodiment of the invention include, for example:
according to the through hole structure, the preparation method of the through hole structure and the semiconductor device, the first conductive through hole penetrating through the dielectric layer is formed by opening the dielectric layer, then the stopping layer is opened, the second conductive through hole penetrating through the stopping layer is formed, the second conductive through hole is connected with the first conductive through hole, and the line width of the second conductive through hole is larger than that of the adjacent first conductive through hole. The lower part of the first conductive through hole is provided with the second conductive through hole in an expanding shape, and the second conductive through hole is in contact with the first conductive layer, so that the contact area with the first conductive layer is increased during subsequent filling, the contact resistance is reduced, and the performance of a semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a via structure according to a first embodiment of the present invention;
fig. 2 is a block diagram illustrating a method for fabricating a via structure according to a second embodiment of the present invention;
fig. 3 to fig. 6 are process flow diagrams of a method for manufacturing a via structure according to a second embodiment of the present invention.
Icon: 100-via structures; 110-a first conductive layer; 130-a stop layer; 131-a second conductive via; 150-a dielectric layer; 151-first conductive via; 170 — a second conductive layer; 190-conductive post.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background art, the conventional back-end metal via has a continuous shape/contour, and when the back-end metal via is connected to the lower layer metal, the bottom line width of the metal via is much smaller than the top line width of the via, and the bottom line width of the metal via is smaller, so that the contact area of the bottom to the lower layer metal is reduced, and the contact resistance is increased. The contact resistance of the via in the back section tends to dominate the device performance of the whole back section, so a higher via contact resistance means a poorer semiconductor device performance. Therefore, if the contact area between the metal via and the lower metal layer can be increased, the contact resistance will be reduced, and the device performance will be improved.
In order to solve the problem of large contact resistance caused by metal vias in the prior art, the invention provides a method for manufacturing a via structure, a via structure and a semiconductor device.
First embodiment
Referring to fig. 1, the present embodiment provides a via structure 100 capable of reducing contact resistance and improving the performance of a semiconductor device.
The via structure 100 provided by the present invention includes a first conductive layer 110, a stop layer 130 formed on the first conductive layer 110, a dielectric layer 150 formed on the stop layer 130, and a second conductive layer 170 formed on the dielectric layer 150. The dielectric layer 150 has a first conductive via 151 formed thereon, the stop layer 130 has a second conductive via 131 formed thereon, the first conductive via 151 is connected to the second conductive via 131, and a line width of the second conductive via 131 is greater than a line width of the adjacent first conductive via 151.
In this embodiment, the via structure 100 may be a part of a common semiconductor device, or may be a part of a multilayer PCB, the second conductive via 131 and the first conductive via 151 are both filled with a conductive material to form a conductive pillar 190 embedded in the second conductive via 131 and the first conductive via 151, the conductive pillar 190 is electrically contacted with the first conductive layer 110, the second conductive layer 170 is electrically contacted with the conductive pillar 190, and the first conductive layer 110 and the second conductive layer 170 are electrically contacted through the conductive pillar 190.
It should be noted that the line widths of the first conductive via 151 and the second conductive via 131 in this embodiment refer to the aperture sizes of the first conductive via 151 and the second conductive via 131, specifically, the line width of the first conductive via 151 gradually decreases from the second conductive layer 170 to the first conductive layer 110, that is, the line width of the end of the first conductive via 151 close to the first conductive layer 110 is greater than the line width of the end of the first conductive via 151 close to the second conductive layer 170. Also, the line width of the second conductive via 131 is greater than the line width of the adjacent first conductive via 151, which means that the line width of the second conductive via 131 is greater than the line width of the end of the first conductive via 151 close to the first conductive layer 110, and the size relationship between the line width of the end of the first conductive via 151 close to the second conductive layer 170 and the line width of the second conductive via 131 is not particularly limited, and preferably, the line width of the top end of the first conductive via 151 may be greater than the line width of the second conductive via 131.
In this embodiment, the first conductive via 151 and the second conductive via 131 are filled with a conductive material to form a conductive pillar 190 for electrically connecting the first conductive layer 110 and the second conductive layer 170, wherein the conductive material may be a conductive metal, such as a copper material, and during actual manufacturing, the first conductive via 151 and the second conductive via 131 may be formed through an etching process, and then the second conductive via 131 and the first conductive via 151 are sequentially filled with a copper material to form a copper pillar with a good conductive function. Of course, the conductive material may be aluminum material or other filling materials with conductive function, such as conductive paste doped with metal particles.
Preferably, in this embodiment, the first conductive layer 110 and the second conductive layer 170 are both made of a metal material, for example, a copper material, that is, the first conductive layer 110 and the second conductive layer 170 are both made of a copper material layer, and the conductive pillar 190 and the second conductive layer 170 may be integrally formed or may be separately formed.
In this embodiment, the conductive pillar 190 and the second conductive layer 170 are separately formed, after the first conductive via 151 and the second conductive via 131 are formed, the first conductive via 151 and the second conductive via 131 may be filled by a copper electroplating layer, and the conductive pillar 190 is formed and then polished by a CMP machine, so as to ensure the flatness of the surface of the dielectric layer 150, and the second conductive layer 170 is formed on the surface of the polished dielectric layer 150 by sputtering, so as to ensure the distribution uniformity of the second conductive layer 170.
In this embodiment, circuit layers are further distributed on the first conductive layer 110 and the second conductive layer 170, and electrically connected to the conductive post 190 after the wiring is performed.
In the present embodiment, the stop layer 130 and the dielectric layer 150 are both dielectric materials, and have high resistivity, and one or more of silicon dioxide, polystyrene, silicon carbide, diamond, sapphire, germanium, and silicon may be used. The materials of the stop layer 130 and the dielectric layer 150 are different, the etching rate of the dielectric layer 150 is greater than that of the stop layer 130, and the etching rate of the stop layer 130 is greater than that of the first conductive layer 110, so that the etching can be stopped on the stop layer 130 when the first conductive via 151 is formed by the etching process, and then the etching process is adjusted to perform the etching process of the stop layer 130 and stopped on the first conductive layer 110. And, when the second conductive via 131 is formed by etching, a lateral etching process is adopted, so that the second conductive via 131 forms a hole expansion structure and is wider than the adjacent first conductive via 151. In the embodiment, by using the etching rate selectivity difference between the stop layer 130, the dielectric layer 150 and the first conductive layer 110, a lateral etching profile is performed when the second conductive via 131 on the stop layer 130 is etched, so that the contact area between the bottom surface and the first conductive layer 110 is increased, and the contact resistance of the conductive post 190 is reduced.
It should be noted that, in the present embodiment, the thickness of the stop layer 130 is smaller than that of the dielectric layer 150, and the stop layer 130 is used for stopping etching when the first conductive via 151 is formed by etching, so that the etching is stopped at the stop layer 130.
In summary, the present embodiment provides a via structure 100, a first conductive via 151 penetrating through a dielectric layer 150 is formed by opening a hole in the dielectric layer, and then a second conductive via 131 penetrating through a stop layer 130 is formed by opening a hole in the stop layer 130, the second conductive via 131 is connected to the first conductive via 151, and the line width of the second conductive via 131 is greater than the line width of the adjacent first conductive via 151. The second conductive through hole 131 in the shape of an expanded hole is formed in the lower portion of the first conductive through hole 151, and the second conductive through hole 131 is in contact with the first conductive layer 110, so that the contact area with the first conductive layer 110 is increased when the conductive column 190 is formed by subsequent filling, the contact resistance is reduced, and the performance of the semiconductor device is improved.
Second embodiment
Referring to fig. 2, the present embodiment further provides a method for preparing a via structure, which is used to prepare the via structure 100 provided in the first embodiment, and when preparing the via structure 100, the method includes the following steps:
s1: a substrate structure is provided.
Referring to fig. 3 in combination, specifically, the substrate structure includes a first conductive layer 110, a stop layer 130 and a dielectric layer 150, the stop layer 130 is located on the first conductive layer 110, and the dielectric layer 150 is located on the stop layer 130, and the substrate structure may be prepared in advance or in situ before performing step S2.
It should be noted that the base structure can be formed by growing the first conductive layer 110 on the substrate, growing the stop layer 130 on the first conductive layer 110, growing the dielectric layer 150 on the stop layer 130, and finally peeling off the substrate, and the growth process thereof can refer to a conventional epitaxial growth process, which will not be described in detail herein.
In the present embodiment, the first conductive layer 110 is a metal layer, and specifically, the first conductive layer 110 is a copper layer, which has good conductive performance.
S2: a hole is opened in the dielectric layer 150 and the underlying stop layer 130 is exposed to form a first conductive via 151 (shown in fig. 4) through the dielectric layer 150.
Referring to fig. 4, specifically, the dielectric layer 150 is etched, and an opening is formed in the dielectric layer 150 by an etching process, wherein the etching depth is the thickness of the dielectric layer 150, and the etching is performed until the underlying stop layer 130 is exposed. Here, the material of the stop layer 130 is different from the material of the dielectric layer 150, and the etching rate of the dielectric layer 150 is much greater than that of the stop layer 130, so that the etching can be stopped on the stop layer 130 when the first conductive via 151 is formed.
In other preferred embodiments of the present invention, the process of forming the first conductive via 151 by opening the dielectric layer 150 may also be a laser opening process, and the opening process is not limited herein.
It should be noted that, in the process of etching the dielectric layer 150 in this embodiment, the etching line width gradually decreases with the increase of the etching depth, so that the upper line width of the first conductive via 151 is greater than the lower line width.
S3: openings are formed in the stop layer 130 within the first conductive vias 151 and expose the underlying first conductive layer 110 to form second conductive vias 131 (shown in fig. 5) through the stop layer 130.
Referring to fig. 5, in the present embodiment, after the first conductive via 151 is formed by etching and the stop layer 130 is exposed, the etching process parameters are adjusted, and the stop layer 130 is laterally etched again and the underlying first conductive layer 110 is exposed. An etching process is used to open a hole in the stop layer 130, wherein the etching depth is the thickness of the stop layer 130, and the etching is performed until the underlying first conductive layer 110 is exposed. Here, the material of the stop layer 130 is different from the material of the first conductive layer 110, and the etching rate of the first conductive layer 110 is much smaller than that of the stop layer 130, so that the etching can be stopped on the first conductive layer 110 when the second conductive via 131 is formed. Moreover, the first conductive through hole 151 is communicated with the second conductive through hole 131, and a lateral etching process, i.e., a drilling and etching process, is adopted when the etching stop layer 130 is etched, so that the line width of the etched second conductive through hole 131 is larger than the line width of the adjacent first conductive through hole 151.
It should be noted that, in the present embodiment, by the lateral etching process, the second conductive via 131 is formed at the lower portion of the first conductive via 151, so as to increase the exposed area of the first conductive layer 110.
S4: the second conductive via 131 and the first conductive via 151 are sequentially filled with a conductive material, and a conductive pillar 190 (shown in fig. 6) is formed.
Referring to fig. 6, specifically, the conductive material is a copper material, the second conductive via 131 and the first conductive via 151 are sequentially filled with the copper material by an electroplating process, and ground after molding, so as to form a conductive pillar 190 penetrating through the dielectric layer 150 and the stop layer 130, wherein a top of the conductive pillar 190 is flush with a top surface of the dielectric layer 150.
In this embodiment, the copper material is filled in the second conductive via 131 and directly contacts with the first conductive layer 110 exposed in the second conductive via 131, so as to realize the electrical contact between the conductive pillar 190 and the first conductive layer 110, and since the line width of the second conductive via 131 is relatively large, the contact area between the conductive pillar 190 and the first conductive layer 110 is increased, the contact resistance between the conductive pillar 190 and the first conductive layer 110 is greatly reduced, and the performance of the entire device is improved.
S5: a second conductive layer 170 is formed on the dielectric layer 150.
Referring to fig. 1 in combination, specifically, a metal is sputtered on the dielectric layer 150, thereby forming a second conductive layer 170. The second conductive layer 170 is also a copper layer. In actual fabrication, a copper material may be sputtered on the upper surface of the dielectric layer 150 to form the second conductive layer 170 with a uniform thickness. Of course, the second conductive layer 170 may be formed by other processes, such as CVD (Chemical Vapor Deposition), VPE (Vapor Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), atomic layer Epitaxy, MBE (Molecular Beam Epitaxy), evaporation, and the like.
In the present embodiment, the conductive pillar 190 is electrically contacted with the first conductive layer 110, the second conductive layer 170 is electrically contacted with the conductive pillar 190, and the first conductive layer 110, the second conductive layer 170 and the conductive pillar 190 are made of copper, which has good conductive performance.
In summary, in the method for manufacturing a via structure provided in this embodiment, the first conductive via 151 penetrating through the dielectric layer is formed by etching the dielectric layer, the second conductive via 131 penetrating through the stop layer 130 is formed by etching the stop layer 130, the second conductive via 131 is connected to the first conductive via 151, and a lateral etching process is adopted, so that the line width of the second conductive via 131 is greater than the line width of the adjacent first conductive via 151. The second conductive through hole 131 in the shape of an expanded hole is formed in the lower portion of the first conductive through hole 151, and the second conductive through hole 131 is in contact with the first conductive layer 110, so that the contact area with the first conductive layer 110 is increased when the conductive column 190 is formed by subsequent filling, the contact resistance is reduced, and the performance of the semiconductor device is improved.
Third embodiment
The present embodiment provides a semiconductor device including the via structure 100 provided in the first embodiment.
The via structure 100 includes a first conductive layer 110, a stop layer 130 formed on the first conductive layer 110, a dielectric layer 150 formed on the stop layer 130, and a second conductive layer 170 formed on the dielectric layer 150. The dielectric layer 150 has a first conductive via 151 formed thereon, the stop layer 130 has a second conductive via 131 formed thereon, the first conductive via 151 is connected to the second conductive via 131, and a line width of the second conductive via 131 is greater than a line width of the adjacent first conductive via 151.
In this embodiment, the first conductive layer 110 and the second conductive layer 170 may also be connected to a chip, a capacitor, a resistor, and other elements, and the specific arrangement structure thereof may refer to an existing semiconductor package structure.
In the present embodiment, the first conductive layer 110 and the second conductive layer 170 are both metal layers to achieve good conductive performance. Of course, in other preferred embodiments of the present invention, the first conductive layer 110 and the second conductive layer 170 may also be made of semiconductor materials, and are electrically connected to the conductive pillar 190 by a copper wire being laid inside, which is not described herein again.
In the semiconductor device provided in this embodiment, a first conductive via 151 penetrating through the dielectric layer is formed by opening a hole in the dielectric layer, and then a second conductive via 131 penetrating through the stop layer 130 is formed by opening a hole in the stop layer 130, the second conductive via 131 is connected to the first conductive via 151, and the line width of the second conductive via 131 is greater than the line width of the adjacent first conductive via 151. The second conductive through hole 131 in the shape of an expanded hole is arranged at the lower part of the first conductive through hole 151, and is in contact with the first conductive layer 110 through the second conductive through hole 131, so that the contact area with the first conductive layer 110 is increased during subsequent filling, the contact resistance is reduced, and the performance of the semiconductor device is improved.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A method for fabricating a via structure, comprising:
forming a hole on the dielectric layer and exposing the stop layer below the hole to form a first conductive through hole penetrating through the dielectric layer;
forming a hole on the stop layer positioned in the first conductive through hole, and exposing the first conductive layer below to form a second conductive through hole penetrating through the stop layer;
the first conductive through hole is communicated with the second conductive through hole, and the line width of the second conductive through hole is larger than that of the adjacent first conductive through hole.
2. The method of claim 1, wherein the step of opening the dielectric layer to expose the underlying stop layer comprises:
and etching the dielectric layer and exposing the stop layer below.
3. The method of claim 1, wherein the step of opening the stop layer in the first conductive via to expose the underlying first conductive layer comprises:
and laterally etching the stop layer in the first conductive through hole, and exposing the first conductive layer below.
4. The method of claim 1, wherein after the step of opening the stop layer in the first conductive via and exposing the underlying first conductive layer, the method further comprises:
sequentially filling the second conductive through hole and the first conductive through hole with a conductive material to form a conductive column;
forming a second conductive layer on the dielectric layer;
wherein the conductive post is in electrical contact with the first conductive layer and the second conductive layer is in electrical contact with the conductive post.
5. The method of claim 4, wherein the step of forming a second conductive layer on the dielectric layer comprises:
sputtering metal on the dielectric layer to form the second conductive layer.
6. The method of claim 4, wherein the step of filling the first and second conductive vias with a conductive material comprises:
and sequentially filling the second conductive through hole and the first conductive through hole with a metal material to form a conductive column.
7. The method of claim 1, wherein the first conductive layer is a metal layer.
8. A via structure, comprising:
a first conductive layer;
a stop layer formed on the first conductive layer;
a dielectric layer formed on the stop layer;
the dielectric layer is provided with a first conductive through hole, the stop layer is provided with a second conductive through hole, the first conductive through hole is communicated with the second conductive through hole, and the line width of the second conductive through hole is larger than that of the adjacent first conductive through hole.
9. The via structure of claim 8, further comprising a second conductive layer formed on the dielectric layer, wherein the second conductive via and the first conductive via are each filled with a conductive material to form a conductive pillar, the conductive pillar being in electrical contact with the first conductive layer, and the second conductive layer being in electrical contact with the conductive pillar.
10. A semiconductor device comprising the via structure of claim 8 or 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023279808A1 (en) * | 2021-07-05 | 2023-01-12 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
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