CN113053744B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN113053744B
CN113053744B CN202011499279.4A CN202011499279A CN113053744B CN 113053744 B CN113053744 B CN 113053744B CN 202011499279 A CN202011499279 A CN 202011499279A CN 113053744 B CN113053744 B CN 113053744B
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plasma
etching
chamber
damaged layer
sample
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CN113053744A (en
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石井洋平
凯瑟琳·迈尔
梅德哈特·哈利勒
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Hitachi High Tech Corp
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Hitachi High Technologies Corp
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Priority claimed from US16/906,206 external-priority patent/US11756793B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The present invention enables the formation of a pattern having a vertical cross section by a relatively low temperature process when a fine pattern is processed using a compound semiconductor material or the like. The method for manufacturing a semiconductor device includes a step of etching a semiconductor material using plasma, a step of forming a damaged layer in the semiconductor material, and a step of removing the damaged layer.

Description

Method for manufacturing semiconductor device
Technical Field
The present invention relates to a method for manufacturing a semiconductor device using a compound semiconductor material or the like.
Background
As the integration of semiconductor devices increases and patterns formed on substrates are miniaturized, a material having high electron mobility is required as a material used as a channel material.
As the channel material having such high mobility, a compound semiconductor such as a group III-V material is known. Patent document 1 (japanese patent application laid-open No. 2010-40780) describes a plasma etching process for a compound semiconductor containing indium (In).
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2010-40780
Compound semiconductors such as III-V materials have problems of low volatility (difficult volatility) and difficult anisotropic processing.
As a method for solving the problem, patent document 1 (japanese patent application laid-open No. 2010-40780) describes that, when a compound semiconductor containing indium (In) is processed, a plasma etching treatment is performed In which a workpiece is heated to a high temperature and then the workpiece is processed In a plasma.
However, compound semiconductor materials have a problem that anisotropic processing is difficult due to low volatility. Further, there is a problem that the etching rate of the lower portion (the side closer to the substrate) of the pattern becomes lower than the etching rate of the upper portion (the side closer to the plasma) of the formed pattern due to the low volatility, and the cross section is preferably processed into a vertical shape, but the lower portion is processed into a tapered shape having a larger size than the upper portion of the pattern, and it is difficult to form a pattern having a vertical shape in cross section.
In order to heat the workpiece to a high temperature and process the workpiece, a relatively expensive material such as one that can withstand a high temperature must be used as the mask material.
Disclosure of Invention
The present invention solves the above-described problems of the prior art, and provides a method for manufacturing a semiconductor device, which enables a pattern having a vertical cross section to be formed by a relatively low-temperature process when a fine pattern is processed using a compound semiconductor material or the like.
Means for solving the problems
In order to solve the above-described problems, in the method of forming a pattern of a semiconductor material on a substrate by processing the semiconductor material, the semiconductor material is processed by performing plasma etching on the semiconductor material, forming a damage (damage) layer on the semiconductor material, and removing the formed damage layer by wet etching or plasma treatment.
Effects of the invention
According to the present invention, a semiconductor material can be processed to form a fine pattern having a vertical processing section.
Drawings
Fig. 1 is a block diagram showing a schematic configuration of a plasma etching apparatus according to embodiment 1 of the present invention.
Fig. 2 is a block diagram showing a schematic configuration of a wet etching apparatus according to embodiment 1 of the present invention.
Fig. 3 is a flowchart showing a flow of processing in the processing method of the compound semiconductor material according to example 1 of the present invention.
Fig. 4 is a flowchart showing a flow of a process of anisotropic processing by plasma etching in the process in the processing method of the compound semiconductor material according to example 1 of the present invention.
Fig. 5 is a flowchart showing a flow of a process for forming a damaged layer by plasma etching in the process in the method for processing a compound semiconductor material according to example 1 of the present invention.
Fig. 6 is a flowchart showing a flow of a process of selectively removing a damaged layer by wet etching in a process in a method of processing a compound semiconductor material according to example 1 of the present invention.
Fig. 7 is a view showing the cross-sectional shape of a sample in each step of the processing of the compound semiconductor material according to example 1 of the present invention.
Fig. 8 is a graph showing a relationship between ion energy and ion penetration depth when hydrogen ions are irradiated to a material (InGaAs) forming a damaged layer.
Fig. 9 is a graph showing a relationship between power applied to a substrate sample stage and ion energy incident on a substrate, which is actually measured using the plasma etching apparatus according to example 1 of the present invention.
Fig. 10 is a block diagram showing a schematic configuration of a plasma processing apparatus according to embodiment 2 of the present invention.
Fig. 11 is a flowchart showing a flow of processing of the method for processing a compound semiconductor material according to example 2 of the present invention.
Fig. 12 is a flowchart showing a flow of a process of selectively removing a damaged layer using a plasma processing apparatus in a process in a method of processing a compound semiconductor material according to example 2 of the present invention.
Description of the reference numerals
100: a plasma etching device;
101: a microwave power supply;
103: a waveguide;
104: an etching processing chamber;
105: a dielectric window;
106: an electromagnetic coil;
107: a sample;
108: a sample stage;
110: a high frequency power supply;
112: a matching circuit;
114: a gas supply unit;
115: a gas flow rate control unit;
116: a vacuum exhaust unit;
120: a control unit;
200: a wet etching device;
201: a treatment liquid tank;
202: a supply pipe;
203: a discharge pipe;
204: a feed liquid flow rate adjustment unit;
205: a discharge liquid flow rate adjustment unit;
206: etching treatment liquid;
210: a control unit;
220: a sample loading means;
222: a sample loading tool driving section;
1000: a plasma processing device;
1100: a plasma processing chamber;
1110: a plasma generation chamber;
1120: a radical irradiation chamber;
1121: a substrate sample stage;
1122: an insulating block;
1140: a gas supply nozzle;
1150: a vacuum exhaust pump;
1160: a high frequency power supply;
1170: and a control unit.
Detailed Description
The present invention relates to a method for manufacturing a semiconductor device, which includes a step of forming a damaged layer on a semiconductor material, a step of removing the formed damaged layer by wet etching or plasma treatment.
In the present invention, a plasma treatment step of forming a damaged layer in a portion having a taper shape remaining in the anisotropic processing step and an anisotropic processing step by plasma etching may be combined with a wet etching treatment step or a plasma treatment step of removing the formed damaged layer.
In addition, in the damaged layer forming step, the energy of the incident ions incident on the substrate is controlled by a process using light elements (hydrogen, helium), thereby forming a desired damaged layer at a cone-shaped portion caused by the anisotropic processing step.
Further, in the present invention, as a process condition, ion energy (substrate bias power) is determined so that ion incidence depth becomes the whole of the tapered portion in order to form a damaged layer at a portion remaining in a tapered shape after a step of removing a semiconductor material by plasma etching.
In addition, since the pressure in the damaged layer forming step requires normal incidence of ions (in order to prevent the damaged layer from being formed under the mask), a pressure region where no ions within the sheath collide is used.
Further, in the case where the semiconductor material is a compound semiconductor material, the present invention uses chlorine (Cl) in the anisotropic processing step 2 ) And hydrogen (H) 2 ) The mixed gas or chlorine (Cl) 2 ) Hydrogen (H) 2 ) And methane (CH) 4 ) Mixed gas.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Example 1
Fig. 1 is a block diagram showing the structure of a plasma etching apparatus 100 used in the plasma etching process and the damaged layer forming process in the present embodiment.
The plasma etching apparatus 100 according to the present embodiment shown in fig. 1 includes: an etching process chamber 104; a microwave power supply 101; a waveguide 103 connecting the microwave power supply 101 and the etching chamber 104; a dielectric window 105 for supplying the etching gas introduced into the etching chamber 104 to the etching chamber 104 at the upper portion of the etching chamber 104 and introducing microwave power having a frequency of, for example, 2.45GHz propagating from the waveguide 103 into the etching chamber 104; and an electromagnetic coil 106 disposed on the outer periphery of the etching chamber 104 for forming a magnetic field inside the etching chamber 104, and the plasma etching apparatus 100 generates a microwave ECR plasma inside the etching chamber 104.
The etching chamber 104 includes a sample stage 108 on which a sample 107 is placed, a high-frequency power supply 110 for applying high-frequency power to the sample stage 108 to introduce ions into plasma to the sample 107 placed on the sample stage 108, and a matching circuit 112 for adjusting the high-frequency impedance of the sample stage 108 with respect to the high-frequency power supply 110. A sample stage 108 is disposed inside the etch processing chamber 104.
The plasma etching apparatus 100 further includes: a gas supply unit 114 for supplying a process gas into the etching chamber 104; a gas flow rate control unit 115 for controlling the flow rate of the process gas supplied from the gas supply unit 114 into the etching chamber 104; and a vacuum exhaust unit 116 for evacuating the interior of the etching chamber 104.
Reference numeral 120 denotes a control unit that controls the microwave power source 101, the electromagnetic coil 106, the high-frequency power source 110, the gas flow rate control unit 115, the vacuum exhaust unit 116, and the like.
The control unit 120 further includes a storage unit 121, an arithmetic unit 122, and a CPU123. A program for processing the sample 107 in the plasma etching apparatus 100 and product processing conditions for controlling the microwave power source 101, the electromagnetic coil 106, the high-frequency power source 110, the gas flow rate control unit 115, the vacuum exhaust unit 116, and the like are registered and stored in the storage unit 121.
The operation unit 122 performs various operation processes, and as an example thereof, calculates an average high-frequency power to be supplied from the microwave power source 101 for generating plasma, based on the product processing conditions stored in the storage unit 121.
The CPU123 controls the microwave power source 101, the electromagnetic coil 106, the high-frequency power source 110, the gas flow rate control unit 115, the vacuum exhaust unit 116, and the like, according to a program for processing the sample 107 in the plasma etching apparatus 100 stored in the storage unit 121 and product processing conditions.
The control unit 120 controls the microwave power source 101, the electromagnetic coil 106, the high-frequency power source 110, and the like based on the average high-frequency power calculated by the calculation unit 122.
In the plasma etching apparatus 100 having such a structure, first, microwave power is oscillated from the microwave power source 101, and the oscillated microwave power is transmitted to the etching chamber 104 through the waveguide 103.
A dielectric window 105 for sealing the etching gas in the lower portion of the etching chamber 104 is provided in the upper portion of the etching chamber 104, and the inside of the etching chamber 104 located below the dielectric window 105 is evacuated by a vacuum evacuation section 116 and kept in a vacuum state.
In the etching chamber 104 held in the vacuum state, the etching process gas whose flow rate is controlled by the gas flow rate control unit 115 is supplied from the gas supply unit 114 at a predetermined flow rate, and in this state, microwave power propagating through the waveguide 103 is transmitted through the dielectric window 105 and introduced into the etching chamber 104.
An electromagnetic coil 106 is disposed around the etching chamber 104. Electron cyclotron resonance is generated by the magnetic field formed in the etching chamber 104 by the electromagnetic coil 106 and the microwave power introduced into the etching chamber 104 through the dielectric window 105.
By the electron cyclotron resonance generated in the etching chamber 104, the etching gas introduced into the etching chamber 104 by the gas introduction means, not shown, can be efficiently plasmatized.
Fig. 2 is a cross-sectional view showing a schematic configuration of a wet etching apparatus 200 for wet etching processing in the present embodiment.
The wet etching apparatus 200 shown in fig. 2 includes a processing liquid tank 201 for storing an etching processing liquid 206, a supply pipe 202 for supplying the processing liquid to the processing liquid tank 201, a discharge pipe 203 for discharging the processing liquid from the processing liquid tank 201, a supply liquid flow rate adjusting unit 204 for adjusting a flow rate of the processing liquid supplied to the processing liquid tank 201 through the supply pipe 202, a discharge liquid flow rate adjusting unit 205 for adjusting a flow rate of the processing liquid discharged from the processing liquid tank 201 through the discharge pipe 203, a control unit 210 for controlling the supply liquid flow rate adjusting unit 204 and the discharge liquid flow rate adjusting unit 205, a sample loading tool 220 for loading a sample 221, and a sample loading tool driving unit 222 for controlling the sample loading tool 220 to be moved into and out of the etching processing liquid 206 stored in the processing liquid tank 201 by the control unit 210.
A method of forming a pattern of a nonvolatile material such as a compound semiconductor on a substrate by processing the nonvolatile material such as a compound semiconductor using the plasma etching apparatus 100 shown in fig. 1 and the wet etching apparatus 200 shown in fig. 2 will be described with reference to fig. 3 to 9.
In this embodiment, a compound semiconductor is described as including a group III-V compound semiconductor, a group II-VI compound semiconductor, a group III-VI compound semiconductor, an oxide semiconductor, a nitride semiconductor, and the like.
Fig. 3 shows the overall flow of the process. In this embodiment, a material in a state in which a layer 420 of a compound semiconductor material is formed on a substrate (e.g., a single crystal silicon substrate) 410 and a mask pattern 430 is formed thereon, such as that shown in fig. 7 (a) which shows its cross-sectional shape, is used as a sample of a processing object. In addition, an etch stop (stopper) layer is formed on the surface of the substrate (e.g., monocrystalline silicon substrate) 410.
First, in S310, the sample 107 having the mask pattern 430 formed on the surface thereof is processed by using the plasma etching apparatus 100 described in fig. 1, and the layer of the compound semiconductor material is subjected to anisotropic processing by performing plasma etching. The cross-sectional shape of the sample in the anisotropic processed state is shown in fig. 7 (b). In this state, the width of the substrate 410 is larger than the width of the mask pattern 430, and the cross-sectional shape is trapezoidal, resulting in etching residues.
Next, in S320, the plasma etching apparatus 100 is used to implant ions of a light element (hydrogen or helium) into the portion remaining by the etching, and as shown in fig. 7 (c), a damaged layer 423 is formed.
Finally, in S330, wet etching treatment is performed on the sample using the wet etching apparatus 200, and the damaged layer 423 formed in S320 is removed so as to have a shape as shown in fig. 7 (d).
Next, the details of the step S310 will be described with reference to the flowchart of fig. 4.
First, the sample 107 is carried into the plasma etching apparatus 100 shown in fig. 1 and placed on the sample stage 108 (S311). The section of the portion of the sample 107 where the mask pattern was formed at this time was in the shape shown in fig. 7 (a).
Next, a process gas (etching gas) is supplied from the gas supply unit 114 into the etching chamber 104 (S312). As the supplied process gas (etching gas), chlorine (C1 2 ) And hydrogen (H) 2 ) The mixed gas or chlorine (Cl) 2 ) Hydrogen (H) 2 ) And methane (CH) 4 ) The flow rate of the mixed gas is adjusted by the gas flow rate control unit 115 and supplied.
Next, the interior of the etching chamber 104 is evacuated by the evacuation section 116, and the interior of the etching chamber 104 is set to a predetermined pressure (S313).
In this state, the electromagnetic coil 106 disposed on the outer periphery of the etching chamber 104 generates a magnetic field inside the etching chamber 104, and the microwave power is supplied from the microwave power source 101 to the inside of the etching chamber 104 through the waveguide 103, so that plasma is generated inside the etching chamber 104, and discharge is started (S314).
The discharge state is monitored by an etching monitor (not shown), the light emission state (light emission spectrum signal intensity) of the plasma in the etching chamber 104 is monitored, and the detection of the end point of the etching process is continued (S315) until the end point is detected (no in S315).
When the end point of the etching process is detected from a detection signal of an etching monitor (not shown) (yes in S315), the generation of the magnetic field by the electromagnetic coil 106 is stopped, the supply of the microwave power from the microwave power source 101 is stopped, and the discharge of the interior of the etching process chamber 104 is terminated (S316). Next, the supply of the process gas (etching gas) into the etching chamber 104 is stopped (S317), and the process is terminated.
The cross section of the portion carrying the mask pattern of the sample 107 in this state is processed into the shape shown in fig. 7 (b). That is, the mask pattern 430 serves as a mask, and a portion of the layer 420 of the compound semiconductor material under the mask pattern 430 remains, and a portion not covered with the mask pattern 430 is removed by the plasma etching process.
Here, since the thickness (height) h of the pattern 421 of the compound semiconductor material is large (aspect ratio is large) with respect to the pitch p of the adjacent mask pattern 430, a difference occurs in etching amount between the nearer side and the farther side (the side closer to the substrate 410) of the mask pattern 430, and the layer 420 of the compound semiconductor material has a trapezoidal cross-sectional shape having a tapered side surface, as in the pattern 421, in which the width dimension of the side closer to the substrate 410 is large with respect to the width dimension of the side closer to the mask pattern 430, and etching residues are generated.
Next, a damaged layer forming process (S320) by plasma etching will be described with reference to the flowchart shown in fig. 5.
In a state where the sample 107 having completed the anisotropic processing step (S310) by plasma etching described in the process flow chart of fig. 4 is placed on the sample stage 108 in the etching chamber 104, a gas for forming a damaged layer is supplied from the gas supply unit 114 into the etching chamber 104 (S321).
Here, when argon (Ar) is used as the damage-causing gas, the gas is mixed with hydrogen (H 2 ) Since the damaged layer due to ion intrusion is formed only in the vicinity of the outermost surface because of the large atomic size and the shallow ion intrusion depth, a taper angle is generated due to etching residues (in fig. 7 (b), the inclination of the pattern 421The angle of the side surface with the surface of the substrate 410). Therefore, it is preferable to select a hydrogen (H) containing a small atomic radius and having a relatively large ion penetration depth 2 ) A light element gas system such as helium (He).
In this embodiment, as the supplied process gas, a mixed gas containing a light element (hydrogen or helium) is used.
Next, the interior of the etching chamber 104 is evacuated by the evacuation section 116, and the interior of the etching chamber 104 is set to a predetermined pressure (S322). Here, the set pressure is set so that ions generated in the plasma in the etching residue portion do not collide with other ions in a sheath region formed near the surface of the sample 107. That is, the pressure is set so that the mean free path of the ions becomes larger than the thickness of the sheath region.
Specifically, the mean free path L can be expressed as (expression 1).
[ number 1]
In addition, sheath length d is Can be expressed as (expression 2).
[ number 2]
In the above-mentioned formula (i), the formula (i),
ε 0 : vacuum dielectric constant, n p : plasma density, T: gas temperature, e: basic electric quantity, V: voltage referred to by sample, d: atomic radius, te: electron temperature, k B : boltzmann constant, p: pressure within the etch processing chamber.
Their values are respectively set as
ε 0 ＝8.85×10 -12 (F/m)、n p ＝5.0×10 16 (/m 3 )、T＝363(K)、e＝1.60×10 -19 (C)、V＝400(V)、T e ＝3.0(eV)、k B ＝1.38×10 -23 (m 2 ·kg/s 2 ·K)，
And try to find the average free path L and sheath length d is 。
In this embodiment, since the plasma etching apparatus 100 is used to implant ions of light elements (hydrogen, helium, or the like) into the portion remaining after the etching, the atomic radius of hydrogen is 1.06×10 when d is used -10 (m), the average free path L in the case of hydrogen is 2.28mm when the pressure p in the etching chamber is 44Pa, according to (equation 1). On the other hand, if the above value is substituted into (expression 2), the sheath length d is obtained is Then 2.24mm.
When the pressure p in the etching chamber 104 of the plasma etching apparatus 100 is 44Pa or less, the mean free path L in the case of hydrogen is longer than the sheath length d is Since ion collisions are not caused in the sheath region, normal incidence of hydrogen ions to the surface of the sample 107 can be expected.
Next, a magnetic field is generated inside the etching chamber 104 by the electromagnetic coil 106 disposed on the outer periphery of the etching chamber 104, and microwave power is supplied from the microwave power source 101 to the inside of the etching chamber 104 through the waveguide 103, so that plasma is generated inside the etching chamber 104, and discharge is started (S323). Meanwhile, in order to introduce ions in the plasma to the sample 107, high-frequency power is applied from the high-frequency power supply 110 to the sample stage 108 (S324).
Here, a relationship between ion energy and ion penetration depth obtained in simulation will be described with reference to fig. 8 and 9.
FIG. 8 shows the In pair 0.53 Ga 0.47 The material of As is irradiated with hydrogen (H 2 ) A plot of ion energy versus ion intrusion depth for ions. If the ion energy is increased, the ion penetration depth becomes deep. From this graph, it is clear that, for example, in order to secure an ion penetration depth of 20nm, it is necessary to set the ion energy to 200eV or more.
On the other hand, fig. 9 is a view showing high-frequency power applied from the high-frequency power supply 110 to the sample stage 108 in order to introduce ions in plasma to the sample 107: a graph of W-RF versus ion energy of hydrogen ions incident on the surface of the sample 107 mounted on the sample stage 108.
The graph shown in fig. 9 shows the result of actual measurement performed by using the plasma etching apparatus 100 shown in fig. 1, in the case where hydrogen (H 2 ) The flow rate of (2) was 550ccm, the pressure inside the etching chamber 104 was 3.0Pa, and the microwave power supplied from the microwave power supply 101 was set to be 3.0 Pa: MW was set to 600W.
From this figure, it can be seen that in order to make hydrogen (H 2 ) The ion energy of (2) is 200eV or more, and the high-frequency power applied from the high-frequency power supply 110 to the sample stage 108 must be set to: W-RF is 160W or more.
Here, microwave power of 2.45GHz is supplied from the microwave power supply 101 to the interior of the etching chamber 104. At this time, a magnetic field is formed inside the etching chamber 104 by the electromagnetic coil 106, so that the ECR condition is established for the microwave power. By supplying microwave power to such a magnetic field, a high-density plasma is generated inside the etching chamber 104.
In this way, when the frequency of the high-frequency power applied from the high-frequency power source 110 to the sample stage 108 is 400KHz in a state where the microwave power is supplied so that the high-density plasma is generated, the influence on the high-density plasma generated in the etching chamber 104 by the high-frequency power is small, and therefore, the energy of ions incident on the sample 107 can be independently controlled by the high-frequency power applied from the high-frequency power source 110 to the sample stage 108.
When the sample 107 is irradiated with ions under such conditions, the ions are incident substantially perpendicularly to the surface of the sample 107, and therefore, as shown in fig. 7 (c), the tapered portions on both sides of the pattern 422 intrude into the ions incident substantially perpendicularly to the surface of the sample 107, forming the damaged layer 423.
After ion irradiation is performed for a predetermined period of time, formation of the damaged layer is terminated (yes in S325), generation of the magnetic field by the electromagnetic coil 106 is stopped, supply of microwave power from the microwave power source 101 is stopped, application of high-frequency power from the high-frequency power source 110 to the sample stage 108 is stopped, and discharge inside the etching chamber 104 is stopped (S326).
Further, the supply of the gas from the gas supply unit 114 into the etching chamber 104 is stopped (S327), and the processed sample 107 is carried out of the etching chamber 104 (S328), and the damaged layer formation step using the plasma etching apparatus is completed (S320).
Next, with reference to fig. 6, the details of the selective removal process (S330) of the damaged layer using the wet etching apparatus, in which the damaged layer formed in S320 is selectively removed by wet etching, will be described.
First, a plurality of samples 107 (shown as samples 221 in fig. 2) processed in the step of forming a damaged layer using a plasma etching apparatus (S320) are mounted on the sample loading tool 220 of the wet etching apparatus 200 shown in fig. 2 and set (S331).
Next, the control unit 210 controls the driving of the sample loading tool driving unit 222 to lower the sample loading tool 220 into the etching treatment liquid 206 stored in the treatment liquid tank 201, and the wet etching is started by immersing all of the plurality of samples 221 in the etching treatment liquid 206 (S332).
When the sample 221 is immersed in the etching solution 206, the damaged layer 423 can be removed by the etching solution 206. At this time, although the portions other than the damaged layer 423 are also etched, the damaged layer 423 can be selectively etched because the etching rate of the damaged layer 423 is larger (etching selectivity ratio is larger) than that of the other portions.
After immersing the sample 221 in the etching processing liquid 206 for a predetermined period of time (yes in S333), the control unit 210 controls the sample loading tool driving unit 222 to raise the sample loading tool 220, and lifts the sample 221 from the processing liquid tank 201 (S334).
Finally, the wet-etched sample 221 is taken out from the sample loading tool 220 (S335), and the selective removal process of the damaged layer using the wet etching apparatus is completed (S330).
According to the present embodiment, vertical processing of a pattern on a sample can be achieved by anisotropic processing based on plasma etching and selective removal process of a damaged layer based on wet etching. In addition, by performing the wet etching step after the plasma etching, the unnecessary damaged layer can be removed at the same time.
In the above example, as shown in fig. 3, after the anisotropic processing is performed using the plasma etching apparatus 100 in S310, the damaged layer is formed using the same plasma etching apparatus 100 in S320, but the damaged layer may be formed in the portion of fig. 7 (a) not covered with the mask pattern 430 by performing S320, and then the anisotropic etching of S310 is performed on the damaged layer-formed portion.
According to the present embodiment, it becomes possible to vertically process a high mobility channel material including a compound semiconductor which is low in volatility and difficult in anisotropic processing.
Further, according to the present embodiment, since the light element can be made into plasma in an atmosphere at a desired pressure and ions in the plasma are perpendicularly incident to form a damaged layer under such a condition that ion collision in the sheath region does not occur, the damaged layer can be generated only at a portion not covered with the mask, and thus vertical processing can be realized.
Further, since the formed damaged layer is removed by a wet etching process, a high-temperature process is not required, and resistance to a high temperature is not required as a mask material, so that a selection range of the mask material can be enlarged as compared with the conventional one, and for example, a photoresist can be used.
Further, although the microwave ECR plasma etching apparatus is described as an example in this embodiment, the same effects as in this embodiment can be obtained in a plasma processing apparatus in other plasma generation systems such as a capacitive coupling type plasma and an inductive coupling type plasma.
In the present embodiment, the description has been made with an example in which the substrate is disposed below the compound semiconductor material and the mask pattern is formed above the compound semiconductor material, but in the present invention, the mask pattern is not necessarily required to be above the compound semiconductor material, and the substrate is not necessarily required to be below the compound semiconductor material.
Example 2
In example 1, a method of performing anisotropic processing and formation of a damaged layer using the plasma etching apparatus 100 and selectively removing the damaged layer by a wet etching process using the wet etching apparatus 200 is described, but in this example, a method of removing the damaged layer by a reaction with a radical (chemical) is described.
The anisotropic processing and damaged layer formation steps using the plasma etching apparatus 100 in this embodiment are the same as those described in embodiment 1, and therefore, description thereof is omitted.
Fig. 10 shows a structure of a plasma processing apparatus 1000 for removing a damaged layer by a reaction with radicals, which is used in this example.
The plasma processing apparatus 1000 according to the present embodiment includes a plasma processing chamber 1100 including a plasma generation chamber 1110 and a radical irradiation chamber 1120, and a substrate sample stage 1121 on which a sample 107 is placed and an insulating block 1122 that insulates between the substrate sample stage 1121 and the radical irradiation chamber 1120 are disposed inside the radical irradiation chamber 1120. A high-frequency power source 1160 is connected to the substrate sample stage 1121.
A coil (spiral coil) 1130 is arranged on the outer periphery of the plasma generation chamber 1110, and high-frequency power (for example, high-frequency power having a frequency of 13.56 MHz) is applied to the coil 1130 from a coil power supply 1131, so that plasma is generated inside the plasma generation chamber 1110.
The plasma generation chamber 1110 is provided with a gas supply nozzle 1140 for supplying a gas for generating plasma (for example, argon gas: ar) to the inside. The flow rate of the gas supplied from the gas supply nozzle 1140 into the plasma generation chamber 1110 is controlled by the gas flow rate control unit 1141.
A porous plate 1132 is disposed inside the plasma processing chamber 1100 to separate the plasma generating chamber 1110 and the radical irradiation chamber 1120, wherein the porous plate 1132 includes a conductor such as a metal, and a plurality of small holes 1133 are formed. The porous plate 1132 and the plasma generation chamber 1110 are electrically connected.
A vacuum pump 1150 is connected to the radical irradiation chamber 1120, and the inside of the radical irradiation chamber 1120 and the inside of the plasma generation chamber 1110 are evacuated.
The coil power supply 1131, the gas flow controller 1141, the vacuum pump 1150, and the high-frequency power supply 1160 are controlled by the controller 1170, respectively.
In the plasma processing apparatus 1000 having such a configuration, the inside of the radical irradiation chamber 1120 and the inside of the plasma generation chamber 1110 are evacuated by operating the vacuum exhaust pump 1150, and the gas whose flow rate is controlled by the gas flow rate control unit 1141 is supplied from the gas supply nozzle 1140 to the inside of the plasma generation chamber 1110.
When high-frequency power is applied to the coil 1130 from the coil power supply 1131 in a state where the pressure inside the plasma generation chamber 1110 to which the gas is supplied from the gas supply nozzle 1140 is a predetermined pressure, inductively coupled plasma is generated inside the plasma generation chamber 1110.
Here, many small holes 1133 formed in the porous plate 1132 are formed to such a size that ions in the inductively coupled plasma generated inside the plasma generation chamber 1110 cannot pass. On the other hand, neutral radicals can be supplied to the radical irradiation chamber 1120 side through many small holes 1133 formed in the porous plate 1132 from inductively coupled plasma generated inside the plasma generation chamber 1110.
As the sample 107 placed on the substrate sample stage 1121, if the sample is a sample having the damage layer 423 formed as shown in fig. 7 (c) in example 1, the damage layer 423 is selectively etched to be processed into a shape as shown in fig. 7 (d) by radicals supplied from the inductively coupled plasma region of the plasma generating chamber 1110 to the radical irradiation chamber 1120 side through a plurality of small holes 1133.
Fig. 11 shows a process flow of the present embodiment corresponding to the flowchart 3 in the embodiment 1. The anisotropic processing step (S510) using the plasma processing apparatus and the damaged layer forming step (S520) using the plasma processing apparatus are the same as steps S310 and S320 described in example 1, respectively.
On the other hand, the process described above is performed in the selective removal step (S530) of the damaged layer using the plasma processing apparatus. That is, the damaged layer 423 formed on the sample 107 is selectively etched and removed by radicals supplied from the inductively coupled plasma generated in the plasma generation chamber 1110 to the radical irradiation chamber 1120 side through the small holes 1133 of the porous plate 1132 using the plasma processing apparatus 1000.
The detailed operation of step S530 is described with reference to fig. 12.
First, the sample 107 is carried into the radical irradiation chamber 1120 of the plasma processing apparatus 1000 shown in fig. 10 and placed on the substrate sample stage 1121 (S531). The section of the portion of the sample 107 where the mask pattern was formed was in the shape of the damaged layer 423 as shown in fig. 7 (c).
Next, the inside of the radical irradiation chamber 1120 and the plasma generation chamber 1110 is evacuated by the vacuum exhaust pump 1150, and a gas for plasma discharge is supplied from the gas supply nozzle 1140 to the inside of the plasma generation chamber 1110 (S532). As the gas for plasma discharge to be supplied, a gas capable of selectively removing the damaged layer by a reaction with radicals is used, and the flow rate is adjusted by the gas flow rate control unit 1141 to supply the gas.
Next, in a state where a gas for plasma discharge is supplied into the plasma generation chamber 1110, the insides of the radical irradiation chamber 1120 and the plasma generation chamber 1110 are evacuated by the vacuum exhaust pump 1150, whereby the insides of the radical irradiation chamber 1120 and the plasma generation chamber 1110 are set to a predetermined pressure (S533).
In this state, high-frequency power is applied from the coil power supply 1131 to the coil 1130 disposed on the outer peripheral portion of the plasma generation chamber 1110, so that inductively coupled plasma is generated inside the plasma generation chamber 1110, and discharge is started (S534).
After the discharge is continued for a predetermined period of time (yes in S535), the application of high-frequency power from the coil power supply 1131 to the coil 1130 is stopped, and the discharge inside the plasma generation chamber 1110 is terminated (S536). Next, the supply of the process gas (etching gas) into the plasma generation chamber 1110 is stopped (S537).
The damaged layer 423 was removed from the cross section of the portion carrying the mask pattern of the sample 107 in this state, and was processed into a shape as shown in fig. 7 (d).
Finally, the sample 107 from which the damaged layer 423 was removed is taken out of the substrate sample stage 1121, and carried out of the plasma processing apparatus 1000 (S538), and a series of processes is terminated.
According to this example, as in the case of example 1, it becomes possible to vertically process a channel material with high mobility including a compound semiconductor having low volatility and difficult anisotropic processing.
In this example, as in the case of example 1, the light element can be made into plasma in an atmosphere at a desired pressure, and ions in the plasma are made to enter vertically under such a condition that ion collisions in the sheath region do not occur, so that a damaged layer can be formed only in a region not covered with a mask, and vertical processing can be realized.
Further, since the formed damaged layer is removed by a reaction with radicals by a plasma process, a high-temperature process is not required, and resistance to a high temperature is not required as a mask material, and thus, a selection range of the mask material can be widened as compared with the conventional one, and for example, a photoresist can be used.
Further, the same effects as those of the present embodiment can be obtained also in the plasma processing apparatus in the plasma generation system such as the microwave ECR plasma, the capacitive coupling plasma, or the inductive coupling plasma. In addition, in the remote plasma processing apparatus, the same effects as those of the present embodiment can be obtained.
While the compound semiconductor material was described as an example as the material to be etched in examples 1 and 2, the present invention is not limited to the improvement of the taper shape by etching with a material that is difficult to volatilize, and the present invention can be applied to the improvement of the taper shape of a material that is generally used in a semiconductor manufacturing process.
For example, the present invention can be applied to Si, siGe, ge, siN, siO used in the front-end process 2 Or a Low-k material such as SiOC, siON, siOCN used as an interlayer film in a back-end process.
The present invention is not limited to the above-described embodiments, and various modifications are included. For example, the above-described embodiments are described in detail for the purpose of easily understanding the present invention, and are not limited to the configuration in which all the described structures are necessarily provided. In addition, deletion, and substitution of other structures can be performed on a part of the structure of example 1.

Claims (5)

1. A method for manufacturing a semiconductor device is characterized by comprising:
etching the semiconductor material using the plasma;
forming a damaged layer on a sidewall of the etched semiconductor material using a plasma generated from hydrogen or helium; and
and removing the damaged layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein,
the step of removing the damaged layer is performed by wet etching.
3. The method for manufacturing a semiconductor device according to claim 1, wherein,
the semiconductor material is a compound semiconductor material.
4. The method for manufacturing a semiconductor device according to claim 3, wherein,
the etching step is performed using a mixed gas of chlorine and hydrogen or a mixed gas of chlorine, hydrogen, and methane gas.
5. The method for manufacturing a semiconductor device according to claim 1, wherein,
the step of removing the damaged layer is performed using plasma.
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